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authorPan Li <pan2.li@intel.com>2024-01-30 15:42:06 +0800
committerPan Li <pan2.li@intel.com>2024-01-30 21:48:28 +0800
commit7bfea0aedbce3f33a783bbb47f39724a58d19f73 (patch)
treed0e62ba174977bb3c252e33b566df26a97446970 /gcc/c
parent9f382376660069e49290fdb51861abdec63519c7 (diff)
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RISC-V: Bugfix for vls mode aggregated in GPR calling convention
According to the issue as below. https://hub.fgit.cf/riscv-non-isa/riscv-elf-psabi-doc/pull/416 When the mode size of vls integer mode is less than 2 * XLEN, we will take the gpr for both the args and the return values. Instead of the reference. For example the below code: typedef short v8hi __attribute__ ((vector_size (16))); v8hi __attribute__((noinline)) add (v8hi a, v8hi b) { v8hi r = a + b; return r; } Before this patch: add: vsetivli zero,8,e16,m1,ta,ma vle16.v v1,0(a1) <== arg by reference vle16.v v2,0(a2) <== arg by reference vadd.vv v1,v1,v2 vse16.v v1,0(a0) <== return by reference ret After this patch: add: addi sp,sp,-32 sd a0,0(sp) <== arg by register a0 - a3 sd a1,8(sp) sd a2,16(sp) sd a3,24(sp) addi a5,sp,16 vsetivli zero,8,e16,m1,ta,ma vle16.v v2,0(sp) vle16.v v1,0(a5) vadd.vv v1,v1,v2 vse16.v v1,0(sp) ld a0,0(sp) <== return by a0 - a1. ld a1,8(sp) addi sp,sp,32 jr ra For vls floating point, we take the same rules as integer and passed by the gpr or reference. The riscv regression passed for this patch. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to calculate the gpr count required by vls mode. (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode. (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr for vls mode. (riscv_get_arg_info): Add vls mode handling. (riscv_pass_by_reference): Return false if arg info has no zero gpr count. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/def.h: Add new helper macro. * gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c: New test. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
Diffstat (limited to 'gcc/c')
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