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| author | Fei Gao <gaofei@eswincomputing.com> | 2023-12-10 13:39:30 -0700 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2023-12-10 13:41:01 -0700 |
| commit | 5a4faf915575c690a25f0522dccc5b8d82909f10 (patch) | |
| tree | 15237d529e1fe877057a0410c023c84d67b35d2e /gcc/c | |
| parent | b3aed459634654d295a1d00e6c149565ced7a9a2 (diff) | |
| download | gcc-5a4faf915575c690a25f0522dccc5b8d82909f10.zip gcc-5a4faf915575c690a25f0522dccc5b8d82909f10.tar.gz gcc-5a4faf915575c690a25f0522dccc5b8d82909f10.tar.bz2 | |
[PATCH 2/5] [ifcvt] optimize x=c ? (y shift_op z):y by RISC-V Zicond like insns
op=[ASHIFT, ASHIFTRT, LSHIFTRT, ROTATE, ROTATERT]
Conditional op, if zero
rd = (rc == 0) ? (rs1 op rs2) : rs1
-->
czero.nez rd, rs2, rc
op rd, rs1, rd
Conditional op, if non-zero
rd = (rc != 0) ? (rs1 op rs2) : rs1
-->
czero.eqz rd, rs2, rc
op rd, rs1, rd
gcc/ChangeLog:
* ifcvt.cc (noce_cond_zero_binary_op_supported): Add support for shift
like op.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zicond_ifcvt_opt.c: Add tests for shift like op.
Co-authored-by: Xiao Zeng<zengxiao@eswincomputing.com>
Diffstat (limited to 'gcc/c')
0 files changed, 0 insertions, 0 deletions