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| author | Jin Ma <jinma@linux.alibaba.com> | 2023-11-17 15:33:25 +0800 |
|---|---|---|
| committer | Christoph Müllner <christoph.muellner@vrull.eu> | 2024-01-10 18:55:07 +0100 |
| commit | 52e809d5cf345ce01fc81be716a57f5b6d5b4545 (patch) | |
| tree | da79eaa020c69f80976c942ce402b7b02808f4cb /gcc/c | |
| parent | 7cbe41d35e6a60776484e04e42e408de9fc82954 (diff) | |
| download | gcc-52e809d5cf345ce01fc81be716a57f5b6d5b4545.zip gcc-52e809d5cf345ce01fc81be716a57f5b6d5b4545.tar.gz gcc-52e809d5cf345ce01fc81be716a57f5b6d5b4545.tar.bz2 | |
RISC-V: T-HEAD: Add support for the XTheadInt ISA extension
The XTheadInt ISA extension provides the following instructions
to accelerate interrupt processing:
* th.ipush
* th.ipop
Ref:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf
gcc/ChangeLog:
* config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
(th_int_get_save_adjustment): Likewise.
(th_int_adjust_cfi_prologue): Likewise.
* config/riscv/riscv.cc (BITSET_P): Moved away from here.
(TH_INT_INTERRUPT): New macro.
(riscv_expand_prologue): Add the processing of XTheadInt.
(riscv_expand_epilogue): Likewise.
* config/riscv/riscv.h (BITSET_P): Moved to here.
* config/riscv/riscv.md: New unspec.
* config/riscv/thead.cc (th_int_get_mask): New function.
(th_int_get_save_adjustment): Likewise.
(th_int_adjust_cfi_prologue): Likewise.
* config/riscv/thead.md (th_int_push): New pattern.
(th_int_pop): new pattern.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadint-push-pop.c: New test.
Diffstat (limited to 'gcc/c')
0 files changed, 0 insertions, 0 deletions