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| author | Haochen Gui <guihaoc@gcc.gnu.org> | 2023-12-11 08:40:34 +0800 |
|---|---|---|
| committer | Haochen Gui <guihaoc@gcc.gnu.org> | 2023-12-11 08:46:10 +0800 |
| commit | 46e342b985e6b4058db73875103cced2666e84e2 (patch) | |
| tree | 27fd48c21a1d5b50e123130613c337ab9fe1065c /gcc/c | |
| parent | 4a6613e2a417512077ea39b5097c0c602055f028 (diff) | |
| download | gcc-46e342b985e6b4058db73875103cced2666e84e2.zip gcc-46e342b985e6b4058db73875103cced2666e84e2.tar.gz gcc-46e342b985e6b4058db73875103cced2666e84e2.tar.bz2 | |
rs6000: Enable lrint<mode>si2 on old archs with stfiwx enabled
The powerpc 32-bit processors (e.g. 5470) supports "fctiw" instruction,
but the instruction can't be generated on such platforms as the insn is
guard by TARGET_POPCNTD. The root cause is SImode in float register is
supported from Power7. Actually implementation of "fctiw" only needs
stfiwx which is supported by the old 32-bit processors. This patch
enables "fctiw" expand for these processors.
gcc/
PR target/112707
* config/rs6000/rs6000.md (expand lrint<mode>si2): New.
(insn lrint<mode>si2): Rename to...
(*lrint<mode>si): ...this.
(lrint<mode>si_di): New.
gcc/testsuite/
PR target/112707
* gcc.target/powerpc/pr112707-1.c: New.
Diffstat (limited to 'gcc/c')
0 files changed, 0 insertions, 0 deletions