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author | demin.han <demin.han@starfivetech.com> | 2024-03-06 17:34:34 +0800 |
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committer | demin.han <demin.han@starfivetech.com> | 2024-03-08 10:31:43 +0800 |
commit | 42187c6968af9907de1f9b7563d87de739857684 (patch) | |
tree | 39cb15eb34a61396915fe93525930076f094533c /gcc/c | |
parent | a0e945888d973fc1a4a9d2944aa7e96d2a4d7581 (diff) | |
download | gcc-42187c6968af9907de1f9b7563d87de739857684.zip gcc-42187c6968af9907de1f9b7563d87de739857684.tar.gz gcc-42187c6968af9907de1f9b7563d87de739857684.tar.bz2 |
RISC-V: Fix ICE in riscv vector costs
The following code can result in ICE:
-march=rv64gcv --param riscv-autovec-lmul=dynamic -O3
char *jpeg_difference7_input_buf;
void jpeg_difference7(int *diff_buf) {
unsigned width;
int samp, Rb;
while (--width) {
Rb = samp = *jpeg_difference7_input_buf;
*diff_buf++ = -(int)(samp + (long)Rb >> 1);
}
}
One biggest_mode update missed in one branch and trigger assertion fail.
gcc_assert (biggest_size >= mode_size);
Tested On RV64 and no regression.
PR target/114264
gcc/ChangeLog:
* config/riscv/riscv-vector-costs.cc: Fix ICE
gcc/testsuite/ChangeLog:
* gcc.dg/vect/costmodel/riscv/rvv/pr114264.c: New test.
Signed-off-by: demin.han <demin.han@starfivetech.com>
Diffstat (limited to 'gcc/c')
0 files changed, 0 insertions, 0 deletions