I386: Add more testcases for unsigned SAT_ADD vector pattern

Some forms like below failed to be recognized as a SAT_ADD pattern
for target i386.  It is related to some match pattern
extraction but get fixed after the refactor of the SAT_ADD
pattern.  Thus, add testcases to ensure we won't have similar
issues in the future.

  #define DEF_SAT_ADD(T)   \
  T sat_add_##T (T x, T y) \
  {                        \
    T res;                 \
    res = x + y;           \
    res |= -(T)(res < x);  \
    return res;            \
  }

  #define VEC_DEF_SAT_ADD(T)                       \
  void vec_sat_add(T * restrict a, T * restrict b) \
  {                                                \
    for (int i = 0; i < 8; i++)                    \
      b[i] = sat_add_##T (a[i], b[i]);             \
  }

  DEF_SAT_ADD (uint32_t)
  VEC_DEF_SAT_ADD (uint32_t)

The below test suites are passed for this patch.
make -k check-gcc RUNTESTFLAGS="--target_board=unix\{,-m32\} i386.exp=pr112600-5a-*.c"

	PR target/112600

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr112600-5-u16.c: New test.
	* gcc.target/i386/pr112600-5-u32.c: New test.
	* gcc.target/i386/pr112600-5-u64.c: New test.
	* gcc.target/i386/pr112600-5-u8.c: New test.
	* gcc.target/i386/pr112600-5.h: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

0 files changed, 0 insertions, 0 deletions