diff options
| author | Max Filippov <jcmvbkbc@gmail.com> | 2020-04-13 13:26:04 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2020-04-14 16:55:40 -0700 |
| commit | a288e202c5e50704968685fc2922d159335be2cb (patch) | |
| tree | 052fab83de36d97b4b78981d3280f6bbff50fce9 /gcc/c/c-parser.c | |
| parent | ae046fa25e5d4a905cc7fab028d0f92cb21dc972 (diff) | |
| download | gcc-a288e202c5e50704968685fc2922d159335be2cb.zip gcc-a288e202c5e50704968685fc2922d159335be2cb.tar.gz gcc-a288e202c5e50704968685fc2922d159335be2cb.tar.bz2 | |
xtensa: fix PR target/94584
Patterns zero_extendhisi2, zero_extendqisi2 and extendhisi2_internal can
load value from memory, but they don't treat volatile memory correctly.
Add %v1 before load instructions to emit 'memw' instruction when
-mserialize-volatile is in effect.
2020-04-14 Max Filippov <jcmvbkbc@gmail.com>
gcc/
* config/xtensa/xtensa.md (zero_extendhisi2, zero_extendqisi2)
(extendhisi2_internal): Add %v1 before the load instructions.
gcc/testsuite/
* gcc.target/xtensa/pr94584.c: New test.
Diffstat (limited to 'gcc/c/c-parser.c')
0 files changed, 0 insertions, 0 deletions