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author | Edwin Lu <ewlu@rivosinc.com> | 2023-09-05 10:09:40 -0700 |
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committer | Edwin Lu <ewlu@rivosinc.com> | 2023-09-05 10:09:40 -0700 |
commit | decbf9ec81f33052be12296b89cd86ea65ae10da (patch) | |
tree | 63038135d4d144cffc65bae741ab8d647df16e64 /gcc/c/c-decl.cc | |
parent | c85db606d46774283ca4ec037dc3051719828f41 (diff) | |
download | gcc-decbf9ec81f33052be12296b89cd86ea65ae10da.zip gcc-decbf9ec81f33052be12296b89cd86ea65ae10da.tar.gz gcc-decbf9ec81f33052be12296b89cd86ea65ae10da.tar.bz2 |
RISC-V: Add Types to Un-Typed Risc-v Instructions
Updates risc-v instructions to ensure that no instruction is left
without a type attribute. Added new types "trap" and "cbo" (for
cache related instructions)
Tested for regressions using rv32/64 multilib with newlib/linux and
rv32/64 gcv for linux.
gcc/Changelog:
* config/riscv/riscv.md: Update/Add types
Reviewed-by: Jeff Law <jlaw@ventanamicro.com>
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
Diffstat (limited to 'gcc/c/c-decl.cc')
0 files changed, 0 insertions, 0 deletions