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| author | Xi Ruoyao <xry111@xry111.site> | 2024-02-03 03:35:07 +0800 |
|---|---|---|
| committer | Xi Ruoyao <xry111@xry111.site> | 2024-02-05 19:41:08 +0800 |
| commit | 4d7fe3cf82505b45719356a2e51b1480b5ee21d6 (patch) | |
| tree | 3b3526b01b68a23ac7eb058a561a8f0c629494b9 /gcc/c/c-decl.cc | |
| parent | 42959acb8409c39e1c71c43528832611c3b71e25 (diff) | |
| download | gcc-4d7fe3cf82505b45719356a2e51b1480b5ee21d6.zip gcc-4d7fe3cf82505b45719356a2e51b1480b5ee21d6.tar.gz gcc-4d7fe3cf82505b45719356a2e51b1480b5ee21d6.tar.bz2 | |
MIPS: Fix wrong MSA FP vector negation
We expanded (neg x) to (minus const0 x) for MSA FP vectors, this is
wrong because -0.0 is not 0 - 0.0. This causes some Python tests to
fail when Python is built with MSA enabled.
Use the bnegi.df instructions to simply reverse the sign bit instead.
gcc/ChangeLog:
* config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
(neg<mode>2): Change the mode iterator from MSA to IMSA because
in FP arithmetic we cannot use (0 - x) for -x.
(neg<mode>2): New define_insn to implement FP vector negation,
using a bnegi instruction to negate the sign bit.
Diffstat (limited to 'gcc/c/c-decl.cc')
0 files changed, 0 insertions, 0 deletions