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| author | Roger Sayle <roger@eyesopen.com> | 2005-03-12 04:56:29 +0000 |
|---|---|---|
| committer | Roger Sayle <sayle@gcc.gnu.org> | 2005-03-12 04:56:29 +0000 |
| commit | 210e185272bc34731909e0a53fb982d3ae434516 (patch) | |
| tree | 96386c408166b9b5428a6ddf7d05ea299cb137d7 /gcc/builtins.c | |
| parent | 7999e310bf46cdd9fd435b7d0f56ad4c72054748 (diff) | |
| download | gcc-210e185272bc34731909e0a53fb982d3ae434516.zip gcc-210e185272bc34731909e0a53fb982d3ae434516.tar.gz gcc-210e185272bc34731909e0a53fb982d3ae434516.tar.bz2 | |
re PR middle-end/20419 (ICE in gen_lowpart_general, at rtlhooks.c:58)
PR middle-end/20419
* builtins.c (expand_builtin_signbit): Force the signbit's word
into an integer register to avoid SUBREGs of floating point modes.
From-SVN: r96328
Diffstat (limited to 'gcc/builtins.c')
| -rw-r--r-- | gcc/builtins.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/gcc/builtins.c b/gcc/builtins.c index 4f46474..e6e0717 100644 --- a/gcc/builtins.c +++ b/gcc/builtins.c @@ -5003,6 +5003,11 @@ expand_builtin_signbit (tree exp, rtx target) bitpos = bitpos % BITS_PER_WORD; } + /* Force the intermediate word_mode (or narrower) result into a + register. This avoids attempting to create paradoxical SUBREGs + of floating point modes below. */ + temp = force_reg (imode, temp); + /* If the bitpos is within the "result mode" lowpart, the operation can be implement with a single bitwise AND. Otherwise, we need a right shift and an AND. */ |