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| author | Pekka Jääskeläinen <visit0r@gcc.gnu.org> | 2017-05-04 05:50:21 +0000 |
|---|---|---|
| committer | Pekka Jääskeläinen <visit0r@gcc.gnu.org> | 2017-05-04 05:50:21 +0000 |
| commit | c6e334cdb1177c9722cef5e5f7153986edd5e5d3 (patch) | |
| tree | f572c282c5f13374d670fc370b9d69d10a340c7c /gcc/brig | |
| parent | 1738af6048162cadc20913d41320a38b40a50fc4 (diff) | |
| download | gcc-c6e334cdb1177c9722cef5e5f7153986edd5e5d3.zip gcc-c6e334cdb1177c9722cef5e5f7153986edd5e5d3.tar.gz gcc-c6e334cdb1177c9722cef5e5f7153986edd5e5d3.tar.bz2 | |
Minor BRIG/HSAIL frontend updates and bug fixes:
* brig-builtins.def: Added a builtin for class_f64.
* builtin-types.def: Added a builtin type needed by class_f64.
* brigfrontend/brig-code-entry-handler.cc
(brig_code_entry_handler::build_address_operand): Fix a bug
with reg+offset addressing on 32b segments. In large mode,
the offset is treated as 32bits unless it's global, readonly or
kernarg address space.
* rt/workitems.c: Removed a leftover comment.
* rt/arithmetic.c (__hsail_class_f32, __hsail_class_f64): Fix the
check for signaling/non-signalling NaN. Add class_f64 default
implementation.
From-SVN: r247576
Diffstat (limited to 'gcc/brig')
| -rw-r--r-- | gcc/brig/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/brig/brigfrontend/brig-code-entry-handler.cc | 23 |
2 files changed, 30 insertions, 1 deletions
diff --git a/gcc/brig/ChangeLog b/gcc/brig/ChangeLog index 9f9a27e..338873e 100644 --- a/gcc/brig/ChangeLog +++ b/gcc/brig/ChangeLog @@ -1,3 +1,11 @@ +2017-05-03 Pekka Jääskeläinen <visit0r@kamu> + + * brigfrontend/brig-code-entry-handler.cc + (brig_code_entry_handler::build_address_operand): Fix a bug + with reg+offset addressing on 32b segments. In large mode, + the offset is treated as 32bits unless it's global, readonly or + kernarg address space. + 2016-02-01 Pekka Jääskeläinen <pekka.jaaskelainen@parmance.com> * brigfrontend/brig-code-entry-handler.cc: fix address diff --git a/gcc/brig/brigfrontend/brig-code-entry-handler.cc b/gcc/brig/brigfrontend/brig-code-entry-handler.cc index 08e49f9..3abd80e 100644 --- a/gcc/brig/brigfrontend/brig-code-entry-handler.cc +++ b/gcc/brig/brigfrontend/brig-code-entry-handler.cc @@ -464,7 +464,24 @@ brig_code_entry_handler::build_address_operand uint64_t offs = gccbrig_to_uint64_t (addr_operand.offset); if (offs > 0 || addr == NULL_TREE) { - tree const_offset_2 = build_int_cst (size_type_node, offs); + /* In large mode, the offset is treated as 32bits unless it's + global, readonly or kernarg address space. + See: + http://www.hsafoundation.com/html_spec111/HSA_Library.htm + #PRM/Topics/02_ProgModel/small_and_large_machine_models.htm + #table_machine_model_data_sizes */ + + int is64b_offset = segment == BRIG_SEGMENT_GLOBAL + || segment == BRIG_SEGMENT_READONLY + || segment == BRIG_SEGMENT_KERNARG; + + /* The original offset is signed and should be sign + extended for the pointer arithmetics. */ + tree const_offset_2 = is64b_offset + ? build_int_cst (size_type_node, offs) + : convert (long_integer_type_node, + build_int_cst (integer_type_node, offs)); + if (addr == NULL_TREE) addr = const_offset_2; else @@ -1265,6 +1282,10 @@ brig_code_entry_handler::build_operands (const BrigInstBase &brig_inst) operand_type = uint32_type_node; half_to_float = false; } + else if (brig_inst.opcode == BRIG_OPCODE_ACTIVELANEPERMUTE && i == 4) + { + operand_type = uint32_type_node; + } else if (half_to_float) /* Treat the operands as the storage type at this point. */ operand_type = half_storage_type; |