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| author | Tamar Christina <tamar.christina@arm.com> | 2021-02-01 13:50:43 +0000 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2021-02-01 13:50:43 +0000 |
| commit | 0a3eccb6ef9351cf8668eede8060dd7481794cd2 (patch) | |
| tree | 3097d45da393854ac6d9d5f4eb7cfe7d67d8c7c6 /gcc/bitmap.h | |
| parent | 1b303ef6cc8a5913345cbcd91abf13075ab2aec9 (diff) | |
| download | gcc-0a3eccb6ef9351cf8668eede8060dd7481794cd2.zip gcc-0a3eccb6ef9351cf8668eede8060dd7481794cd2.tar.gz gcc-0a3eccb6ef9351cf8668eede8060dd7481794cd2.tar.bz2 | |
AArch64: Change canonization of smlal and smlsl in order to be able to optimize the vec_dup
g:87301e3956d44ad45e384a8eb16c79029d20213a and
g:ee4c4fe289e768d3c6b6651c8bfa3fdf458934f4 changed the intrinsics to be
proper RTL but accidentally ended up creating a regression because of the
ordering in the RTL pattern.
The existing RTL that combine should try to match to remove the vec_dup is
aarch64_vec_<su>mlal_lane<Qlane> and aarch64_vec_<su>mult_lane<Qlane> which
expects the select register to be the second operand of mult.
The pattern introduced has it as the first operand so combine was unable to
remove the vec_dup. This flips the order such that the patterns optimize
correctly.
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md (aarch64_<su>mlal_n<mode>,
aarch64_<su>mlsl<mode>, aarch64_<su>mlsl_n<mode>): Flip mult operands.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/advsimd-intrinsics/smlal-smlsl-mull-optimized.c: New test.
Diffstat (limited to 'gcc/bitmap.h')
0 files changed, 0 insertions, 0 deletions