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| author | Marcus Comstedt <marcus@mc.pp.se> | 2021-03-19 20:49:08 +0100 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2021-03-23 17:32:41 +0800 |
| commit | 7ac4dfec3912ef0be85542a00628c3ba01ddea2a (patch) | |
| tree | a9e0f6195977bd67711c2e5dde17f5465f17eed0 /gcc/analyzer/program-state.cc | |
| parent | 4eb3a801a5ed947a50f941b63e30a0359fccf138 (diff) | |
| download | gcc-7ac4dfec3912ef0be85542a00628c3ba01ddea2a.zip gcc-7ac4dfec3912ef0be85542a00628c3ba01ddea2a.tar.gz gcc-7ac4dfec3912ef0be85542a00628c3ba01ddea2a.tar.bz2 | |
RISC-V: Fix matches against subreg with a bytenum of 0 in riscv.md
These all intend the least significant subpart of the register.
Use the same endian-neutral "subreg_lowpart_operator" predicate that
ARM does instead.
gcc/
* config/riscv/predicates.md (subreg_lowpart_operator): New predicate
* config/riscv/riscv.md (*addsi3_extended2, *subsi3_extended2)
(*negsi2_extended2, *mulsi3_extended2, *<optab>si3_mask)
(*<optab>si3_mask_1, *<optab>di3_mask, *<optab>di3_mask_1)
(*<optab>si3_extend_mask, *<optab>si3_extend_mask_1): Use
new predicate "subreg_lowpart_operator"
Diffstat (limited to 'gcc/analyzer/program-state.cc')
0 files changed, 0 insertions, 0 deletions