diff options
| author | Zhao Dingyi <dingyizhao.zdy@outlook.com> | 2024-09-07 10:48:46 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2024-09-07 10:48:46 -0600 |
| commit | 6749c69ae143ed808e0d0aa9097f0c9b7c6a785d (patch) | |
| tree | 88853fe95fec9f1972434662d3ac2202c499d316 /gcc/analyzer/program-state.cc | |
| parent | d620499b3a24f14cfb98529640584e63d7eca149 (diff) | |
| download | gcc-6749c69ae143ed808e0d0aa9097f0c9b7c6a785d.zip gcc-6749c69ae143ed808e0d0aa9097f0c9b7c6a785d.tar.gz gcc-6749c69ae143ed808e0d0aa9097f0c9b7c6a785d.tar.bz2 | |
[PATCH] RISC-V: Add missing insn types for XiangShan Nanhu scheduler model
This patch aims to add the missing instruction types to the XiangShan-Nanhu scheduler model.
The current XiangShan -Nanhu model lacks the trap, atomic trap, fcvt_i2f, and fcvt_f2i instructions.
The trap, atomic, and i2f instructions belong to xs_jmp_rs. [1]
The f2i instruction belongs to xs_fmisc_rs.[2]
[1]
https://github.com/OpenXiangShan/XiangShan/blob/v2.0/src/main/scala/xiangshan/package.scala#L780
[2]
https://github.com/OpenXiangShan/XiangShan/blob/v2.0/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala#L290
gcc/ChangeLog:
* config/riscv/xiangshan.md: Add atomic, trap, fcvt_i2f, fcvt_f2i.
Diffstat (limited to 'gcc/analyzer/program-state.cc')
0 files changed, 0 insertions, 0 deletions