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author | Pan Li <pan2.li@intel.com> | 2023-05-25 19:56:40 +0800 |
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committer | Pan Li <pan2.li@intel.com> | 2023-05-29 10:41:46 +0800 |
commit | 272f920b78f5a9ff80755861fa07ec9eb1aa4b58 (patch) | |
tree | b6fc5c666824e6b0832f30c2acd0cbcfa1ced92e /gcc/ada | |
parent | 68816ba245afc6d0e1482bde2d15b35b925b4195 (diff) | |
download | gcc-272f920b78f5a9ff80755861fa07ec9eb1aa4b58.zip gcc-272f920b78f5a9ff80755861fa07ec9eb1aa4b58.tar.gz gcc-272f920b78f5a9ff80755861fa07ec9eb1aa4b58.tar.bz2 |
RISC-V: Add ZVFHMIN extension to the -march= option
This patch would like to add new sub extension (aka ZVFHMIN) to the
-march= option. To make it simple, only the sub extension itself is
involved in this patch, and the underlying FP16 related RVV intrinsic
API depends on the TARGET_ZVFHMIN.
The Zvfhmin extension depends on the Zve32f extension. You can locate
more information about ZVFHMIN from below spec doc.
https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin-vector-extension-for-minimal-half-precision-floating-point
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc:
(riscv_implied_info): Add zvfhmin item.
(riscv_ext_version_table): Ditto.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv-opts.h (MASK_ZVFHMIN): New macro.
(TARGET_ZFHMIN): Align indent.
(TARGET_ZFH): Ditto.
(TARGET_ZVFHMIN): New macro.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-20.c: New test.
* gcc.target/riscv/predef-26.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
Diffstat (limited to 'gcc/ada')
0 files changed, 0 insertions, 0 deletions