RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1

This patch would like to add test cases for the unsigned scalar
.SAT_ADD IMM form 1.  Aka:

Form 1:
  #define DEF_SAT_U_ADD_IMM_FMT_1(T)       \
  T __attribute__((noinline))              \
  sat_u_add_imm_##T##_fmt_1 (T x)          \
  {                                        \
    return (T)(x + 9) >= x ? (x + 9) : -1; \
  }

DEF_SAT_U_ADD_IMM_FMT_1(uint64_t)

The below test is passed for this patch.
* The rv64gcv regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_arith.h: Add helper test macro.
	* gcc.target/riscv/sat_u_add_imm-1.c: New test.
	* gcc.target/riscv/sat_u_add_imm-2.c: New test.
	* gcc.target/riscv/sat_u_add_imm-3.c: New test.
	* gcc.target/riscv/sat_u_add_imm-4.c: New test.
	* gcc.target/riscv/sat_u_add_imm-run-1.c: New test.
	* gcc.target/riscv/sat_u_add_imm-run-2.c: New test.
	* gcc.target/riscv/sat_u_add_imm-run-3.c: New test.
	* gcc.target/riscv/sat_u_add_imm-run-4.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

0 files changed, 0 insertions, 0 deletions