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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-11-07 16:02:43 +0800 |
|---|---|---|
| committer | Lehua Ding <lehua.ding@rivai.ai> | 2023-11-07 16:40:33 +0800 |
| commit | ab7ccb91e592035261e1cac34d9815b6d58ca1bb (patch) | |
| tree | 0459067f8784946fe6f1bbc95da1eb6a8bfc9337 /gcc/ada | |
| parent | a5a76c6f8795f8072e8005e5ada741b69c742198 (diff) | |
| download | gcc-ab7ccb91e592035261e1cac34d9815b6d58ca1bb.zip gcc-ab7ccb91e592035261e1cac34d9815b6d58ca1bb.tar.gz gcc-ab7ccb91e592035261e1cac34d9815b6d58ca1bb.tar.bz2 | |
RISC-V regression test: Fix FAIL bb-slp-cond-1.c for RVV
Previously, in this patch: https://gcc.gnu.org/pipermail/gcc-patches/2023-November/635392.html
I use vect64 && vect128 to represent both RVV and AMDGCN. However, it caused additional FAIL on ARM SVE.
I don't know why ARM SVE vect64 is set as true since their AdvSIMD is 128bit vector and they don't use 64bit vector.
So, here we leverage current AMDGCN solution, just add RISCV like AMDGCN.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/bb-slp-cond-1.c: Add riscv.
Diffstat (limited to 'gcc/ada')
0 files changed, 0 insertions, 0 deletions