RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 3

This patch would like to add test cases for the unsigned scalar
.SAT_ADD IMM form 3.  Aka:

Form 3:
  #define DEF_SAT_U_ADD_IMM_FMT_3(T)                       \
  T __attribute__((noinline))                              \
  sat_u_add_imm_##T##_fmt_3 (T x)                          \
  {                                                        \
    T ret;                                                 \
    return __builtin_add_overflow (x, 8, &ret) ? -1 : ret; \
  }

DEF_SAT_U_ADD_IMM_FMT_3(uint64_t)

The below test is passed for this patch.
* The rv64gcv regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_arith.h: Add helper test macro.
	* gcc.target/riscv/sat_u_add_imm-10.c: New test.
	* gcc.target/riscv/sat_u_add_imm-11.c: New test.
	* gcc.target/riscv/sat_u_add_imm-12.c: New test.
	* gcc.target/riscv/sat_u_add_imm-9.c: New test.
	* gcc.target/riscv/sat_u_add_imm-run-10.c: New test.
	* gcc.target/riscv/sat_u_add_imm-run-11.c: New test.
	* gcc.target/riscv/sat_u_add_imm-run-12.c: New test.
	* gcc.target/riscv/sat_u_add_imm-run-9.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

0 files changed, 0 insertions, 0 deletions