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authorJeff Law <jlaw@ventanamicro.com>2024-05-18 15:08:07 -0600
committerJeff Law <jlaw@ventanamicro.com>2024-05-18 15:08:07 -0600
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[to-be-committed,RISC-V] Improve some shift-add sequences
So this is a minor fix/improvement for shift-add sequences. This was supposed to help xz in a minor way IIRC. Combine may present us with (x + C2') << C1 which was canonicalized from (x << C1) + C2. Depending on the precise values of C2 and C2' one form may be better than the other. We can (somewhat awkwardly) use riscv_const_insns to test for which sequence would be preferred. Tested on Ventana's CI system as well as my own. Waiting on CI results from Rivos's tester before moving forward. Jeff gcc/ * config/riscv/riscv.md: Add new patterns to allow selection between (x << C1) + C2 vs (x + C2') << C1 depending on the cost C2 vs C2'. gcc/testsuite * gcc.target/riscv/shift-add-1.c: New test.
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