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author | Jeff Law <jlaw@ventanamicro.com> | 2024-05-18 15:08:07 -0600 |
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committer | Jeff Law <jlaw@ventanamicro.com> | 2024-05-18 15:08:07 -0600 |
commit | 3c9c52a1c0fa7af22f769a2116b28a0b7ea18129 (patch) | |
tree | 982b496dfe1476963239e7d0a824c66fa88c6fab /gcc/ada | |
parent | 988838da722dea09bd81ee9d49800a6f24980372 (diff) | |
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[to-be-committed,RISC-V] Improve some shift-add sequences
So this is a minor fix/improvement for shift-add sequences. This was
supposed to help xz in a minor way IIRC.
Combine may present us with (x + C2') << C1 which was canonicalized from
(x << C1) + C2.
Depending on the precise values of C2 and C2' one form may be better
than the other. We can (somewhat awkwardly) use riscv_const_insns to
test for which sequence would be preferred.
Tested on Ventana's CI system as well as my own. Waiting on CI results
from Rivos's tester before moving forward.
Jeff
gcc/
* config/riscv/riscv.md: Add new patterns to allow selection
between (x << C1) + C2 vs (x + C2') << C1 depending on the
cost C2 vs C2'.
gcc/testsuite
* gcc.target/riscv/shift-add-1.c: New test.
Diffstat (limited to 'gcc/ada')
0 files changed, 0 insertions, 0 deletions