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| author | Tamar Christina <tamar.christina@arm.com> | 2018-05-21 10:33:30 +0000 |
|---|---|---|
| committer | Tamar Christina <tnfchris@gcc.gnu.org> | 2018-05-21 10:33:30 +0000 |
| commit | d21052ebd7ac9d545a26dde3229c57f872c1d5f3 (patch) | |
| tree | c815fa2f2bd1006a7b0094bc4bd245a21c1fcc8b /gcc/ada/switch.adb | |
| parent | 825f9d0b756aa3103bb15ed4cab5f8691b79c419 (diff) | |
| download | gcc-d21052ebd7ac9d545a26dde3229c57f872c1d5f3.zip gcc-d21052ebd7ac9d545a26dde3229c57f872c1d5f3.tar.gz gcc-d21052ebd7ac9d545a26dde3229c57f872c1d5f3.tar.bz2 | |
Add missing AArch64 NEON instrinctics for Armv8.2-a to Armv8.4-a
This patch adds the missing neon intrinsics for all 128 bit vector Integer modes for the
three-way XOR and negate and xor instructions for Arm8.2-a to Armv8.4-a.
gcc/
2018-05-21 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_eor3qv8hi): Change to
eor3q<mode>4.
(aarch64_bcaxqv8hi): Change to bcaxq<mode>4.
* config/aarch64/aarch64-simd-builtins.def (veor3q_u8, veor3q_u32,
veor3q_u64, veor3q_s8, veor3q_s16, veor3q_s32, veor3q_s64, vbcaxq_u8,
vbcaxq_u32, vbcaxq_u64, vbcaxq_s8, vbcaxq_s16, vbcaxq_s32,
vbcaxq_s64): New.
* config/aarch64/arm_neon.h: Likewise.
* config/aarch64/iterators.md (VQ_I): New.
gcc/testsuite/
2018-05-21 Tamar Christina <tamar.christina@arm.com>
* gcc.target/gcc.target/aarch64/sha3.h (veor3q_u8, veor3q_u32,
veor3q_u64, veor3q_s8, veor3q_s16, veor3q_s32, veor3q_s64, vbcaxq_u8,
vbcaxq_u32, vbcaxq_u64, vbcaxq_s8, vbcaxq_s16, vbcaxq_s32,
vbcaxq_s64): New.
* gcc.target/gcc.target/aarch64/sha3_1.c: Likewise.
* gcc.target/gcc.target/aarch64/sha3_1.c: Likewise.
* gcc.target/gcc.target/aarch64/sha3_1.c: Likewise.
From-SVN: r260435
Diffstat (limited to 'gcc/ada/switch.adb')
0 files changed, 0 insertions, 0 deletions