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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-06-09 22:32:41 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-06-13 09:28:04 +0800 |
| commit | de5f3bbf95674c2e6688b2ce7e7a01cdc236ea41 (patch) | |
| tree | e4eb0fefa2966286be99d5b4a24bd786ae38fcaa /gcc/ada/sem_ch3.adb | |
| parent | d150afb4791e8dff4fc1d4e4b10938b55e58cb16 (diff) | |
| download | gcc-de5f3bbf95674c2e6688b2ce7e7a01cdc236ea41.zip gcc-de5f3bbf95674c2e6688b2ce7e7a01cdc236ea41.tar.gz gcc-de5f3bbf95674c2e6688b2ce7e7a01cdc236ea41.tar.bz2 | |
RISC-V: Fix V_WHOLE && V_FRACT iterator requirement
This patch fixes the requirement of V_WHOLE and V_FRACT.
E.g. VNx8QI in V_WHOLE has no requirement which is incorrect.
Actually, VNx8QI should be whole(full) mode when TARGET_MIN_VLEN < 128
since when TARGET_MIN_VLEN == 128, VNx8QI is e8mf2 which is fractional
vector.
Co-Authored by: Robin Dapp <rdapp@ventanamicro.com>
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Fix requirement.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c: New test.
Diffstat (limited to 'gcc/ada/sem_ch3.adb')
0 files changed, 0 insertions, 0 deletions