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authorArnaud Charlet <charlet@gcc.gnu.org>2015-11-12 12:40:26 +0100
committerArnaud Charlet <charlet@gcc.gnu.org>2015-11-12 12:40:26 +0100
commite3f94155df2c4223b92f63837d0d887502fa7e6e (patch)
treee856a7f2f93456d2f37728a98f5d093dbcf9fcd7 /gcc/ada/init.c
parent311014705a3cf42caf7446caa95f4e4a34fce9be (diff)
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[multiple changes]
2015-11-12 Jerome Lambourg <lambourg@adacore.com> * init.c: Do not try to mess with the MSR values in RTP mode: not needed and forbidden. 2015-11-12 Ed Schonberg <schonberg@adacore.com> * exp_attr.adb (Compile_Stream_Body_In_Scope): Do not install full view of a type that has pragma Stream_Convert, because this indicates special processing for the stream operations of the type. From-SVN: r230240
Diffstat (limited to 'gcc/ada/init.c')
-rw-r--r--gcc/ada/init.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/gcc/ada/init.c b/gcc/ada/init.c
index 0ce6423..59fc335 100644
--- a/gcc/ada/init.c
+++ b/gcc/ada/init.c
@@ -1922,8 +1922,9 @@ __gnat_error_handler (int sig, siginfo_t *si, void *sc)
/* VxWorks on e500v2 clears the SPE bit of the MSR when entering CPU
exception state. To allow the handler and exception to work properly
when they contain SPE instructions, we need to set it back before doing
- anything else. */
-#if (CPU == PPCE500V2) || (CPU == PPC85XX)
+ anything else.
+ This mechanism is only need in kernel mode. */
+#if !(defined (__RTP__) || defined (CERT)) && ((CPU == PPCE500V2) || (CPU == PPC85XX))
register unsigned msr;
/* Read the MSR value */
asm volatile ("mfmsr %0" : "=r" (msr));