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authorDavid S. Miller <davem@davemloft.net>2011-09-25 21:28:51 +0000
committerDavid S. Miller <davem@gcc.gnu.org>2011-09-25 14:28:51 -0700
commite8b141b593cea20857b5041b4c4f1139e7c67712 (patch)
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parent7cbcf85bf976f8eaeb2beee113b1ea60bdb39f99 (diff)
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Add support for floating-point fused multiply-add on Sparc.
* configure.ac: Add feature check to make sure the assembler supports the FMAF, HPC, and VIS 3.0 instructions found on Niagara-3 and later cpus. * configure: Rebuild. * config.in: Likewise. * config/sparc/sparc.opt: New option '-mfmaf'. * config/sparc/sparc.md: Add float fused multiply-add patterns. * config/sparc/sparc.h (AS_NIAGARA3_FLAG): New macro. (ASM_CPU64_DEFAULT_SPEC, ASM_CPU_SPEC): Use it, as needed. * config/sparc/sol2.h (ASM_CPU32_DEFAULT_SPEC, ASM_CPU64_DEFAULT_SPEC, ASM_CPU_SPEC): Likewise. * config/sparc/sparc.c (sparc_option_override): Turn MASK_FMAF on by default for Niagara-3 and later. Turn it off if TARGET_FPU is disabled. (sparc_rtx_costs): Handle 'FMA'. * doc/invoke.texi: Document -mfmaf. From-SVN: r179174
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