xtensa: Optimize bitwise splicing operation

This patch optimizes the operation of cutting and splicing two register
values at a specified bit position, in other words, combining (bitwise
ORing) bits 0 through (C-1) of the register with bits C through 31
of the other, where C is the specified immediate integer 17 through 31.

This typically applies to signed copy of floating point number and
__builtin_return_address() if the windowed register ABI, and saves one
instruction compared to four shifts and a bitwise OR by the default RTL
combination pass.

gcc/ChangeLog:

	* config/xtensa/xtensa.md (*splice_bits):
	New insn_and_split pattern.

0 files changed, 0 insertions, 0 deletions