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author | Andreas Krebbel <krebbel@linux.ibm.com> | 2019-11-07 11:52:05 +0000 |
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committer | Andreas Krebbel <krebbel@gcc.gnu.org> | 2019-11-07 11:52:05 +0000 |
commit | 163f23d21e5f2faee08163f2dcb363042b53ee1e (patch) | |
tree | 68c4a0ec3465a30ea31b298198f65c037e7d9dc0 /gcc/ChangeLog | |
parent | 084d390246c2172853f9e12ce04aef23cba79590 (diff) | |
download | gcc-163f23d21e5f2faee08163f2dcb363042b53ee1e.zip gcc-163f23d21e5f2faee08163f2dcb363042b53ee1e.tar.gz gcc-163f23d21e5f2faee08163f2dcb363042b53ee1e.tar.bz2 |
IBM Z: Add pattern for load truth value of comparison into reg
The RTXs used to express an overflow condition check in add/sub/mul are
too complex for if conversion. However, there is code in
noce_emit_store_flag which generates a simple CC compare as the base
for using a conditional load. All we have to do is to provide a
pattern to store the truth value of a CC compare into a GPR.
Done with the attached patch.
2019-11-07 Andreas Krebbel <krebbel@linux.ibm.com>
* config/s390/s390.md ("*cstorecc<mode>_z13"): New insn_and_split
pattern.
gcc/testsuite/ChangeLog:
2019-11-07 Andreas Krebbel <krebbel@linux.ibm.com>
* gcc.target/s390/addsub-signed-overflow-1.c: Expect lochi
instructions to be used.
* gcc.target/s390/addsub-signed-overflow-2.c: Likewise.
* gcc.target/s390/mul-signed-overflow-1.c: Likewise.
* gcc.target/s390/mul-signed-overflow-2.c: Likewise.
* gcc.target/s390/vector/vec-scalar-cmp-1.c: Check for 32 and 64
bit variant of lochi. Swap the values for the lochi's.
* gcc.target/s390/zvector/vec-cmp-1.c: Likewise.
From-SVN: r277922
Diffstat (limited to 'gcc/ChangeLog')
-rw-r--r-- | gcc/ChangeLog | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 55532cc..aba4707 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2019-11-07 Andreas Krebbel <krebbel@linux.ibm.com> + + * config/s390/s390.md ("*cstorecc<mode>_z13"): New insn_and_split + pattern. + 2019-11-07 Richard Biener <rguenther@suse.de> PR tree-optimization/92405 |