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author | Robin Dapp <rdapp@ventanamicro.com> | 2025-02-21 17:08:16 +0100 |
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committer | Robin Dapp <rdapp@ventanamicro.com> | 2025-02-24 16:04:13 +0100 |
commit | 6be1b9e94d9a2ead15e3625e833f1e34503ab803 (patch) | |
tree | 03a4b260b1584d0b5ef33f556157f635622b5ebf /gcc/ChangeLog.2 | |
parent | f3d4208e798afafcba5246334004e9646e390681 (diff) | |
download | gcc-6be1b9e94d9a2ead15e3625e833f1e34503ab803.zip gcc-6be1b9e94d9a2ead15e3625e833f1e34503ab803.tar.gz gcc-6be1b9e94d9a2ead15e3625e833f1e34503ab803.tar.bz2 |
RISC-V: Include pattern stmts for dynamic LMUL computation [PR114516].
When scanning for program points, i.e. vector statements, we're missing
pattern statements. In PR114516 this becomes obvious as we choose
LMUL=8 assuming there are only three statements but the divmod pattern
adds another three. Those push us beyond four registers so we need to
switch to LMUL=4.
This patch adds pattern statements to the program points which helps
calculate a better register pressure estimate.
PR target/114516
gcc/ChangeLog:
* config/riscv/riscv-vector-costs.cc (compute_estimated_lmul):
Add pattern statements to program points.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/costmodel/riscv/rvv/pr114516.c: New test.
Diffstat (limited to 'gcc/ChangeLog.2')
0 files changed, 0 insertions, 0 deletions