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| author | Jakub Jelinek <jakub@redhat.com> | 2023-01-01 16:20:13 +0100 |
|---|---|---|
| committer | Jakub Jelinek <jakub@redhat.com> | 2023-01-01 16:20:13 +0100 |
| commit | d64f877906111645af0217d4d54993a7b2ecbd2e (patch) | |
| tree | 166f7a493ae415bb43256ff7ee1492cda0cfc5f9 /gcc/ChangeLog-2022 | |
| parent | d423e8dc59045d8f281dcb1a02559cb6f91456bf (diff) | |
| download | gcc-d64f877906111645af0217d4d54993a7b2ecbd2e.zip gcc-d64f877906111645af0217d4d54993a7b2ecbd2e.tar.gz gcc-d64f877906111645af0217d4d54993a7b2ecbd2e.tar.bz2 | |
Rotate ChangeLog files.
Rotate ChangeLog files for ChangeLogs with yearly cadence.
Diffstat (limited to 'gcc/ChangeLog-2022')
| -rw-r--r-- | gcc/ChangeLog-2022 | 35086 |
1 files changed, 35086 insertions, 0 deletions
diff --git a/gcc/ChangeLog-2022 b/gcc/ChangeLog-2022 new file mode 100644 index 0000000..248b5de --- /dev/null +++ b/gcc/ChangeLog-2022 @@ -0,0 +1,35086 @@ +2022-12-31 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + Iain Sandoe <iain@sandoe.co.uk> + + PR modula2/107612 + * Makefile.in: Make the configured libintl includes avaiable in INCINTL. + (BUILD_CPPFLAGS): Use INCINTL. + +2022-12-30 Alexandre Oliva <oliva@adacore.com> + + * hash-table.h (check_complete_insertion, check_insert_slot): + New hash_table methods. + (m_inserting_slot): New hash_table field. + (begin, hash_table ctors, ~hash_table): Check previous insert. + (expand, empty_slow, clear_slot, find_with_hash): Likewise. + (remote_elt_with_hash, traverse_noresize): Likewise. + (gt_pch_nx): Likewise. + (find_slot_with_hash): Likewise. Record requested insert. + +2022-12-30 Stam Markianos-Wright <stam.markianos-wright@arm.com> + + PR target/107714 + * config/arm/arm-protos.h (mve_struct_mem_operand): New protoype. + * config/arm/arm.cc (mve_struct_mem_operand): New function. + * config/arm/constraints.md (Ug): New constraint. + * config/arm/mve.md (mve_vst4q<mode>): Change constraint. + (mve_vst2q<mode>): Likewise. + (mve_vld4q<mode>): Likewise. + (mve_vld2q<mode>): Likewise. + * config/arm/predicates.md (mve_struct_operand): New predicate. + +2022-12-29 Alexandre Oliva <oliva@adacore.com> + + * hash-map.h (put, get_or_insert): Check that added entry + doesn't look deleted either. + * hash-set.h (add): Likewise. + +2022-12-29 Alexandre Oliva <oliva@adacore.com> + + * tree-parloops.cc (take_address_of): Skip INSERT if !gsi. + +2022-12-29 Alexandre Oliva <oliva@adacore.com> + + * hash-map.h (put, get_or_insert): Check that entry does not + look empty after insertion. + +2022-12-29 Alexandre Oliva <oliva@adacore.com> + + * hash-set.h (add): Check that the inserted entry does not + look empty. + +2022-12-29 Alexandre Oliva <oliva@adacore.com> + + * trans-mem.cc (split_bb_make_tm_edge): Record new node in + tm_restart. + +2022-12-29 Alexandre Oliva <oliva@adacore.com> + + * postreload-gcse.cc (lookup_expr_in_table): Use NO_INSERT. + +2022-12-29 Alexandre Oliva <oliva@adacore.com> + + * tree-inline.cc (declare_return_variable): Don't remap NULL + default def of result. + +2022-12-29 Alexandre Oliva <oliva@adacore.com> + + * tree-ssa-loop-niter.cc (expand_simple_operands): Refrain + from caching NULL TREE_OPERANDs. + +2022-12-29 Alexandre Oliva <oliva@adacore.com> + + * tree-inline.cc (insert_decl_map): Skip mapping a NULL decl + as value to itself. + +2022-12-29 Alexandre Oliva <oliva@adacore.com> + + * varpool.cc (symbol_table::remove_unreferenced_decls): Do not + add NULL vnodes to referenced table. + +2022-12-29 Alexandre Oliva <oliva@adacore.com> + + * tree-ssa-scopedtables.cc + (avail_exprs_stack::lookup_avail_expr): Finish hash table + insertion before further lookups. + +2022-12-29 Max Filippov <jcmvbkbc@gmail.com> + + * config/xtensa/xtensa.cc (xtensa_return_in_memory): Use + GP_RETURN_* instead of magic constant. + +2022-12-29 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.cc (xtensa_expand_prologue): Fix to check + DF availability before use of DF_* macros. + +2022-12-28 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/i386.md (*clzsi2_lzcnt_zext_2): define_insn_and_split + to match ZERO_EXTEND form of *clzsi2_lzcnt_zext. + (*clzsi2_lzcnt_zext_2_falsedep): Likewise, new define_insn to match + ZERO_EXTEND form of *clzsi2_lzcnt_zext_falsedep. + (*bmi2_bzhi_zero_extendsidi_5): Likewise, new define_insn to match + ZERO_EXTEND form of *bmi2_bzhi_zero_extendsidi. + (*popcountsi2_zext_2): Likewise, new define_insn_and_split to match + ZERO_EXTEND form of *popcountsi2_zext. + (*popcountsi2_zext_2_falsedep): Likewise, new define_insn to match + ZERO_EXTEND form of *popcountsi2_zext_falsedep. + (*popcounthi2_2): Likewise, new define_insn_and_split to match + ZERO_EXTEND form of *popcounthi2. + (define_peephole2): ZERO_EXTEND variant of HImode popcount&1 using + parity flag peephole2. + +2022-12-28 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/i386-expand.cc (ix86_split_ashl): Call + ix86_expand_clear to generate an xor instruction. + +2022-12-28 Martin Liska <mliska@suse.cz> + + PR tree-optimization/108137 + * tree-ssa-strlen.cc (get_range_strlen_phi): Reject anything + different from INTEGER_CST. + +2022-12-28 Kito Cheng <kito.cheng@sifive.com> + + * config/riscv/riscv-vsetvl.h (vl_vtype_info::get_avl_info): + Return const reference rather than value. + +2022-12-27 Jeff Law <jlaw@ventanamicro.com> + + * config/riscv/riscv.md: Add missing modes to last patch.t + +2022-12-27 Raphael Moreira Zinsly <rzinsly@ventanamicro.com> + + PR target/95632 + PR target/106602 + * config/riscv/riscv.md: New pattern to simulate complex + const_int loads. + +2022-12-27 Christoph Müllner <christoph.muellner@vrull.eu> + + * config/riscv/riscv.cc (riscv_next_saved_reg): New function. + (riscv_is_eh_return_data_register): New function. + (riscv_for_each_saved_reg): Restructure loop. + +2022-12-27 Christoph Müllner <christoph.muellner@vrull.eu> + + * config/riscv/riscv.md: Sync comments with code. + +2022-12-27 jinma <jinma@linux.alibaba.com> + + * common/config/riscv/riscv-common.cc: + +2022-12-27 Jonathan Yong <10walls@gmail.com> + + * configure.ac: use grep -i for case insensitive test. + * configure: Regenerate. + +2022-12-27 Max Filippov <jcmvbkbc@gmail.com> + + * config/xtensa/xtensa.md (unspec): Extract UNSPEC_* constants + into this enum. + (unspecv): Extract UNSPECV_* constants into this enum. + +2022-12-27 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md (set_frame_ptr): Fix to reflect + TARGET_DENSITY. + +2022-12-27 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.h (GP_RETURN, GP_RETURN_REG_COUNT): + Change to GP_RETURN_FIRST and GP_RETURN_LAST, respectively. + * config/xtensa/xtensa.cc (xtensa_function_value, + xtensa_libcall_value, xtensa_function_value_regno_p): Ditto. + +2022-12-27 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.cc (xtensa_expand_prologue): Modify to + exit the inspection loops as soon as the necessity of stack + pointer is found. + +2022-12-27 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/elf.h: Tabify, and trim trailing spaces. + * config/xtensa/linux.h: Likewise. + * config/xtensa/uclinux.h: Likewise. + * config/xtensa/xtensa-dynconfig.c: Likewise. + * config/xtensa/xtensa.cc: Likewise. + * config/xtensa/xtensa.h: Likewise. + * config/xtensa/xtensa.md: Likewise. + +2022-12-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-vsetvl.cc + (pass_vsetvl::compute_global_backward_infos): Change to visit CFG. + (pass_vsetvl::prune_expressions): Ditto. + +2022-12-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-vsetvl.cc (change_insn): Remove pp_print. + (avl_info::avl_info): Add copy function. + (vector_insn_info::dump): Remove pp_print. + * config/riscv/riscv-vsetvl.h: Add copy function. + +2022-12-27 Kewen Lin <linkw@linux.ibm.com> + + PR target/106680 + * common/config/rs6000/rs6000-common.cc (rs6000_handle_option): Remove + the adjustment for option powerpc64 in -m64 handling, and remove the + whole -m32 handling. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): When no + explicit powerpc64 option is provided, enable it for -m64. For 32 bit + and OS_MISSING_POWERPC64, disable powerpc64 if it's enabled but not + specified explicitly. + +2022-12-26 liuhongt <hongtao.liu@intel.com> + + PR target/55522 + PR target/36821 + * config/i386/gnu-user-common.h (GNU_USER_TARGET_MATHFILE_SPEC): + Link crtfastmath.o whenever -mdaz-ftz is specified. Don't link + crtfastmath.o when -share or -mno-daz-ftz is specified. + * config/i386/i386.opt (mdaz-ftz): New option. + * doc/invoke.texi (x86 options): Document mftz-daz. + +2022-12-25 Roger Sayle <roger@nextmovesoftware.com> + Uroš Bizjak <ubizjak@gmail.com> + + * config/i386/i386-builtin.def (__builtin_ia32_movss): Update + CODE_FOR_sse_movss to CODE_FOR_sse_movss_v4sf. + (__builtin_ia32_movsd): Likewise, update CODE_FOR_sse2_movsd to + CODE_FOR_sse2_movsd_v2df. + * config/i386/i386-expand.cc (split_convert_uns_si_sse): Update + gen_sse_movss call to gen_sse_movss_v4sf, and gen_sse2_movsd call + to gen_sse2_movsd_v2df. + (expand_vec_perm_movs): Also allow V4SImode with TARGET_SSE and + V2DImode with TARGET_SSE2. + * config/i386/sse.md + (avx512fp16_fcmaddcsh_v8hf_mask3<round_expand_name>): Update + gen_sse_movss call to gen_sse_movss_v4sf. + (avx512fp16_fmaddcsh_v8hf_mask3<round_expand_name>): Likewise. + (sse_movss_<mode>): Renamed from sse_movss using VI4F_128 mode + iterator to handle both V4SF and V4SI. + (sse2_movsd_<mode>): Likewise, renamed from sse2_movsd using + VI8F_128 mode iterator to handle both V2DF and V2DI. + +2022-12-23 Jakub Jelinek <jakub@redhat.com> + Aldy Hernandez <aldyh@redhat.com> + + * tree-ssa-phiopt.cc (value_replacement): Instead of resetting + phires range info, union it with carg. + +2022-12-23 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/108068 + * tree.h (real_maybe_zerop): Declare. + * tree.cc (real_maybe_zerop): Define. + * tree-ssa-dom.cc (record_edge_info): Use it instead of + real_zerop or TREE_CODE (op1) == SSA_NAME || real_zerop. Always set + can_infer_simple_equiv to false for decimal floating point types. + +2022-12-23 Roger Sayle <roger@nextmovesoftware.com> + + PR target/107548 + * config/i386/i386-features.cc (scalar_chain::add_insn): The + operands of a VEC_SELECT don't need to added to the scalar chain. + (general_scalar_chain::compute_convert_gain) <case VEC_SELECT>: + Provide gains for performing STV on a VEC_SELECT. + (general_scalar_chain::convert_insn): Convert VEC_SELECT to pshufd, + psrldq or no-op. + (general_scalar_to_vector_candidate_p): Handle VEC_SELECT of a + single element from a vector register to a scalar register. + +2022-12-23 H.J. Lu <hjl.tools@gmail.com> + Roger Sayle <roger@nextmovesoftware.com> + + PR target/106933 + PR target/106959 + * config/i386/i386-features.cc (single_def_chain_p): New predicate + function to check that a pseudo's use-def chain is in SSA form. + (timode_scalar_to_vector_candidate_p): Check that TImode regs that + are SET_DEST or SET_SRC of an insn match/are single_def_chain_p. + +2022-12-23 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/vector.md: Fix contraints. + +2022-12-23 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-protos.h (get_avl_type_rtx): New function. + * config/riscv/riscv-v.cc (get_avl_type_rtx): Ditto. + * config/riscv/riscv-vector-builtins-bases.cc (class loadstore): New + class. + (BASE): Ditto. + * config/riscv/riscv-vector-builtins-bases.h: Ditto. + * config/riscv/riscv-vector-builtins-functions.def (vle): Ditto. + (vse): Ditto. + * config/riscv/riscv-vector-builtins-shapes.cc (build_one): Ditto. + (struct loadstore_def): Ditto. + (SHAPE): Ditto. + * config/riscv/riscv-vector-builtins-shapes.h: Ditto. + * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_U_OPS): New + macro. + (DEF_RVV_F_OPS): Ditto. + (vuint8mf8_t): Add corresponding mask type. + (vuint8mf4_t): Ditto. + (vuint8mf2_t): Ditto. + (vuint8m1_t): Ditto. + (vuint8m2_t): Ditto. + (vuint8m4_t): Ditto. + (vuint8m8_t): Ditto. + (vuint16mf4_t): Ditto. + (vuint16mf2_t): Ditto. + (vuint16m1_t): Ditto. + (vuint16m2_t): Ditto. + (vuint16m4_t): Ditto. + (vuint16m8_t): Ditto. + (vuint32mf2_t): Ditto. + (vuint32m1_t): Ditto. + (vuint32m2_t): Ditto. + (vuint32m4_t): Ditto. + (vuint32m8_t): Ditto. + (vuint64m1_t): Ditto. + (vuint64m2_t): Ditto. + (vuint64m4_t): Ditto. + (vuint64m8_t): Ditto. + (vfloat32mf2_t): Ditto. + (vfloat32m1_t): Ditto. + (vfloat32m2_t): Ditto. + (vfloat32m4_t): Ditto. + (vfloat32m8_t): Ditto. + (vfloat64m1_t): Ditto. + (vfloat64m2_t): Ditto. + (vfloat64m4_t): Ditto. + (vfloat64m8_t): Ditto. + * config/riscv/riscv-vector-builtins.cc (DEF_RVV_TYPE): Adjust for new + macro. + (DEF_RVV_I_OPS): Ditto. + (DEF_RVV_U_OPS): New macro. + (DEF_RVV_F_OPS): New macro. + (use_real_mask_p): New function. + (use_real_merge_p): Ditto. + (get_tail_policy_for_pred): Ditto. + (get_mask_policy_for_pred): Ditto. + (function_builder::apply_predication): Ditto. + (function_builder::append_base_name): Ditto. + (function_builder::append_sew): Ditto. + (function_expander::add_vundef_operand): Ditto. + (function_expander::add_mem_operand): Ditto. + (function_expander::use_contiguous_load_insn): Ditto. + (function_expander::use_contiguous_store_insn): Ditto. + * config/riscv/riscv-vector-builtins.def (DEF_RVV_TYPE): Adjust for + adding mask type. + (vbool64_t): Ditto. + (vbool32_t): Ditto. + (vbool16_t): Ditto. + (vbool8_t): Ditto. + (vbool4_t): Ditto. + (vbool2_t): Ditto. + (vbool1_t): Ditto. + (vint8mf8_t): Ditto. + (vint8mf4_t): Ditto. + (vint8mf2_t): Ditto. + (vint8m1_t): Ditto. + (vint8m2_t): Ditto. + (vint8m4_t): Ditto. + (vint8m8_t): Ditto. + (vint16mf4_t): Ditto. + (vint16mf2_t): Ditto. + (vint16m1_t): Ditto. + (vint16m2_t): Ditto. + (vint16m4_t): Ditto. + (vint16m8_t): Ditto. + (vint32mf2_t): Ditto. + (vint32m1_t): Ditto. + (vint32m2_t): Ditto. + (vint32m4_t): Ditto. + (vint32m8_t): Ditto. + (vint64m1_t): Ditto. + (vint64m2_t): Ditto. + (vint64m4_t): Ditto. + (vint64m8_t): Ditto. + (vfloat32mf2_t): Ditto. + (vfloat32m1_t): Ditto. + (vfloat32m2_t): Ditto. + (vfloat32m4_t): Ditto. + (vfloat32m8_t): Ditto. + (vfloat64m1_t): Ditto. + (vfloat64m4_t): Ditto. + * config/riscv/riscv-vector-builtins.h + (function_expander::add_output_operand): New function. + (function_expander::add_all_one_mask_operand): Ditto. + (function_expander::add_fixed_operand): Ditto. + (function_expander::vector_mode): Ditto. + (function_base::apply_vl_p): Ditto. + (function_base::can_be_overloaded_p): Ditto. + * config/riscv/riscv-vsetvl.cc (get_vl): Remove restrict of supporting + AVL is not VLMAX. + * config/riscv/t-riscv: Add include file. + +2022-12-23 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-vector-builtins-shapes.cc (struct vsetvl_def): Add + "__riscv_" prefix. + +2022-12-23 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-vector-builtins-bases.cc: Change it to no side effects. + * config/riscv/vector.md (@vsetvl<mode>_no_side_effects): New pattern. + +2022-12-23 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-vector-builtins-bases.cc: Remove side effects. + +2022-12-23 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-vsetvl.cc (anticipatable_occurrence_p): Fix + incorrect annotations. + (available_occurrence_p): Ditto. + (backward_propagate_worthwhile_p): Ditto. + (can_backward_propagate_p): Ditto. + +2022-12-23 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-vsetvl.cc (vlmax_avl_insn_p): Fix multi-line + conditional. + (vsetvl_insn_p): Ditto. + (same_bb_and_before_p): Ditto. + (same_bb_and_after_or_equal_p): Ditto. + +2022-12-22 Andrew Carlotti <andrew.carlotti@arm.com> + + * doc/md.texi: Move example code remark next to it's code block. + +2022-12-22 Andrew Carlotti <andrew.carlotti@arm.com> + + * doc/md.texi: Fix inconsistent example name. + +2022-12-22 Andrew Carlotti <andrew.carlotti@arm.com> + + * doc/md.texi: Fix incorrect pxref. + +2022-12-22 Richard Biener <rguenther@suse.de> + + PR bootstrap/106482 + * doc/install.texi (ISO C++11 Compiler): Document GCC version + known to work. + +2022-12-22 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/108166 + * tree-ssa-phiopt.cc (value_replacement): For the maybe_equal_p + case turned into equal_p reset SSA_NAME_RANGE_INFO of phi result. + +2022-12-22 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/108193 + * cse.cc (compute_const_anchors): Change n type to + unsigned HOST_WIDE_INT, adjust comparison against it to avoid + warnings. Formatting fix. + (insert_const_anchor): Use gen_int_mode instead of GEN_INT. + +2022-12-22 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107451 + * tree-vect-stmts.cc (vectorizable_load): Avoid loading + SLP group members from group numbers in excess of the + vectorization factor. + +2022-12-22 Jakub Jelinek <jakub@redhat.com> + + * config/aarch64/t-aarch64 (TM_H): Don't add aarch64-cores.def, + add aarch64-fusion-pairs.def, aarch64-tuning-flags.def and + aarch64-option-extensions.def. + (OPTIONS_H_EXTRA): Don't add aarch64-fusion-pairs.def nor + aarch64-tuning-flags.def. + +2022-12-22 Jan Hubicka <hubicka@ucw.cz> + + * config/i386/i386-expand.cc (ix86_expand_set_or_cpymem): Add + TARGET_AVX512_SPLIT_REGS + * config/i386/i386-options.cc (ix86_option_override_internal): + Honor x86_TONE_AVOID_256FMA_CHAINS. + * config/i386/i386.cc (ix86_vec_cost): Honor TARGET_AVX512_SPLIT_REGS. + (ix86_reassociation_width): Likewise. + * config/i386/i386.h (TARGET_AVX512_SPLIT_REGS): New tune. + * config/i386/x86-tune.def (X86_TUNE_USE_GATHER_2PARTS): Disable + for znver4. + (X86_TUNE_USE_GATHER_4PARTS): Likewise. + (X86_TUNE_AVOID_256FMA_CHAINS): Set for znver4. + (X86_TUNE_AVOID_512FMA_CHAINS): New utne; set for znver4. + (X86_TUNE_AVX256_OPTIMAL): Add znver4. + (X86_TUNE_AVX512_SPLIT_REGS): New tune. + (X86_TUNE_AVX256_MOVE_BY_PIECES): Add znver1-3. + (X86_TUNE_AVX256_STORE_BY_PIECES): Add znver1-3. + (X86_TUNE_AVX512_MOVE_BY_PIECES): Add znver4. + (X86_TUNE_AVX512_STORE_BY_PIECES): Add znver4. + +2022-12-22 Jan Hubicka <hubicka@ucw.cz> + + * config/i386/x86-tune-costs.h (znver4_cost): Upate costs of FP and SSE + moves, division multiplication, gathers, L2 cache size, and more + complex FP instrutions. + +2022-12-21 Andrew Pinski <apinski@marvell.com> + + PR tree-optimization/105532 + * match.pd (~(X >> Y) -> ~X >> Y): Check if it is an integral + type before calling tree_nonzero_bits. + (popcount(X) + popcount(Y)): Likewise. + (popcount(X&C1)): Likewise. + +2022-12-21 Chung-Lin Tang <cltang@codesourcery.com> + + * config/nvptx/nvptx.cc (nvptx_print_operand): Add 'p' case, adjust + comments. + (enum nvptx_builtins): Add NVPTX_BUILTIN_BAR_RED_AND, + NVPTX_BUILTIN_BAR_RED_OR, and NVPTX_BUILTIN_BAR_RED_POPC. + (nvptx_expand_bar_red): New function. + (nvptx_init_builtins): + Add DEFs of __builtin_nvptx_bar_red_[and/or/popc]. + (nvptx_expand_builtin): Use nvptx_expand_bar_red to expand + NVPTX_BUILTIN_BAR_RED_[AND/OR/POPC] cases. + * config/nvptx/nvptx.md (define_c_enum "unspecv"): Add + UNSPECV_BARRED_AND, UNSPECV_BARRED_OR, and UNSPECV_BARRED_POPC. + (BARRED): New int iterator. + (barred_op,barred_mode,barred_ptxtype): New int attrs. + (nvptx_barred_<barred_op>): New define_insn. + +2022-12-21 Richard Biener <rguenther@suse.de> + + PR middle-end/107994 + * gimplify.cc (gimplify_expr): Catch errorneous comparison + operand. + +2022-12-21 Jan Hubicka <hubicka@ucw.cz> + + * lto-opts.cc (lto_write_options): Also skip -fwhole-program. + +2022-12-21 Jan Hubicka <jh@suse.cz> + + * lto-cgraph.cc (lto_output_node): When doing WPA in incremental link + pass down resolution info. + +2022-12-21 Jan Hubicka <hubicka@ucw.cz> + + * doc/invoke.texi: Fix documentation of -fwhole-program with LTO + and document behaviour for incremental linking. + +2022-12-21 Kewen Lin <linkw@linux.ibm.com> + + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Fix the + location for OPTION_MASK_P10_FUSION flag setting. + +2022-12-21 Kewen Lin <linkw@linux.ibm.com> + + * fold-const.cc (fold_convert_const_real_from_real): Treat floating + point conversion to a type with same mode as copy instead of normal + convertFormat. + +2022-12-21 Kewen Lin <linkw@linux.ibm.com> + + PR target/106736 + * config/rs6000/mma.md (define_expand movoo): Call function + rs6000_opaque_type_invalid_use_p to check and emit error message for + the invalid use of opaque type. + (define_expand movxo): Likewise. + * config/rs6000/rs6000-protos.h + (rs6000_opaque_type_invalid_use_p): New function declaration. + (currently_expanding_gimple_stmt): New extern declaration. + * config/rs6000/rs6000.cc (rs6000_opaque_type_invalid_use_p): New + function. + +2022-12-21 Jason Merrill <jason@redhat.com> + + * fold-const.cc (fold_convert_loc): Check return value of + protected_set_expr_location_unshare. + +2022-12-21 Jason Merrill <jason@redhat.com> + + PR c++/84471 + PR c++/107504 + * fold-const.cc (protected_set_expr_location_unshare): Not static. + * tree.h: Declare it. + * tree.cc (decl_value_expr_insert): Use it. + +2022-12-20 Patrick Palka <ppalka@redhat.com> + + PR c++/101886 + * tree.cc (walk_tree_1) <case TREE_VEC>: Walk the elements + in forward instead of reverse order. + <case VECTOR_CST>: Likewise. + +2022-12-20 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/108139 + * gimple-range-cache.cc (ranger_cache::fill_block_cache): Do not + use equivalences originating from PHIS. + +2022-12-20 Richard Biener <rguenther@suse.de> + + PR d/104749 + * doc/install.texi (GDC): Document GDC 9.4 or later is required + to build the D language frontend. + +2022-12-20 Jiufu Guo <guojiufu@linux.ibm.com> + + PR target/103743 + * config/rs6000/rs6000-protos.h (can_be_rotated_to_lowbits): New. + (can_be_rotated_to_positive_16bits): New. + (can_be_rotated_to_negative_15bits): New. + * config/rs6000/rs6000.cc (can_be_rotated_to_lowbits): New definition. + (can_be_rotated_to_positive_16bits): New definition. + (can_be_rotated_to_negative_15bits): New definition. + * config/rs6000/rs6000.md (*rotate_on_cmpdi): New define_insn_and_split. + (eqne): Move earlier. + +2022-12-19 Jason Merrill <jason@redhat.com> + + * sort.cc: Disable -Wconditionally-supported in + CHECKING_P code. + +2022-12-19 Jason Merrill <jason@redhat.com> + + PR c++/64867 + * configure.ac (strict_warn): Add -Wconditionally-supported. + * configure: Regenerate. + +2022-12-19 Richard Biener <rguenther@suse.de> + + PR tree-optimization/108164 + * tree-vect-loop-manip.cc (vect_update_ivs_after_vectorizer): + Perform vect_step_op_add update in the appropriate type. + +2022-12-19 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/arm-c.cc (__ARM_FEATURE_CLZ): Fix definition of + preprocessor macro when target has CLZ in another ISA. + +2022-12-19 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/vector.md: Remove vste. + +2022-12-19 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config.gcc: Add riscv-vsetvl.o. + * config/riscv/riscv-passes.def (INSERT_PASS_BEFORE): Add VSETVL PASS + location. + * config/riscv/riscv-protos.h (make_pass_vsetvl): New function. + (enum avl_type): New enum. + (get_ta): New function. + (get_ma): Ditto. + (get_avl_type): Ditto. + (calculate_ratio): Ditto. + (enum tail_policy): New enum. + (enum mask_policy): Ditto. + * config/riscv/riscv-v.cc (calculate_ratio): New function. + (emit_pred_op): change the VLMAX mov codgen. + (get_ta): New function. + (get_ma): Ditto. + (enum tail_policy): Change enum. + (get_prefer_tail_policy): New function. + (enum mask_policy): Change enum. + (get_prefer_mask_policy): New function. + * config/riscv/t-riscv: Add riscv-vsetvl.o + * config/riscv/vector.md: Adjust attribute and pattern for VSETVL + PASS. + (@vlmax_avl<mode>): Ditto. + (@vsetvl<mode>_no_side_effects): Delete. + (vsetvl_vtype_change_only): New MD pattern. + (@vsetvl_discard_result<mode>): Ditto. + * config/riscv/riscv-vsetvl.cc: New file. + * config/riscv/riscv-vsetvl.h: New file. + +2022-12-19 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-vector-switch.def (ENTRY): Correct attributes. + +2022-12-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + PR target/108140 + * config/aarch64/aarch64-builtins.cc + (aarch64_expand_builtin_data_intrinsic): Handle NULL target. + +2022-12-19 Jakub Jelinek <jakub@redhat.com> + + * config/gnu-user.h (LIBHWASAN_EARLY_SPEC): Add libhwasan_preinit.o + to link spec if not -shared. + +2022-12-19 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-v.cc (emit_vlmax_vsetvl): Pass through VLMUL enum + instead of machine mode. + * config/riscv/riscv-vector-builtins-bases.cc: Ditto. + * config/riscv/riscv.cc (riscv_print_operand): Print LMUL by enum vlmul + instead of machine mode. + +2022-12-19 Jiufu Guo <guojiufu@linux.ibm.com> + + PR target/106708 + * config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Add using + "li; x?oris" to build constant. + +2022-12-19 liuhongt <hongtao.liu@intel.com> + + PR target/55522 + * config/i386/gnu-user-common.h (GNU_USER_TARGET_MATHFILE_SPEC): + Don't add crtfastmath.o for -shared. + * doc/invoke.texi (-shared): Add related documentation. + +2022-12-18 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + + * config.gcc: Determine Solaris minor version. + Obsolete *-*-solaris2.11.[0-3]*. + * doc/install.texi (Specific, *-*-solaris2*): Document it. + +2022-12-17 Segher Boessenkool <segher@kernel.crashing.org> + + * config/rs6000/rs6000-logue.cc (rs6000_output_function_epilogue): + Handle GNU Rust for the tbtab lang field. + +2022-12-16 John David Anglin <danglin@gcc.gnu.org> + + * config/pa/pa.cc (pa_option_override): Disable -fstack-protector. + +2022-12-16 Vladimir N. Makarov <vmakarov@redhat.com> + + Revert: + 2022-12-15 Vladimir N. Makarov <vmakarov@redhat.com> + + * ira-costs.cc: Include print-rtl.h. + (record_reg_classes, scan_one_insn): Add code to print debug info. + * ira.cc (ira_init_register_move_cost): Check that at least one hard + reg of the mode are in the class contents to calculate the + register move costs. + +2022-12-16 Qing Zhao <qing.zhao@oracle.com> + + * doc/invoke.texi: Document -Wstrict-flex-arrays option. + * gimple-array-bounds.cc (check_out_of_bounds_and_warn): Add two more + arguments. + (array_bounds_checker::check_array_ref): Issue warnings for + -Wstrict-flex-arrays. + * opts.cc (finish_options): Issue warning for unsupported combination + of -Wstrict_flex_arrays and -fstrict-flex-array. + * tree-vrp.cc (execute_ranger_vrp): Enable the pass when + warn_strict_flex_array is true. + +2022-12-16 Palmer Dabbelt <palmer@rivosinc.com> + + * config/riscv/riscv.cc (riscv_option_override): Fix comment + wording. + +2022-12-16 Palmer Dabbelt <palmer@rivosinc.com> + + * doc/extend.texi (__builtin_riscv_pause): Imply + Xgnuzihintpausestate. + +2022-12-16 Richard Biener <rguenther@suse.de> + + PR middle-end/108086 + * tree-inline.cc (remap_ssa_name): Do not unshare the + result from the decl_map. + +2022-12-16 Richard Biener <rguenther@suse.de> + + PR middle-end/108086 + * tree-inline.cc (copy_bb): Remove handling of (foo *)&this->m + substitution which is done in remap_gimple_op_r via + re-gimplifying. + +2022-12-16 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/106751 + * loop-invariant.cc (move_invariant_reg): If preheader bb ends + with a JUMP_INSN, split the preheader edge and emit invariants + into the new preheader basic block. + +2022-12-16 Richard Biener <rguenther@suse.de> + + PR middle-end/108086 + * tree-inline.cc (remap_gimple_stmt): Add stmts to the + sequence without updating them. Simplify x == x detection. + +2022-12-16 Haochen Jiang <haochen.jiang@intel.com> + + * config/i386/cmpccxaddintrin.h + (__cmpccxadd_epi32): Rename to _cmpccxadd_epi32. + (__cmpccxadd_epi64): Rename to _cmpccxadd_epi64. + +2022-12-15 Vladimir N. Makarov <vmakarov@redhat.com> + + * ira-costs.cc: Include print-rtl.h. + (record_reg_classes, scan_one_insn): Add code to print debug info. + * ira.cc (ira_init_register_move_cost): Check that at least one hard + reg of the mode are in the class contents to calculate the + register move costs. + +2022-12-15 Siddhesh Poyarekar <siddhesh@gotplt.org> + + * doc/extend.texi (__builtin_dynamic_object_size): Document + builtin. + * doc/passes.texi + (Optimize calls to @code{__builtin_object_size}): Also mention + __builtin_dynamic_object_size. + +2022-12-15 Siddhesh Poyarekar <siddhesh@gotplt.org> + + PR middle-end/70090 + * doc/invoke.texi (-fsanitize=object-size): Use + __builtin_dynamic_object_size instead of + __builtin_object_size. + +2022-12-15 Richard Biener <rguenther@suse.de> + + PR middle-end/108086 + * tree-inline.cc (copy_edges_for_bb): Walk stmts backwards for + splitting the block to avoid quadratic behavior with setting + stmts BB on multliple splits. + +2022-12-15 Spacetown <michael.foerderer@gmx.de> + + PR gcov-profile/107537 + * gcov.cc (output_branch_count): Add annotation '(fallthrough)' + or '(throw)' also to uncovered branches. + +2022-12-15 Richard Biener <rguenther@suse.de> + + PR middle-end/108086 + * tree-inline.cc (copy_edges_for_bb): Do not update all + stmts again. + +2022-12-15 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/108095 + * tree-into-ssa.cc (maybe_register_def): Insert debug stmt + on all non-EH edges from asm goto if they have a single + predecessor rather than asserting there is at most one such edge. + Test whether there are no PHI nodes next to the single predecessor + test. + +2022-12-14 David Faust <david.faust@oracle.com> + + PR target/106773 + * btfout.cc (get_section_name): New function. + (btf_collect_datasec): Use it here. Process functions, marking them + 'extern' and generating DATASEC entries for them as appropriate. Move + creation of BTF_KIND_FUNC records to here... + (btf_dtd_emit_preprocess_cb): ... from here. + +2022-12-14 David Faust <david.faust@oracle.com> + + PR target/106773 + * btfout.cc (btf_collect_datasec): Correct size of void entries. + (btf_dvd_emit_preprocess_cb): Do not skip emitting variables which + refer to void types. + (btf_init_postprocess): Create 'const void' type record if needed and + adjust variables to refer to it as appropriate. + +2022-12-14 David Faust <david.faust@oracle.com> + + PR target/106773 + * btfout.cc (btf_collect_datasec): Mark extern variables as such. + (btf_dvd_emit_preprocess_cb): Skip non-defining extern variable decl + if there is a defining decl for the same variable. + (btf_asm_varent): Accomodate 'extern' linkage. + +2022-12-14 Martin Jambor <mjambor@suse.cz> + + * ipa-sra.cc (create_parameter_descriptors): Consider the first + parameter of a method safe to dereference. + +2022-12-14 Martin Jambor <mjambor@suse.cz> + + * ipa-sra.cc (loaded_decls): Adjust comment. + (scan_expr_access): Also detect assignments of address of local + variables to a variable. Bail out early on SSA_NAMEs and + constants as an optimization. + +2022-12-14 Gaius Mulley <gaiusmod2@gmail.com> + + * configure.ac (HAVE_PYTHON): Test for Python3 added. + * dwarf2out.cc (gen_compile_unit_die): Check language_string + and language to DW_LANG_Modula2. + * doc/install.texi: Add m2 as a language. + (--disable-libgm2): Documented. Add make check-m2 to testing selected + tests. + * doc/sourcebuild.texi (GM2): New prerequisite item. + (Python3 modules) New item. + (libgm2) Added. + (gcc/m2) Added. + * configure: Rebuilt. + * config.in: Rebuilt. + * doc/gm2.texi: New file. + +2022-12-14 Martin Jambor <mjambor@suse.cz> + + * doc/invoke.texi (ipa-sra-ptrwrap-growth-factor): Fix the + description. + * params.opt (ipa-sra-ptrwrap-growth-factor): Likewise. + +2022-12-14 Tamar Christina <tamar.christina@arm.com> + + PR target/107988 + * config/aarch64/aarch64.cc + (aarch64_vectorize_can_special_div_by_constant): Ensure input and output + RTL are registers. + +2022-12-14 Martin Liska <mliska@suse.cz> + + * doc/invoke.texi: Document ipa-sra-ptrwrap-growth-factor. + +2022-12-14 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107617 + * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): + Handle negative pd.rhs_off. + (vn_reference_lookup_3): Properly provide pd.rhs_off + for .LEN_STORE on big-endian targets. + +2022-12-13 Martin Jambor <mjambor@suse.cz> + + * ipa-param-manipulation.cc + (ipa_param_body_adjustments::modify_expression): Bail out early if + there are no replacements. + (ipa_param_body_adjustments::modify_assignment): Likewise. + +2022-12-13 Martin Jambor <mjambor@suse.cz> + + * ipa-sra.cc (isra_param_desc): New fields safe_size, + conditionally_dereferenceable and safe_size_set. + (struct gensum_param_desc): New field conditionally_dereferenceable. + (struct isra_param_flow): Updated comment of field unit_size. + (ipa_sra_function_summaries::duplicate): Copy the new fields. + (isra_call_summary::dump): Dump unit_size when representing safe_size. + (dump_gensum_param_descriptor): Dump new flag. + (dump_isra_param_descriptor): Dump new fields. + (isra_analyze_call): Fill unit_size when it represents known safe + size. + (check_gensum_access): Instead of disqualifying pointers which are not + always dereference, mark them as conditionally dereferencable if loads + are frequent enough. + (process_scan_results): Copy the conditionally_dereferenceable flag. + (isra_write_node_summary): Stream new fields, or assert they are not + initialized yet. + (isra_read_node_info): Stream new fields. + (update_safe_size): New function. + (propagate_param_hints_accross_call): Propagate safe_sizes. + (propagate_hints_to_all_callees): New function. + (adjust_parameter_descriptions): Check conditionally_dereferenceable + candidates, rework dumping. + (ipa_sra_analysis): Move most of hint propagation for one node to + propagate_hints_to_all_callees. Add another loop to stabilize within + SCCs and another one to verify. + +2022-12-13 Martin Jambor <mjambor@suse.cz> + + * ipa-sra.cc (isra_param_desc): New field not_specially_constructed. + (struct isra_param_flow): New field constructed_for_calls. + (isra_call_summary::dump): Dump the new flag. + (loaded_decls): New variable. + (dump_isra_param_descriptor): New parameter hints, dump + not_specially_constructed if it is true. + (dump_isra_param_descriptors): New parameter hints, pass it to + dump_isra_param_descriptor. + (ipa_sra_function_summaries::duplicate): Duplicate new flag. + (create_parameter_descriptors): Adjust comment. + (get_gensum_param_desc): Bail out when decl2desc is NULL. + (scan_expr_access): Add loaded local variables to loaded_decls. + (scan_function): Survive if final_bbs is NULL. + (isra_analyze_call): Compute constructed_for_calls flag. + (process_scan_results): Be optimistic about size limits. Do not dump + computed param hints when dumpint IPA-SRA structures. + (isra_write_edge_summary): Stream constructed_for_calls. + (isra_read_edge_summary): Likewise. + (ipa_sra_dump_all_summaries): New parameter hints, pass it to + dump_isra_param_descriptor. + (flip_all_hints_pessimistic): New function. + (flip_all_param_hints_pessimistic): Likewise. + (propagate_param_hints): Likewise. + (disable_unavailable_parameters): Renamed to + adjust_parameter_descriptions. Expand size limits for parameters + which are specially contstructed by all callers. Check limits again.p + (ipa_sra_analysis): Pass required hints to ipa_sra_dump_all_summaries. + Add hint propagation. + (ipa_sra_summarize_function): Initialize and destory loaded_decls, + rearrange so that scan_function is called even when there are no + candidates. + * params.opt (ipa-sra-ptrwrap-growth-factor): New parameter. + +2022-12-13 Martin Jambor <mjambor@suse.cz> + + * ipa-sra.cc (ipa_sra_analysis): Move top-down analysis before + bottom-up analysis. Replace FOR_EACH_VEC_ELT with C++11 iteration. + +2022-12-13 Martin Jambor <mjambor@suse.cz> + + PR ipa/103585 + * params.opt (ipa-sra-deref-prob-threshold): New parameter. + * doc/invoke.texi (ipa-sra-deref-prob-threshold): Document it. + * ipa-sra.cc (struct gensum_param_access): New field load_count. + (struct gensum_param_desc): New field safe_ref, adjusted comments. + (by_ref_count): Renamed to unsafe_by_ref_count, adjusted all uses. + (dump_gensum_access): Dump the new field. + (dump_gensum_param_descriptor): Likewise. + (create_parameter_descriptors): Set safe_ref field, move setting + by_ref forward. Only increment unsafe_by_ref_count for unsafe + by_ref parameters. + (allocate_access): Initialize new field. + (mark_param_dereference): Adjust indentation. Only add data to + bb_dereferences for unsafe by_ref parameters. + (scan_expr_access): For loads, accumulate BB counts. + (dereference_probable_p): New function. + (check_gensum_access): Fix leading comment, add parameter FUN. + Check cumulative counts of loads for safe by_ref accesses instead + of dereferences. + (process_scan_results): Do not propagate dereference distances for + safe by_ref parameters. Pass fun to check_gensum_access. Safe + by_ref params do not need the postdominance check. + +2022-12-13 Martin Jambor <mjambor@suse.cz> + + * ipa-cp.cc (clone_for_param_removal_p): New function. + (estimate_local_effects): Call it before considering cloning + just to remove unused parameters. + +2022-12-13 Martin Jambor <mjambor@suse.cz> + + PR ipa/103227 + * ipa-param-manipulation.h (class ipa_param_adjustments): Removed + member function get_updated_index_or_split. + (class ipa_param_body_adjustments): New overload of + register_replacement, new member function append_init_stmts, new + member m_split_agg_csts_inits. + * ipa-param-manipulation.cc: Include ipa-prop.h. + (ipa_param_adjustments::get_updated_index_or_split): Removed. + (ipa_param_body_adjustments::register_replacement): New overload, use + it from the older one. + (ipa_param_body_adjustments::common_initialization): Added the + capability to create replacements for conflicting IPA-CP discovered + constants. + (ipa_param_body_adjustments::ipa_param_body_adjustments): Construct + the new member. + (ipa_param_body_adjustments::append_init_stmts): New function. + * ipa-sra.cc: Include ipa-prop.h. + (push_param_adjustments_for_index): Require IPA-CP transformation + summary as a parameter, do not create replacements which are known to + have constant values. + (process_isra_node_results): Find and pass to the above function the + IPA-CP transformation summary. + * ipa-prop.cc (adjust_agg_replacement_values): Remove the + functionality replacing IPA-SRA created scalar parameters with + constants. Simplify, do not require parameter descriptors, do not + return anything. + (ipcp_transform_function): Simplify now that + adjust_agg_replacement_values does not change cfg. Move definition + and initialization of descriptors lower. + * tree-inline.cc (tree_function_versioning): Call append_init_stmts of + param_body_adjs, if there are any. + +2022-12-13 Martin Jambor <mjambor@suse.cz> + + * ipa-prop.cc (useful_ipcp_transformation_info_p): New function. + (write_ipcp_transformation_info): Added a parameter, simplified + given that is known not to be NULL. + (ipcp_write_transformation_summaries): Write out all useful + transformation summaries. + (read_ipcp_transformation_info): Simplify given that some info + will be read. + (read_replacements_section): Remove assert. + * lto-cgraph.cc (add_node_to): Also set encode_body for clones. + * lto-streamer-out.cc (lto_output): Do not output virtual clones. + +2022-12-13 Jakub Jelinek <jakub@redhat.com> + + PR target/108044 + * config/i386/i386.md (*concat<half><mode>3_5, *concat<mode><dwi>3_6, + *concat<mode><dwi>3_7): Split alternative with =ro output constraint + into =r,o,o and use Wd input constraint for the last alternative which + is enabled for TARGET_64BIT. Reject ix86_endbr_immediate_operand + in the input constant. + +2022-12-13 Tamar Christina <tamar.christina@arm.com> + + * config/aarch64/aarch64.md (tbranch_<code><mode>3): Use gen_int_mode. + +2022-12-13 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/108064 + * tree-vect-patterns.cc (vect_recog_rotate_pattern): Pass uvectype + as 4th argument to append_pattern_def_seq for statements with lhs + with utype type. + +2022-12-13 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105801 + * tree-ssa-ccp.cc (likely_value): .DEFERRED_INIT produces + UNDEFINED. + * doc/invoke.texi (ftrivial-auto-var-init): Explicitely + mention we treat variables without an initializer as + undefined also for optimization purposes. + +2022-12-13 Tom Tromey <tom@tromey.com> + Mark Wielaard <mark@klomp.org> + Marc Poulhiès <dkm@kataplop.net> + + * dwarf2out.cc (is_rust): New. + (base_type_die): Use DW_ATE_UTF for the Rust 'char' type. + (gen_compile_unit_die): Handle "GNU Rust". + +2022-12-13 Richard Biener <rguenther@suse.de> + + PR tree-optimization/108076 + * tree-if-conv.cc (if_convertible_loop_p_1): Reject blocks + with non-local or forced labels that we later remove + labels from. + +2022-12-13 Haochen Gui <guihaoc@gcc.gnu.org> + + * config/rs6000/rs6000.md (cbranchcc4): New expander. + +2022-12-13 Haochen Gui <guihaoc@gcc.gnu.org> + + * optabs.cc (prepare_cmp_insn): Return a NULL rtx other than + assertion failure when targets don't have cbranch optab or + predicate check fails. + +2022-12-12 Wilco Dijkstra <wilco.dijkstra@arm.com> + + * config/aarch64/aarch64.cc (aarch64_rtx_costs): Add correct costs + for 24-bit and 12-bit shifted immediate add/sub. + (TARGET_CONST_ANCHOR): Define. + * config/aarch64/predicates.md (aarch64_pluslong_immediate): + Fix range check. + +2022-12-12 Tamar Christina <tamar.christina@arm.com> + + * match.pd: Add new rule. + +2022-12-12 Tamar Christina <tamar.christina@arm.com> + + * config/aarch64/aarch64.cc (aarch64_can_change_mode_class): Restrict + conversions between partial struct types properly. + +2022-12-12 Tamar Christina <tamar.christina@arm.com> + + * config/aarch64/aarch64.md (*tb<optab><mode>1): Rename to... + (*tb<optab><ALLI:mode><GPI:mode>1): ... this. + (tbranch_<code><mode>4): New. + * config/aarch64/iterators.md(ZEROM, zerom): New. + +2022-12-12 Tamar Christina <tamar.christina@arm.com> + + * dojump.cc (do_jump): Pass along value. + (do_jump_by_parts_greater_rtx): Likewise. + (do_jump_by_parts_zero_rtx): Likewise. + (do_jump_by_parts_equality_rtx): Likewise. + (do_compare_rtx_and_jump): Likewise. + (do_compare_and_jump): Likewise. + * dojump.h (do_compare_rtx_and_jump): New. + * optabs.cc (emit_cmp_and_jump_insn_1): Refactor to take optab to check. + (validate_test_and_branch): New. + (emit_cmp_and_jump_insns): Optiobally take a value, and when value is + supplied then check if it's suitable for tbranch. + * optabs.def (tbranch_eq$a4, tbranch_ne$a4): New. + * doc/md.texi (tbranch_@var{op}@var{mode}4): Document it. + * optabs.h (emit_cmp_and_jump_insns): New. + * tree.h (tree_zero_one_valued_p): New. + +2022-12-12 Tamar Christina <tamar.christina@arm.com> + + * config/aarch64/aarch64-simd.md (*aarch64_simd_movv2hf): New. + (mov<mode>, movmisalign<mode>, aarch64_dup_lane<mode>, + aarch64_store_lane0<mode>, aarch64_simd_vec_set<mode>, + @aarch64_simd_vec_copy_lane<mode>, vec_set<mode>, + reduc_<optab>_scal_<mode>, reduc_<fmaxmin>_scal_<mode>, + aarch64_reduc_<optab>_internal<mode>, aarch64_get_lane<mode>, + vec_init<mode><Vel>, vec_extract<mode><Vel>): Support V2HF. + (aarch64_simd_dupv2hf): New. + * config/aarch64/aarch64.cc (aarch64_classify_vector_mode): + Add E_V2HFmode. + * config/aarch64/iterators.md (VHSDF_P): New. + (V2F, VMOVE, nunits, Vtype, Vmtype, Vetype, stype, VEL, + Vel, q, vp): Add V2HF. + * config/arm/types.md (neon_fp_reduc_add_h): New. + +2022-12-12 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Define + __ARM_FEATURE_PAUTH and __ARM_FEATURE_BTI when appropriate. + * config/aarch64/aarch64.h (TARGET_BTI): Define. + +2022-12-12 Richard Biener <rguenther@suse.de> + + * genmatch.cc (dt_simplify::gen): Revert last change. + * match.pd: Revert simplification of CONSTUCTOR leaf handling. + (&x cmp SSA_NAME): Handle ADDR_EXPR in SSA defs. + * fold-const.cc (split_address_to_core_and_offset): Handle + ADDR_EXPRs in SSA defs. + (address_compare): Likewise. + +2022-12-12 Richard Biener <rguenther@suse.de> + + PR tree-optimization/89317 + * tree-ssa-ccp.cc (ccp_fold): Handle GIMPLE_COND via + gimple_fold_stmt_to_constant_1. + * match.pd (&a != &a + c): Apply to pointer_plus with non-ADDR_EXPR + base as well. + +2022-12-11 Richard Biener <rguenther@suse.de> + + PR tree-optimization/89317 + * match.pd ((p + b) - &p->c -> b - offsetof(c)): New patterns. + +2022-12-11 Richard Biener <rguenther@suse.de> + + * genmatch.cc (dt_node::gen_kids): Handle ADDR_EXPR in both + the GENERIC and GIMPLE op position. + (dt_simplify::gen): Capture both GENERIC and GIMPLE op + position for ADDR_EXPR and CONSTRUCTOR. + * match.pd: Simplify CONSTRUCTOR leaf handling. + +2022-12-11 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106904 + * tree.h (strip_zero_offset_components): Declare. + * tree.cc (strip_zero_offset_components): Define. + * tree-vect-data-refs.cc (vect_create_addr_base_for_vector_ref): + Strip zero offset components before building the address. + +2022-12-10 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/107997 + * tree-ssa-loop-ivopts.cc: Include cfganal.h. + (create_new_iv) <case IP_END>: If ip_end_pos bb is non-empty and ends + with a stmt which ends bb, instead of adding iv update after it split + the latch edge and insert iterator into the new latch bb. + +2022-12-09 Jiufu Guo <guojiufu@linux.ibm.com> + + * config/rs6000/rs6000.cc (rs6000_emit_set_const): Remove copy_rtx. + (rs6000_emit_set_long_const): Likewise. + +2022-12-09 Martin Liska <mliska@suse.cz> + + * config/i386/i386-builtins.cc (fold_builtin_cpu): Use same path + as for PR103661. + * doc/extend.texi: Fix "x86-64" use. + +2022-12-09 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * config/rtems.h (SUBTARGET_CC1_SPEC): Rename to... + (OS_CC1_SPEC): ...this. + * gcc.cc (SUBTARGET_CC1_SPEC): Rename to... + (OS_CC1_SPEC): ...this. + +2022-12-09 David Malcolm <dmalcolm@redhat.com> + + * Makefile.in (ANALYZER_OBJS): Update for renaming of + analyzer/region-model-impl-calls.cc to analyzer/kf.cc. + +2022-12-09 liuhongt <hongtao.liu@intel.com> + + * doc/invoke.texi (x86 options): Document + -mlam={none,u48,u57}. + * config/i386/i386-opts.h (enum lam_type): New enum. + * config/i386/i386.cc (ix86_memtag_can_tag_addresses): New. + (ix86_memtag_set_tag): Ditto. + (ix86_memtag_extract_tag): Ditto. + (ix86_memtag_add_tag): Ditto. + (ix86_memtag_tag_size): Ditto. + (ix86_memtag_untagged_pointer): Ditto. + (TARGET_MEMTAG_CAN_TAG_ADDRESSES): New. + (TARGET_MEMTAG_ADD_TAG): Ditto. + (TARGET_MEMTAG_SET_TAG): Ditto. + (TARGET_MEMTAG_EXTRACT_TAG): Ditto. + (TARGET_MEMTAG_UNTAGGED_POINTER): Ditto. + (TARGET_MEMTAG_TAG_SIZE): Ditto. + (IX86_HWASAN_SHIFT): Ditto. + (IX86_HWASAN_TAG_SIZE): Ditto. + * config/i386/i386-expand.cc (ix86_expand_call): Untag code + pointer. + * config/i386/i386-options.cc (ix86_option_override_internal): + Error when enable -mlam=[u48|u57] for 32-bit code. + * config/i386/i386.opt: Add -mlam=[none|u48|u57]. + * config/i386/i386-protos.h (ix86_memtag_untagged_pointer): + Declare. + (ix86_memtag_can_tag_addresses): Ditto. + +2022-12-08 Marek Polacek <polacek@redhat.com> + + * doc/invoke.texi (-fsanitize=address): Suggest options to improve + stack traces. + +2022-12-08 Eugene Rozenfeld <erozen@microsoft.com> + + PR ipa/108000 + * ipa-cp.cc (ipcp_propagate_stage): Fix profile count comparison + +2022-12-08 David Faust <david.faust@oracle.com> + + * config/bpf/bpf.md (bswap<mode>2): New define_insn. + +2022-12-08 Sebastian Pop <spop@amazon.com> + + PR target/98776 + * config/aarch64/aarch64-protos.h (aarch64_output_patchable_area): + Declared. + * config/aarch64/aarch64.cc (aarch64_print_patchable_function_entry): + Emit an UNSPECV_PATCHABLE_AREA pseudo instruction. + (aarch64_output_patchable_area): New. + * config/aarch64/aarch64.md (UNSPECV_PATCHABLE_AREA): New. + (patchable_area): Define. + +2022-12-08 Jakub Jelinek <jakub@redhat.com> + + PR debug/106719 + * cfgbuild.cc (find_bb_boundaries): If there are NOTEs in between + debug_insn (seen after flow_transfer_insn) and insn, move NOTEs + before all the DEBUG_INSNs and split after NOTEs. If there are + other insns like jump table data, clear debug_insn. + +2022-12-08 Jakub Jelinek <jakub@redhat.com> + + PR target/107627 + * config/i386/i386.md (HALF, half): New mode attributes. + (*concat<half><mode>3_5, *concat<mode><dwi>3_6, + *concat<mode><dwi>3_7): New define_insn_and_split patterns. + +2022-12-08 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/107985 + * gimple-range-op.cc + (gimple_range_op_handler::gimple_range_op_handler): Check if type + of the operands is supported. + * gimple-range.cc (gimple_ranger::prefill_stmt_dependencies): Do + not assert if here is no range-op handler. + +2022-12-08 Jiufu Guo <guojiufu@linux.ibm.com> + + * config/rs6000/predicates.md: Use sext_hwi. + * config/rs6000/rs6000.cc (num_insns_constant_gpr): Likewise. + (darwin_rs6000_legitimate_lo_sum_const_p): Likewise. + (mem_operand_gpr): Likewise. + (mem_operand_ds_form): Likewise. + (rs6000_legitimize_address): Likewise. + (rs6000_emit_set_const): Likewise. + (rs6000_emit_set_long_const): Likewise. + (print_operand): Likewise. + (constant_generates_xxspltiw): Remove unnecessary expressions. + * config/rs6000/rs6000.md: Use sext_hwi. + +2022-12-08 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107699 + * match.pd (&a !=/== &a.b + c -> (&a - &a.b) !=/== c): New + pattern variant. + +2022-12-08 Jakub Jelinek <jakub@redhat.com> + + * range-op-float.cc (frange_nextafter): For MODE_COMPOSITE_P from + denormal or zero, use real_nextafter on DFmode with conversions + around it. + (frange_arithmetic): For mode_composite, on top of rounding in the + right direction accept extra 1ulp error for PLUS/MINUS_EXPR, extra + 2ulps error for MULT_EXPR and extra 3ulps error for RDIV_EXPR. + +2022-12-08 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/107967 + * range-op-float.cc (frange_arithmetic): Fix a thinko - if + inf is negative, use nextafter if !real_less (&result, &value) + rather than if real_less (&result, &value). If result is +-INF + while value is finite and -fno-rounding-math, don't do rounding + if !inexact or if result is significantly above max representable + value or below min representable value. + +2022-12-07 Max Filippov <jcmvbkbc@gmail.com> + + * config.gcc (xtensa*-*-*): Add xtensa-dynconfig.o to extra_objs. + * config/xtensa/t-xtensa (TM_H): Add xtensa-dynconfig.h. + (xtensa-dynconfig.o): New rule. + * config/xtensa/xtensa-dynconfig.c: New file. + * config/xtensa/xtensa-protos.h (xtensa_get_config_strings): New + declaration. + * config/xtensa/xtensa.h (xtensa-config.h): Replace #include + with xtensa-dynconfig.h + (XCHAL_HAVE_MUL32_HIGH, XCHAL_HAVE_RELEASE_SYNC) + (XCHAL_HAVE_S32C1I, XCHAL_HAVE_THREADPTR) + (XCHAL_HAVE_FP_POSTINC): Drop definitions. + (TARGET_DIV32): Replace with __XCHAL_HAVE_DIV32. + (TARGET_CPU_CPP_BUILTINS): Add new 'builtin' variable and loop + through string array returned by the xtensa_get_config_strings + function call. + +2022-12-07 Wilco Dijkstra <wilco.dijkstra@arm.com> + + PR target/108006 + * config/aarch64/aarch64.cc (aarch64_expand_sve_const_vector): + Fix call to aarch64_move_imm to use SI/DI. + +2022-12-07 Richard Biener <rguenther@suse.de> + + PR ipa/105676 + * ipa-pure-const.cc (ipa_make_function_pure): Skip also + for functions already being const. + +2022-12-07 Hongyu Wang <hongyu.wang@intel.com> + + * config/i386/x86-tune.def (X86_TUNE_AVOID_256FMA_CHAINS): Add + m_SAPPHIRERAPIDS, m_ALDERLAKE and m_CORE_ATOM. + +2022-12-07 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> + + PR target/107920 + * config/aarch64/aarch64-sve-builtins-base.cc: Use + gsi_replace_with_seq_vops to handle virtual operands, and gate + the transform on !flag_non_call_exceptions. + * gimple-fold.cc (gsi_replace_with_seq_vops): Make function non static. + * gimple-fold.h (gsi_replace_with_seq_vops): Declare. + +2022-12-07 liuhongt <hongtao.liu@intel.com> + + PR target/107970 + * config/i386/mmx.md (btruncv2sf2): Add TARGET_MMX_WITH_SSE to + the condition. + +2022-12-06 Wilco Dijkstra <wilco.dijkstra@arm.com> + + * config/aarch64/aarch64.cc (aarch64_bitmask_imm): Use unsigned type. + (aarch64_is_mov_xn_imm): New function. + (aarch64_move_imm): Refactor, assert mode is SImode or DImode. + (aarch64_internal_mov_immediate): Assert mode is SImode or DImode. + Simplify special cases. + (aarch64_uimm12_shift): Simplify code. + (aarch64_clamp_to_uimm12_shift): Likewise. + (aarch64_movw_imm): Rename to aarch64_is_movz. + (aarch64_float_const_rtx_p): Pass either SImode or DImode to + aarch64_internal_mov_immediate. + (aarch64_rtx_costs): Likewise. + * config/aarch64/aarch64.md (movdi_aarch64): Merge 'N' and 'M' + constraints into single 'O'. + (mov<mode>_aarch64): Likewise. + * config/aarch64/aarch64-protos.h (aarch64_move_imm): Use unsigned. + (aarch64_bitmask_imm): Likewise. + (aarch64_uimm12_shift): Likewise. + (aarch64_is_mov_xn_imm): New prototype. + * config/aarch64/constraints.md: Add 'O' for 32/64-bit immediates, + limit 'N' to 64-bit only moves. + +2022-12-06 Qing Zhao <qing.zhao@oracle.com> + + * attribs.cc (strict_flex_array_level_of): New function. + * attribs.h (strict_flex_array_level_of): Prototype for new function. + * doc/invoke.texi: Update -Warray-bounds by specifying the impact from + -fstrict-flex-arrays. Also update -Warray-bounds=2 by eliminating its + impact on treating trailing arrays as flexible array members. + * gimple-array-bounds.cc (get_up_bounds_for_array_ref): New function. + (check_out_of_bounds_and_warn): New function. + (array_bounds_checker::check_array_ref): Update with call to the above + new functions. + * tree.cc (array_ref_flexible_size_p): Add one new argument. + (component_ref_sam_type): New function. + (component_ref_size): Control with level of strict-flex-array. + * tree.h (array_ref_flexible_size_p): Update prototype. + (enum struct special_array_member): Add two new enum values. + (component_ref_sam_type): New prototype. + +2022-12-06 David Malcolm <dmalcolm@redhat.com> + + * doc/analyzer.texi: Drop out-of-date ideas for other checkers. + +2022-12-06 David Malcolm <dmalcolm@redhat.com> + + * Makefile.in (ANALYZER_OBJS): Add analyzer/call-details.o, + analyzer/kf-analyzer.o, and kf-lang-cp.o. + +2022-12-06 Marcel Vollweiler <marcel@codesourcery.com> + + * gimplify.cc (optimize_target_teams): Set initial num_teams_upper + to "-2" instead of "1" for non-existing num_teams clause in order to + disambiguate from the case of an existing num_teams clause with value 1. + +2022-12-06 Andre Vieira <andre.simoesdiasvieira@arm.com> + + PR target/107987 + * config/arm/mve.md (mve_vcmp<mve_cmp_op>q_n_<mode>, + @mve_vcmp<mve_cmp_op>q_n_f<mode>): Apply vec_duplicate to scalar + operand. + +2022-12-06 Jakub Jelinek <jakub@redhat.com> + + PR target/107969 + * config/i386/i386.md (cbranchbf4, cstorebf4): Guard expanders + with the same condition as cbranchsf4 or cstoresf4 expanders. + +2022-12-06 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104475 + * pointer-query.h (access_ref::ref_nullptr_p): New flag. + * pointer-query.cc (access_ref::access_ref): Initialize + ref_nullptr_p. + (compute_objsize_r): Set ref_nullptr_p if we treat it that way. + (access_ref::inform_access): If ref was treated as nullptr + based, indicate that. + +2022-12-06 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/107972 + * range-op-float.cc (frange_drop_infs): New function. + (float_binary_op_range_finish): Add DIV_OP2 argument. If DIV_OP2 is + false and lhs is finite or if DIV_OP2 is true and lhs is non-zero and + not NAN, r must be finite too. + (foperator_div::op2_range): Pass true to DIV_OP2 of + float_binary_op_range_finish. + +2022-12-06 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/107975 + * range-op-float.cc (foperator_mult::op1_range, + foperator_div::op1_range, foperator_div::op2_range): Just + return float_binary_op_range_finish result if lhs is known + NAN, or the other operand is known NAN or UNDEFINED. + +2022-12-06 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> + + * config/aarch64/aarch64.cc (aarch64_expand_vector_init): Use dup + and zip1 for interleaving elements in vector initializer. + +2022-12-05 Richard Biener <rguenther@suse.de> + + PR middle-end/40635 + * tree-into-ssa.cc (rewrite_update_phi_arguments): Only + update the argument when the reaching definition is different + from the current argument. Keep an existing argument + location. + +2022-12-05 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106868 + * gimple-ssa-warn-access.cc (pass_waccess::gimple_call_return_arg_ref): + Inline into single user ... + (pass_waccess::check_dangling_uses): ... here and adjust the + call and the PHI case to require that ref.aref is the address + of the decl. + +2022-12-05 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/106805 + * match.pd (cmp @0 REAL_CST@1): Don't optimize x cmp NaN + or NaN cmp x to false/true for cmp >/>=/</<= if -ftrapping-math. + +2022-12-05 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/107879 + * range-op-float.cc (foperator_mult::op1_range): If both + lhs and op2 ranges contain zero or both ranges contain + some infinity, set r range to zero_to_inf_range depending on + signbit_known_p. + (foperator_div::op2_range): Similarly for lhs and op1 ranges. + (foperator_div::op1_range): If lhs range contains zero and op2 + range contains some infinity or vice versa, set r range to + zero_to_inf_range depending on signbit_known_p. + (foperator_div::rv_fold): Fix up condition for returning known NAN. + +2022-12-05 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107833 + PR tree-optimization/107839 + * cfghooks.cc: Include tree.h. + * tree-ssa-loop-im.cc (movement_possibility): Wrap and + make stmts using any ssa_name_maybe_undef_p operand + to preserve execution. + (loop_invariant_motion_in_fun): Call mark_ssa_maybe_undefs + to init maybe-undefined status. + * tree-ssa-loop-ivopts.cc (ssa_name_maybe_undef_p, + ssa_name_set_maybe_undef, ssa_name_any_use_dominates_bb_p, + mark_ssa_maybe_undefs): Move ... + * tree-ssa.cc: ... here. + * tree-ssa.h (ssa_name_any_use_dominates_bb_p, + mark_ssa_maybe_undefs): Declare. + (ssa_name_maybe_undef_p, ssa_name_set_maybe_undef): Define. + +2022-12-05 Andrew Pinski <pinskia@gmail.com> + + PR tree-optimization/107956 + * tree-vect-patterns.cc (vect_recog_mask_conversion_pattern): + Check for NULL LHS on masked loads. + +2022-12-05 Kewen Lin <linkw@linux.ibm.com> + Richard Sandiford <richard.sandiford@arm.com> + + PR tree-optimization/107412 + * gimple-fold.cc (gimple_fold_partial_load_store_mem_ref): Use + untruncated type for the length, and avoid to_constant and tree + arithmetic for subtraction. + +2022-12-02 Bernhard Reutner-Fischer <rep.dot.nop@gmail.com> + Jason Merrill <jason@redhat.com> + + * function.cc (init_function_start): Use DECL_RESULT location + for -Waggregate-return warning. + +2022-12-02 Andrew MacLeod <amacleod@redhat.com> + + * fold-const.cc (fold_unary_loc): Check TREE_TYPE of node. + (tree_invalid_nonnegative_warnv_p): Likewise. + +2022-12-02 Jason Merrill <jason@redhat.com> + + * gcc.cc (validate_switches): Reset suffix/starred on loop. + +2022-12-02 Vladimir N. Makarov <vmakarov@redhat.com> + + * lra-constraints.cc (curr_insn_transform): Check available hard + regs for pseudo and its subreg to decide what to reload. + +2022-12-02 liuhongt <hongtao.liu@intel.com> + + * config/i386/i386-expand.cc + (ix86_expand_fast_convert_bf_to_sf): Use extendbfsf2_1 for + nonimmediate operand. + +2022-12-02 Martin Liska <mliska@suse.cz> + + * configure: Regenerate. + +2022-12-02 Jakub Jelinek <jakub@redhat.com> + + PR target/106577 + * config/i386/i386-expand.cc (ix86_vector_duplicate_value): Save/restore + recog_data around recog_memoized calls. + +2022-12-02 Michael Collison <collison@rivosinc.com> + + * match.pd ((x & 0x1) == 0) ? y : z <op> y + -> (-(typeof(y))(x & 0x1) & z) <op> y. + +2022-12-02 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107946 + * params.opt (-param=max-unswitch-depth=): New. + * doc/invoke.texi (--param=max-unswitch-depth): Document. + * tree-ssa-loop-unswitch.cc (init_loop_unswitch_info): Honor + --param=max-unswitch-depth + +2022-12-02 Eric Gallager <egallager@gcc.gnu.org> + + PR bootstrap/59447 + * configure: Regenerate. + * configure.ac: Document --with-dwarf2 flag as also + applying to later DWARF standards. + * doc/install.texi: Likewise. + +2022-12-02 liuhongt <hongtao.liu@intel.com> + + PR target/107934 + * config/i386/i386.md (extendbfsf2_1): Change type from + sseishft to sseishft1. + +2022-12-01 Alex Coplan <alex.coplan@arm.com> + + * varasm.cc (assemble_variable): Fix type confusion bug when + checking for ".vtable_map_vars" section. + +2022-12-01 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-v.cc (emit_pred_op): Adapt for mask mode. + * config/riscv/vector.md: Remove Tail && make policy operand for mask mode mov. + +2022-12-01 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-protos.h (enum vlmul_type): New enum. + (get_vlmul): New function. + (get_ratio): Ditto. + * config/riscv/riscv-v.cc (struct mode_vtype_group): New struct. + (ENTRY): Adapt for attributes. + (enum vlmul_type): New enum. + (get_vlmul): New function. + (get_ratio): New function. + * config/riscv/riscv-vector-switch.def (ENTRY): Adapt for attributes. + * config/riscv/riscv.cc (ENTRY): Ditto. + * config/riscv/vector.md (false,true): Add attributes. + +2022-12-01 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/constraints.md (Wdm): New constraint. + * config/riscv/predicates.md (direct_broadcast_operand): New predicate. + * config/riscv/riscv-protos.h (RVV_VLMAX): New macro. + (emit_pred_op): Refine function. + * config/riscv/riscv-selftests.cc (run_const_vector_selftests): New function. + (run_broadcast_selftests): Ditto. + (BROADCAST_TEST): New tests. + (riscv_run_selftests): More tests. + * config/riscv/riscv-v.cc (emit_pred_move): Refine function. + (emit_vlmax_vsetvl): Ditto. + (emit_pred_op): Ditto. + (expand_const_vector): New function. + (legitimize_move): Add constant vector support. + * config/riscv/riscv.cc (riscv_print_operand): New asm print rule for const vector. + * config/riscv/riscv.h (X0_REGNUM): New macro. + * config/riscv/vector-iterators.md: New attribute. + * config/riscv/vector.md (vec_duplicate<mode>): New pattern. + (@pred_broadcast<mode>): New pattern. + +2022-12-01 Paul-Antoine Arras <pa@codesourcery.com> + + * config/gcn/gcn-opts.h (TARGET_FIJI): -march=fiji. + (TARGET_VEGA10): -march=gfx900. + (TARGET_VEGA20): -march=gfx906. + (TARGET_GFX908): -march=gfx908. + (TARGET_GFX90a): -march=gfx90a. + * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Define a builtin that + uniquely maps to '-march'. + +2022-12-01 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107937 + * gimple-predicate-analysis.h (predicate::is_true): New. + (predicate::is_false): Likewise. + (predicate::empty_val): Likewise. + (uninit_analysis::uninit_analysis): Properly initialize + def_preds. + * gimple-predicate-analysis.cc (simplify_1b): Indicate + whether the chain became empty. + (predicate::simplify): Release emptied chain before removing it. + (predicate::normalize): Replace temporary object with assertion. + (uninit_analysis::is_use_guarded): Deal with predicates + that simplify to true/false. + +2022-12-01 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107935 + * tree-ssa-sccvn.cc (visit_phi): Honor forced VARYING on + backedges. + +2022-12-01 Jakub Jelinek <jakub@redhat.com> + + PR target/107627 + * config/i386/i386.md (*concat<mode><dwi>3_1, *concat<mode><dwi>3_2): + For operands which are zero_extend arguments allow memory if + output operand is a register. + (*concat<mode><dwi>3_3, *concat<mode><dwi>3_4): Likewise. If + both input operands are memory, use early clobber on output operand. + * config/i386/i386-expand.cc (split_double_concat): Deal with corner + cases where one input is memory and the other is not and the address + of the memory input uses a register we'd overwrite before loading + the memory into a register. + +2022-12-01 Haochen Gui <guihaoc@gcc.gnu.org> + + * config/rs6000/rs6000-call.cc (swap_endian_selector_for_mode): + Corrects comments of this function and make them clear. + +2022-12-01 liuhongt <hongtao.liu@intel.com> + + PR target/107863 + * config/i386/i386-expand.cc (ix86_expand_vec_set_builtin): + Convert op1 to target mode whenever mode mismatch. + +2022-12-01 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/106626 + * diagnostic-path.h + (diagnostic_path::get_first_event_in_a_function): New decl. + * diagnostic.cc (diagnostic_path::get_first_event_in_a_function): + New. + (diagnostic_path::interprocedural_p): Ignore leading events that + are outside of any function. + +2022-12-01 David Malcolm <dmalcolm@redhat.com> + + * Makefile.in (ANALYZER_OBJS): Add analyzer/bounds-checking.o. + +2022-12-01 Haochen Gui <guihaoc@gcc.gnu.org> + + PR target/100866 + * config/rs6000/rs6000-call.cc (swap_endian_selector_for_mode): + Generate permute index directly for little endian targets. + * config/rs6000/vsx.md (revb_<mode>): Call vprem directly with + corresponding permute indexes. + +2022-11-30 John David Anglin <danglin@gcc.gnu.org> + + * config/pa/pa.md (addvdi3): Force operand 2 to a register. + Remove "addi,tsv,*" instruction from unamed pattern. + (subvdi3): Force operand 1 to a register. + Remove "subi,tsv" instruction from from unamed pattern. + +2022-11-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/aarch64.md (aarch64_cpymemdi): Specify clobber of CC reg. + (*aarch64_cpymemdi): Likewise. + (aarch64_movmemdi): Likewise. + (aarch64_setmemdi): Likewise. + (*aarch64_setmemdi): Likewise. + +2022-11-30 Martin Liska <mliska@suse.cz> + + * tree-switch-conversion.cc (bit_test_cluster::emit): Remove + dead variable bt_range. + +2022-11-30 Iskander Shakirzyanov <iskander@ispras.ru> + Franz Sirl <Franz.Sirl-kernel@lauterbach.com> + + PR driver/107787 + * common.opt (Warray-bounds): Turn into alias of + -Warray-bounds=1. + * builtins.cc (c_strlen): Use OPT_Warray_bounds_ + instead of OPT_Warray_bounds. + * diagnostic-spec.cc (nowarn_spec_t::nowarn_spec_t): Ditto. + * gimple-array-bounds.cc (array_bounds_checker::check_array_ref, + array_bounds_checker::check_mem_ref, + array_bounds_checker::check_addr_expr, + array_bounds_checker::check_array_bounds): Ditto. + * gimple-ssa-warn-restrict.cc (maybe_diag_access_bounds): Ditto. + +2022-11-30 Martin Liska <mliska@suse.cz> + + PR tree-optimization/101301 + PR tree-optimization/103680 + * tree-switch-conversion.cc (bit_test_cluster::emit): + Handle correctly remaining probability. + (switch_decision_tree::try_switch_expansion): Fix BB's count + where a cluster expansion happens. + (switch_decision_tree::emit_cmp_and_jump_insns): Fill up also + BB count. + (switch_decision_tree::do_jump_if_equal): Likewise. + (switch_decision_tree::emit_case_nodes): Handle special case + for BT expansion which can also fallback to a default BB. + * tree-switch-conversion.h (cluster::cluster): Add + m_default_prob probability. + +2022-11-30 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107919 + * gimple-predicate-analysis.cc (simplify_1): Rename to ... + (simplify_1a): .. this. + (simplify_1b): New. + (predicate::simplify): Call both simplify_1a and simplify_1b. + +2022-11-30 Richard Biener <rguenther@suse.de> + + * tree-ssa-uninit.cc (find_uninit_use): Dump the edge for a + PHI node. + +2022-11-30 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107919 + * gimple-predicate-analysis.cc (predicate::simplify_2): + Handle predicates of arbitrary length. + +2022-11-30 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/107835 + * tree-chrec.cc (chrec_apply): Don't handle "{a, +, a} (x-1)" + as "a*x" if type is a pointer type. + +2022-11-30 Paul-Antoine Arras <pa@codesourcery.com> + + * config/gcn/gcn.cc (gcn_omp_device_kind_arch_isa): Add gfx803. + * config/gcn/t-omp-device: Add gfx803. + +2022-11-30 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/linux.h (STACK_CHECK_MOVING_SP): + Define this macro to 1. + * config/loongarch/loongarch.cc (STACK_CLASH_PROTECTION_GUARD_SIZE): + Size of guard page. + (loongarch_first_stack_step): Return the size of the first drop stack + according to whether stack checking is performed. + (loongarch_emit_probe_stack_range): Adjust the method of stack checking in prologue. + (loongarch_output_probe_stack_range): Delete useless code. + (loongarch_expand_prologue): Adjust the method of stack checking in prologue. + (loongarch_option_override_internal): Enforce that interval is the same + size as size so the mid-end does the right thing. + * config/loongarch/loongarch.h (STACK_CLASH_MAX_UNROLL_PAGES): + New macro decide whether to loop stack detection. + +2022-11-30 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/103546 + * doc/invoke.texi (Static Analyzer Options): Add isatty, ferror, + fileno, and getc to the list of functions known to the analyzer. + +2022-11-29 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107852 + * tree-ssa-sccvn.cc (visit_phi): Use equivalences recorded + as predicated values to elide more redundant PHIs. + +2022-11-29 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106995 + * tree-if-conv.cc (pass_if_conversion::execute): Also redirect the + versioning condition to the original loop if this very loop + vanished during CFG cleanup. + +2022-11-29 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107898 + * gimple-ssa-warn-alloca.cc (alloca_call_type): Check + the type of the alloca argument is compatible with size_t + before querying ranges. + +2022-11-29 Richard Biener <rguenther@suse.de> + + PR ipa/107897 + * multiple_target.cc (pass_target_clone::gate): Disable + after errors. + +2022-11-29 Martin Liska <mliska@suse.cz> + + * configure: Regenerate. + +2022-11-29 YunQiang Su <yunqiang.su@cipunited.com> + + * configure.ac: add description for + AC_DEFINE(ENABLE_MULTIARCH, 1) + +2022-11-28 Andrew Pinski <apinski@marvell.com> + + * match.pd ((A / (1 << B)) -> (A >> B).): + Fix comment. + +2022-11-28 Sinan <sinan.lin@linux.alibaba.com> + + * config/riscv/riscv.cc (riscv_build_integer): Improve some cases + of loading 64bit constants for rv32. + +2022-11-28 Maciej W. Rozycki <macro@embecosm.com> + + * config/riscv/riscv.cc (riscv_emit_int_order_test): Use EQ 0 + rather that XOR 1 for LE and LEU operations. + +2022-11-28 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107896 + * tree-vect-stmts.cc (supportable_widening_operation): + Handle non-vector mode intermediate mode. + +2022-11-28 Frolov Daniil <frolov.da@phystech.edu> + + * gimple-ssa-sprintf.cc (fmtresult::type_max_digits): Handle + base == 2. + (tree_digits): Likewise. + (format_integer): Likewise. + (parse_directive): Add cases for %b and %B directives. + +2022-11-28 Fei Gao <gaofei@eswincomputing.com> + + * config/riscv/riscv.cc (riscv_first_stack_step): Fix computation + of MIN_FIRST_STEP to cover FP save area too. + +2022-11-28 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107493 + * tree-scalar-evolution.cc (scev_dfs::follow_ssa_edge_expr): + Only handle no-op and sign-changing conversions. + +2022-11-28 Tobias Burnus <tobias@codesourcery.com> + + * config/gcn/gcn.cc (gcn_expand_builtin_1): Work on s1 instead + of s[0:1] and use USE to prevent removal of setting that register. + * config/gcn/gcn.md (prologue_use_di): Remove. + +2022-11-28 Yuri Gribov <y.gribov@samsung.com> + + PR sanitizer/106558 + * sanopt.cc: Do not optimize out checks for non-SSA addresses. + +2022-11-28 Jakub Jelinek <jakub@redhat.com> + + PR target/106875 + * config/i386/i386.opt (x_ix86_abi): Remove TargetSave. + (ix86_abi): Replace it with TargetVariable. + * config/i386/i386-options.cc (ix86_function_specific_save, + ix86_function_specific_restore): Don't save and restore x_ix86_abi. + +2022-11-28 Andrea Corallo <andrea.corallo@arm.com> + + * config/arm/mve.md (mve_vrmlaldavhq_<supf>v4si, + mve_vrmlaldavhaq_<supf>v4si): Fix spacing vs tabs. + +2022-11-28 Andrea Corallo <andrea.corallo@arm.com> + + * config/arm/mve.md (mve_vmlaldavaq_<supf><mode>) + (mve_vmlaldavaxq_s<mode>, mve_vmlaldavaxq_p_<supf><mode>): Fix + spacing vs tabs. + +2022-11-28 Andrea Corallo <andrea.corallo@arm.com> + + * config/arm/mve.md (mve_vsubq_n_f<mode>): Fix spacing. + +2022-11-28 Andrea Corallo <andrea.corallo@arm.com> + + * config/arm/mve.md (mve_vaddlvq_p_<supf>v4si) + (mve_vaddq_n_<supf><mode>, mve_vaddvaq_<supf><mode>) + (mve_vaddlvaq_<supf>v4si, mve_vaddq_n_f<mode>) + (mve_vaddlvaq_p_<supf>v4si, mve_vaddq<mode>, mve_vaddq_f<mode>): + Fix spacing. + +2022-11-28 Stam Markianos-Wright <stam.markianos-wright@arm.com> + + * config/arm/arm_mve.h (__arm_vsubq_x FP): New overloads. + (__arm_vsubq_x Integer): New. + +2022-11-28 Stam Markianos-Wright <stam.markianos-wright@arm.com> + + PR target/107515 + * config/arm/arm_mve.h (__ARM_mve_typeid): Add float types. + +2022-11-28 Stam Markianos-Wright <stam.markianos-wright@arm.com> + + PR target/96795 + * config/arm/arm_mve.h (__arm_vaddq): Fix Overloading. + (__arm_vmulq): Likewise. + (__arm_vcmpeqq): Likewise. + (__arm_vcmpneq): Likewise. + (__arm_vmaxnmavq): Likewise. + (__arm_vmaxnmvq): Likewise. + (__arm_vminnmavq): Likewise. + (__arm_vsubq): Likewise. + (__arm_vminnmvq): Likewise. + (__arm_vrshlq): Likewise. + (__arm_vqsubq): Likewise. + (__arm_vqdmulltq): Likewise. + (__arm_vqdmullbq): Likewise. + (__arm_vqdmulhq): Likewise. + (__arm_vqaddq): Likewise. + (__arm_vhaddq): Likewise. + (__arm_vhsubq): Likewise. + (__arm_vqdmlashq): Likewise. + (__arm_vqrdmlahq): Likewise. + (__arm_vmlasq): Likewise. + (__arm_vqdmlahq): Likewise. + (__arm_vmaxnmavq_p): Likewise. + (__arm_vmaxnmvq_p): Likewise. + (__arm_vminnmavq_p): Likewise. + (__arm_vminnmvq_p): Likewise. + (__arm_vfmasq_m): Likewise. + (__arm_vsetq_lane): Likewise. + (__arm_vcmpneq_m): Likewise. + (__arm_vhaddq_x): Likewise. + (__arm_vhsubq_x): Likewise. + (__arm_vqrdmlashq_m): Likewise. + (__arm_vqdmlashq_m): Likewise. + (__arm_vmlaldavaxq_p): Likewise. + (__arm_vmlasq_m): Likewise. + (__arm_vqdmulhq_m): Likewise. + (__arm_vqdmulltq_m): Likewise. + (__arm_viwdupq_m): Likewise. + (__arm_viwdupq_u16): Likewise. + (__arm_viwdupq_u32): Likewise. + (__arm_viwdupq_u8): Likewise. + (__arm_vdwdupq_m): Likewise. + (__arm_vdwdupq_u16): Likewise. + (__arm_vdwdupq_u32): Likewise. + (__arm_vdwdupq_u8): Likewise. + (__arm_vaddlvaq): Likewise. + (__arm_vaddlvaq_p): Likewise. + (__arm_vaddvaq): Likewise. + (__arm_vaddvaq_p): Likewise. + (__arm_vcmphiq_m): Likewise. + (__arm_vmladavaq_p): Likewise. + (__arm_vmladavaxq): Likewise. + (__arm_vmlaldavaxq): Likewise. + (__arm_vrmlaldavhaq_p): Likewise. + +2022-11-28 Stam Markianos-Wright <stam.markianos-wright@arm.com> + + PR target/96795 + * config/arm/arm_mve.h (__arm_vaddq_m_n_s8): Change types. + (__arm_vaddq_m_n_s32): Likewise. + (__arm_vaddq_m_n_s16): Likewise. + (__arm_vaddq_m_n_u8): Likewise. + (__arm_vaddq_m_n_u32): Likewise. + (__arm_vaddq_m_n_u16): Likewise. + (__arm_vaddq_m): Fix Overloading. + (__ARM_mve_coerce3): New. + +2022-11-28 Andrea Corallo <andrea.corallo@arm.com> + + * config/arm/mve.md (mve_vabsq_f<mode>): Fix spacing. + +2022-11-28 Andrea Corallo <andrea.corallo@arm.com> + + * config/arm/mve.md (@mve_vcmp<mve_cmp_op>q_<mode>): Fix + spacing. + * config/arm/arm_mve.h (__arm_vcmpgtq_m, __arm_vcmpleq_m) + (__arm_vcmpltq_m, __arm_vcmpneq_m): Add missing defines. + +2022-11-28 Andrea Corallo <andrea.corallo@arm.com> + + * config/arm/mve.md (mve_vdupq_n_f<mode>) + (mve_vdupq_n_<supf><mode>, mve_vdupq_m_n_<supf><mode>) + (mve_vdupq_m_n_f<mode>): Fix spacing. + +2022-11-28 Andrea Corallo <andrea.corallo@arm.com> + + * config/arm/mve.md (mve_vdwdupq_m_wb_u<mode>_insn): Fix spacing. + +2022-11-28 Andrea Corallo <andrea.corallo@arm.com> + + * config/arm/mve.md (mve_vddupq_u<mode>_insn): Fix 'vddup.u' + spacing. + (mve_vddupq_m_wb_u<mode>_insn): Likewise. + +2022-11-28 Andrea Corallo <andrea.corallo@arm.com> + + * config/arm/vfp.md (*thumb2_movhi_vfp, *thumb2_movhi_fp16): Fix + 'vmsr' spacing and reg capitalization. + +2022-11-28 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107876 + * tree-ssa-loop-unswitch.cc (clean_up_after_unswitching): Wipe + dominator info if we removed an edge. + +2022-11-28 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107867 + * tree-ssa-forwprop.cc (pass_forwprop::execute): Handle + abnormal cleanup after substitution. + +2022-11-28 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/loongarch.cc (enum loongarch_load_imm_method): + Remove the member METHOD_INSV that is not currently used. + (struct loongarch_integer_op): Define a new member curr_value, + that records the value of the number stored in the destination + register immediately after the current instruction has run. + (loongarch_build_integer): Assign a value to the curr_value member variable. + (loongarch_move_integer): Adds information for the immediate load instruction. + * config/loongarch/loongarch.md (*movdi_32bit): Redefine as define_insn_and_split. + (*movdi_64bit): Likewise. + (*movsi_internal): Likewise. + (*movhi_internal): Likewise. + * config/loongarch/predicates.md: Return true as long as it is CONST_INT, ensure + that the immediate number is not optimized by decomposition during expand + optimization loop. + +2022-11-28 liuhongt <hongtao.liu@intel.com> + + PR target/107748 + * config/i386/avx512bf16intrin.h (_mm_cvtsbh_ss): Refined. + * config/i386/i386-builtin-types.def (FLOAT_FTYPE_BFLOAT16): + New function type. + * config/i386/i386-builtin.def (BDESC): New builtin. + * config/i386/i386-expand.cc (ix86_expand_args_builtin): + Handle the builtin. + * config/i386/i386.md (extendbfsf2): New expander. + (extendbfsf2_1): New define_insn. + (truncsfbf2): Ditto. + +2022-11-26 Andrew Pinski <apinski@marvell.com> + + PR tree-optimization/103356 + * match.pd: ((~a) == b -> a ^ b): New pattern. + +2022-11-25 Sandra Loosemore <sandra@codesourcery.com> + + * common.opt (fopenmp-target-simd-clone): New option. + (target_simd_clone_device): New enum to go with it. + * doc/invoke.texi (-fopenmp-target-simd-clone): Document. + * flag-types.h (enum omp_target_simd_clone_device_kind): New. + * omp-simd-clone.cc (auto_simd_fail): New function. + (auto_simd_check_stmt): New function. + (plausible_type_for_simd_clone): New function. + (ok_for_auto_simd_clone): New function. + (simd_clone_create): Add force_local argument, make the symbol + have internal linkage if it is true. + (expand_simd_clones): Also check for cloneable functions with + "omp declare target". Pass explicit_p argument to + simd_clone.compute_vecsize_and_simdlen target hook. + * opts.cc (default_options_table): Add -fopenmp-target-simd-clone. + * target.def (TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN): + Add bool explicit_p argument. + * doc/tm.texi: Regenerated. + * config/aarch64/aarch64.cc + (aarch64_simd_clone_compute_vecsize_and_simdlen): Update. + * config/gcn/gcn.cc + (gcn_simd_clone_compute_vecsize_and_simdlen): Update. + * config/i386/i386.cc + (ix86_simd_clone_compute_vecsize_and_simdlen): Update. + +2022-11-25 Tamar Christina <tamar.christina@arm.com> + + PR target/107830 + * config/aarch64/aarch64.cc + (aarch64_vectorize_can_special_div_by_constant): Check validity during + codegen phase as well. + +2022-11-25 Eric Botcazou <ebotcazou@adacore.com> + + * range-op.cc (operator_bitwise_xor::op1_range): Fix thinko. + +2022-11-25 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107865 + * tree-cfg.cc (move_sese_region_to_fn): Free the number of + iterations of moved loops. + +2022-11-25 Kewen.Lin <linkw@gcc.gnu.org> + + PR target/99889 + * config/rs6000/rs6000.cc (rs6000_print_patchable_function_entry): + Adjust to call function default_print_patchable_function_entry. + * targhooks.cc (default_print_patchable_function_entry_1): Remove and + move the flags preparation ... + (default_print_patchable_function_entry): ... here, adjust to use + current_function_funcdef_no for label no. + * targhooks.h (default_print_patchable_function_entry_1): Remove. + * varasm.cc (default_elf_asm_named_section): Adjust code for + __patchable_function_entries section support with LPFE label. + +2022-11-24 Wilco Dijkstra <wilco.dijkstra@arm.com> + + PR tree-optimization/107413 + * config/aarch64/aarch64.cc (struct tune_params): Add + fma_reassoc_width to all CPU tuning structures. + (aarch64_reassociation_width): Use fma_reassoc_width. + * config/aarch64/aarch64-protos.h (struct tune_params): Add + fma_reassoc_width. + +2022-11-24 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/107317 + * asan.cc: Include diagnostic-core.h. + (asan_emit_stack_protection): Return NULL early if seen_error (). + +2022-11-24 Aldy Hernandez <aldyh@redhat.com> + + * vr-values.cc (simplify_using_ranges::compare_names): Remove. + (vrp_evaluate_conditional_warnv_with_ops): Remove call to + compare_names. + (simplify_using_ranges::vrp_visit_cond_stmt): Remove use_equiv_p + argument to vrp_evaluate_conditional_warnv_with_ops. + * vr-values.h (class simplify_using_ranges): Remove + compare_names. + Remove use_equiv_p to vrp_evaluate_conditional_warnv_with_ops. + +2022-11-24 Aldy Hernandez <aldyh@redhat.com> + + * tree-vrp.cc (overflow_comparison_p_1): Remove follow_assert_exprs. + (overflow_comparison_p): Remove use_equiv_p. + * tree-vrp.h (overflow_comparison_p): Same. + * vr-values.cc (vrp_evaluate_conditional_warnv_with_ops): Remove + use_equiv_p argument to overflow_comparison_p. + +2022-11-24 Aldy Hernandez <aldyh@redhat.com> + + * doc/gimple.texi: Remove ASSERT_EXPR references. + * fold-const.cc (tree_expr_nonzero_warnv_p): Same. + (fold_binary_loc): Same. + (tree_expr_nonnegative_warnv_p): Same. + * gimple-array-bounds.cc (get_base_decl): Same. + * gimple-pretty-print.cc (dump_unary_rhs): Same. + * gimple.cc (get_gimple_rhs_num_ops): Same. + * pointer-query.cc (handle_ssa_name): Same. + * tree-cfg.cc (verify_gimple_assign_single): Same. + * tree-pretty-print.cc (dump_generic_node): Same. + * tree-scalar-evolution.cc (scev_dfs::follow_ssa_edge_expr):Same. + (interpret_rhs_expr): Same. + * tree-ssa-operands.cc (operands_scanner::get_expr_operands): Same. + * tree-ssa-propagate.cc + (substitute_and_fold_dom_walker::before_dom_children): Same. + * tree-ssa-threadedge.cc: Same. + * tree-vrp.cc (overflow_comparison_p): Same. + * tree.def (ASSERT_EXPR): Add note. + * tree.h (ASSERT_EXPR_VAR): Remove. + (ASSERT_EXPR_COND): Remove. + * vr-values.cc (simplify_using_ranges::vrp_visit_cond_stmt): + Remove comment. + +2022-11-24 Aldy Hernandez <aldyh@redhat.com> + + * Makefile.in: Remove value-range-equiv.o + * gimple-array-bounds.cc + (array_bounds_checker::array_bounds_checker): Remove comment. + * tree-vrp.cc (supported_types_p): Remove use of value_range_equiv. + * value-query.cc (class equiv_allocator): Same. + (range_query::allocate_value_range_equiv): Remove. + (range_query::free_value_range_equiv): Remove. + (range_query::get_value_range): Remove. + * value-query.h (class range_query): Remove get_value_range. + Remove allocate_value_range_equiv. + Remove free_value_range_equiv. + * vr-values.cc (compare_ranges): Replace value_range_equiv with + value_range. + (simplify_using_ranges::get_vr_for_comparison): Same. + (simplify_using_ranges::compare_names): Same. + * vr-values.h: Remove value_range_equiv references. + * value-range-equiv.cc: Removed. + * value-range-equiv.h: Removed. + +2022-11-24 Aldy Hernandez <aldyh@redhat.com> + + * doc/invoke.texi: Remove docs for max-vrp-switch-assertions, + vrp1-mode, and vrp2-mode. + * params.opt: Same. + * range-op.cc (masked_increment): Move from tree-vrp.cc. + * tree-vrp.cc (class live_names): Remove. + (live_names::init_bitmap_if_needed): Remove. + (live_names::block_has_live_names_p): Remove. + (live_names::clear_block): Remove. + (live_names::merge): Remove. + (live_names::set): Remove. + (live_names::clear): Remove. + (live_names::live_names): Remove. + (live_names::~live_names): Remove. + (live_names::live_on_block_p): Remove. + (live_names::live_on_edge_p): Remove. + (get_single_symbol): Make static. + (build_symbolic_expr): Remove. + (adjust_symbolic_bound): Remove. + (combine_bound): Remove. + (set_value_range_with_overflow): Remove. + (extract_range_from_pointer_plus_expr): Remove. + (extract_range_from_plus_minus_expr): Remove. + (drop_undefines_to_varying): Remove. + (range_fold_binary_symbolics_p): Remove. + (range_fold_unary_symbolics_p): Remove. + (range_fold_binary_expr): Remove. + (infer_value_range): Remove. + (dump_assert_info): Remove. + (dump_asserts_info): Remove. + (add_assert_info): Remove. + (extract_code_and_val_from_cond_with_ops): Remove. + (masked_increment): Move to range-op.cc. + (register_edge_assert_for_2): Remove. + (find_case_label_index): Remove. + (find_case_label_range): Remove. + (register_edge_assert_for_1): Remove. + (is_masked_range_test): Remove. + (register_edge_assert_for): Remove. + (stmt_interesting_for_vrp): Remove. + (struct case_info): Remove. + (struct assert_locus): Remove. + (class vrp_asserts): Remove. + (vrp_asserts::build_assert_expr_for): Remove. + (vrp_asserts::dump): Remove. + (vrp_asserts::register_new_assert_for): Remove. + (vrp_asserts::finish_register_edge_assert_for): Remove. + (vrp_asserts::find_conditional_asserts): Remove. + (vrp_asserts::compare_case_labels): Remove. + (vrp_asserts::find_switch_asserts): Remove. + (vrp_asserts::find_assert_locations_in_bb): Remove. + (vrp_asserts::find_assert_locations): Remove. + (vrp_asserts::process_assert_insertions_for): Remove. + (vrp_asserts::compare_assert_loc): Remove. + (vrp_asserts::process_assert_insertions): Remove. + (vrp_asserts::insert_range_assertions): Remove. + (vrp_asserts::all_imm_uses_in_stmt_or_feed_cond): Remove. + (vrp_asserts::remove_range_assertions): Remove. + (class vrp_prop): Remove. + (vrp_prop::initialize): Remove. + (enum ssa_prop_result): Remove. + (vrp_prop::visit_stmt): Remove. + (vrp_prop::visit_phi): Remove. + (vrp_prop::finalize): Remove. + (class vrp_folder): Remove. + (vrp_folder::fold_predicate_in): Remove. + (vrp_folder::fold_stmt): Remove. + (vrp_folder::simplify_casted_conds): Remove. + (execute_vrp): Remove. + * tree-vrp.h (struct assert_info): Remove. + (register_edge_assert_for): Remove. + (stmt_interesting_for_vrp): Remove. + (infer_value_range): Remove. + (get_single_symbol): Remove. + (masked_increment): Remove. + (execute_ranger_vrp): Remove. + * vr-values.cc (set_value_range_to_nonnegative): Remove. + (set_value_range_to_truthvalue): Remove. + (vr_values::get_lattice_entry): Remove. + (vr_values::get_value_range): Remove. + (vr_values::range_of_expr): Remove. + (vr_values::value_of_expr): Remove. + (vr_values::value_on_edge): Remove. + (vr_values::value_of_stmt): Remove. + (vr_values::set_def_to_varying): Remove. + (vr_values::set_defs_to_varying): Remove. + (vr_values::update_value_range): Remove. + (symbolic_range_based_on_p): Remove. + (gimple_assign_nonzero_p): Remove. + (gimple_stmt_nonzero_p): Remove. + (vr_values::vrp_stmt_computes_nonzero): Remove. + (vr_values::op_with_constant_singleton_value_range): Remove. + (vr_values::extract_range_for_var_from_comparison_expr): Remove. + (vr_values::extract_range_from_assert): Remove. + (vr_values::extract_range_from_ssa_name): Remove. + (vr_values::extract_range_from_binary_expr): Remove. + (vr_values::extract_range_from_unary_expr): Remove. + (vr_values::extract_range_from_cond_expr): Remove. + (vr_values::extract_range_from_comparison): Remove. + (vr_values::extract_range_from_ubsan_builtin): Remove. + (vr_values::extract_range_basic): Remove. + (vr_values::extract_range_from_assignment): Remove. + (vr_values::adjust_range_with_scev): Remove. + (vr_values::dump): Remove. + (vr_values::vr_values): Remove. + (vr_values::~vr_values): Remove. + (vrp_valueize): Remove. + (vrp_valueize_1): Remove. + (get_output_for_vrp): Remove. + (vr_values::vrp_visit_assignment_or_call): Remove. + (simplify_using_ranges::vrp_evaluate_conditional): Remove. + (vr_values::vrp_visit_switch_stmt): Remove. + (vr_values::extract_range_from_stmt): Remove. + (vr_values::extract_range_from_phi_node): Remove. + (simplify_using_ranges::fold_cond): Add FIXME note. + (vr_values::set_vr_value): Remove. + (vr_values::swap_vr_value): Remove. + * vr-values.h (class vr_values): Remove. + (get_output_for_vrp): Remove. + +2022-11-24 Hongyu Wang <hongyu.wang@intel.com> + + PR target/107692 + * common/config/i386/i386-common.cc (ix86_optimization_table): + Enable loop unroll O2, disable -fweb and -frename-registers + by default. + * config/i386/i386-options.cc + (ix86_override_options_after_change): + Disable small loop unroll when funroll-loops enabled, reset + cunroll_grow_size when it is not explicitly enabled. + (ix86_option_override_internal): Call + ix86_override_options_after_change instead of calling + ix86_recompute_optlev_based_flags and ix86_default_align + separately. + * config/i386/i386.cc (ix86_loop_unroll_adjust): Adjust unroll + factor if -munroll-only-small-loops enabled. + * loop-init.cc (pass_rtl_unroll_loops::gate): Do not enable + loop unrolling for -O2-speed. + (pass_rtl_unroll_loops::execute): Rmove + targetm.loop_unroll_adjust check. + +2022-11-23 Ramana Radhakrishnan <ramana.gcc@gmail.com> + + * config/arm/types.md: Update comment. + (is_neon_type): Add neon_fcmla, neon_fcadd. + +2022-11-23 Jonathan Wakely <jwakely@redhat.com> + + * doc/invoke.texi (C++ Dialect Options): Recommend using + -Wdelete-non-virtual-dtor instead of -Wnon-virtual-dtor. + +2022-11-23 Jakub Jelinek <jakub@redhat.com> + + PR bootstrap/107722 + * diagnostic.cc (test_diagnostic_get_location_text): Test + special_fname_builtin () rather than "<built-in>" and expect + special_fname_builtin () concatenated with ":" for it. + +2022-11-23 Martin Liska <mliska@suse.cz> + + * Makefile.in: Set DO_LINK_MUTEX. + +2022-11-23 Lulu Cheng <chenglulu@loongson.cn> + xujiahao <xujiahao@loongson.cn> + + * config/loongarch/constraints.md (ZD): New constraint. + * config/loongarch/loongarch-def.c: Initial number of parallel prefetch. + * config/loongarch/loongarch-tune.h (struct loongarch_cache): + Define number of parallel prefetch. + * config/loongarch/loongarch.cc (loongarch_option_override_internal): + Set up parameters to be used in prefetching algorithm. + * config/loongarch/loongarch.md (prefetch): New template. + +2022-11-23 Marek Polacek <polacek@redhat.com> + + Revert: + 2022-11-23 Marek Polacek <polacek@redhat.com> + + * Makefile.in: Set LD_PICFLAG. Use it. Set enable_host_pie. + Remove NO_PIE_CFLAGS and NO_PIE_FLAG. Pass LD_PICFLAG to + ALL_LINKERFLAGS. Use the "pic" build of libiberty if --enable-host-pie. + * configure.ac (--enable-host-shared): Don't set PICFLAG here. + (--enable-host-pie): New check. Set PICFLAG and LD_PICFLAG after this + check. + * configure: Regenerate. + * doc/install.texi: Document --enable-host-pie. + +2022-11-23 Marek Polacek <polacek@redhat.com> + + Revert: + 2022-11-23 Marek Polacek <polacek@redhat.com> + + * configure.ac (--enable-host-bind-now): New check. Add + -Wl,-z,now to LD_PICFLAG if --enable-host-bind-now. + * configure: Regenerate. + * doc/install.texi: Document --enable-host-bind-now. + +2022-11-23 Marek Polacek <polacek@redhat.com> + + * configure.ac (--enable-host-bind-now): New check. Add + -Wl,-z,now to LD_PICFLAG if --enable-host-bind-now. + * configure: Regenerate. + * doc/install.texi: Document --enable-host-bind-now. + +2022-11-23 Marek Polacek <polacek@redhat.com> + + * Makefile.in: Set LD_PICFLAG. Use it. Set enable_host_pie. + Remove NO_PIE_CFLAGS and NO_PIE_FLAG. Pass LD_PICFLAG to + ALL_LINKERFLAGS. Use the "pic" build of libiberty if --enable-host-pie. + * configure.ac (--enable-host-shared): Don't set PICFLAG here. + (--enable-host-pie): New check. Set PICFLAG and LD_PICFLAG after this + check. + * configure: Regenerate. + * doc/install.texi: Document --enable-host-pie. + +2022-11-22 Jeff Law <jlaw@ventanamicro.com> + + * tree-ssa-dom.cc (record_edge_info): Fix thinko in last commit. + +2022-11-22 Jeff Law <jlaw@ventanamicro.com> + + * tree-ssa-dom.cc (record_edge_info): Fix comment typos. + +2022-11-22 Jeff Law <jeffreyalaw@gmail.com> + + * config/riscv/riscv.cc (riscv_get_separate_components): Do not + do shrink-wrapping for a frame with a variable size. + +2022-11-22 Siddhesh Poyarekar <siddhesh@gotplt.org> + + * tree-object-size.cc (todo): New variable. + (object_sizes_execute): Use it. + (strdup_object_size): New function. + (call_object_size): Use it. + +2022-11-22 Eric Botcazou <ebotcazou@adacore.com> + + * tree-loop-distribution.cc (loop_distribution::classify_builtin_ldst): + Bail out if source and destination do not have the same storage order. + +2022-11-22 Martin Jambor <mjambor@suse.cz> + + * ipa-sra.cc (ipa_sra_dump_all_summaries): Dump edge summaries even + for non-candidates. + +2022-11-22 Martin Jambor <mjambor@suse.cz> + + * ipa-cp.cc (push_agg_values_from_edge): Do not consider constants + in unused aggregate parameters. + +2022-11-22 Martin Jambor <mjambor@suse.cz> + + * ipa-param-manipulation.h (ipa_param_body_adjustments): Removed + member m_split_modifications_p. + * ipa-param-manipulation.cc + (ipa_param_body_adjustments::common_initialization): Do not set + m_split_modifications_p. + (ipa_param_body_adjustments::ipa_param_body_adjustments): Remove + initializations of m_split_modifications_p. + (ipa_param_body_adjustments::modify_call_stmt): Check that + m_replacements is empty instead of m_split_modifications_p. + +2022-11-22 Martin Jambor <mjambor@suse.cz> + + PR ipa/107661 + * ipa-cp.cc (push_agg_values_from_edge): New parameter + optimize_self_recursion, use it to decide whether to pass interim to + the helper function. + (find_aggregate_values_for_callers_subset): Pass true in the new + parameter of push_agg_values_from_edge. + (cgraph_edge_brings_all_agg_vals_for_node): Pass false in the new + parameter of push_agg_values_from_edge. + +2022-11-22 Tobias Burnus <tobias@codesourcery.com> + Andrew Stubbs <ams@codesourcery.com> + + * config/gcn/gcn-builtins.def (FIRST_CALL_THIS_THREAD_P, + GET_STACK_LIMIT): Add new builtins. + * config/gcn/gcn.cc (gcn_expand_builtin_1): Expand them. + * config/gcn/gcn.md (prologue_use): Add "register_operand" as + arg to match_operand. + (prologue_use_di): New; DI insn_and_split variant of the former. + +2022-11-22 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107803 + * tree-ssa-propagate.cc (substitute_and_fold_dom_walker): Add + need_ab_cleanup member. + (substitute_and_fold_dom_walker::before_dom_children): When + a stmt can no longer transfer control flow abnormally set + need_ab_cleanup. + (substitute_and_fold_engine::substitute_and_fold): Cleanup + abnormal control flow. + +2022-11-22 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107672 + * tree-vect-stmts.cc (supportable_widening_operation): Avoid + type_for_mode on vector modes. + +2022-11-22 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107766 + * tree-vect-slp-patterns.cc (complex_mul_pattern::matches): + Use *node to check for FP vector types. + +2022-11-22 liuhongt <hongtao.liu@intel.com> + + * config/i386/mmx.md (*mov<mode>_internal): Add + ix86_hard_reg_move_ok to condition. + +2022-11-22 liuhongt <hongtao.liu@intel.com> + + * config/i386/i386.cc (ix86_can_change_mode_class): Also guard + size of TO. + (ix86_hard_regno_mode_ok): Remove VALID_AVX512FP16_SCALAR_MODE + * config/i386/i386.h (VALID_AVX512FP16_SCALAR_MODE): Merged to + .. + (VALID_AVX512F_SCALAR_MODE): .. this, also add HImode. + (VALID_SSE_REG_MODE): Add DI/HImode. + +2022-11-21 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * config/rtems.h (SUBTARGET_CC1_SPEC): Undef and define. + +2022-11-21 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * gcc.cc (SUBTARGET_CC1_SPEC): Define if not defined. + (cc1_spec): Append SUBTARGET_CC1_SPEC. + +2022-11-21 Dimitar Dimitrov <dimitar@dinux.eu> + + * doc/sourcebuild.texi (sockets): Document new check. + +2022-11-21 Andrew Carlotti <andrew.carlotti@arm.com> + + * tree-ssa-loop.h (tree_niter_desc): Update comment. + +2022-11-21 Andrew Carlotti <andrew.carlotti@arm.com> + + * tree-ssa-loop-niter.cc + (number_of_iterations_exit_assumptions): Modify to call... + (number_of_iterations_bitcount): ...this new function. + (number_of_iterations_popcount): Now called by the above. + Refactor, and extract popcount expression builder to... + (build_popcount_expr): this new function. + +2022-11-21 Andrew Carlotti <andrew.carlotti@arm.com> + + * tree-ssa-loop-niter.cc (ssa_defined_by_minus_one_stmt_p): Move + (number_of_iterations_popcount): Move, and remove separate prototype. + +2022-11-21 Andrew Carlotti <andrew.carlotti@arm.com> + + * tree-ssa-loop-niter.cc (number_of_iterations_exit_assumptions): + Move at_stmt assignment. + +2022-11-21 Christophe Lyon <christophe.lyon@arm.com> + + * genmultilib: Fix options and dirnames/osdirnames sanity check. + +2022-11-21 Philipp Tomsich <philipp.tomsich@vrull.eu> + + PR target/107786 + * config/riscv/riscv.md + (*branch<ANYI:mode>_shiftedarith_equals_zero): Wrap ANYI + in a subreg, as our branch instructions only supports X. + +2022-11-21 Jakub Jelinek <jakub@redhat.com> + + PR target/107748 + * config/i386/avx512fp16intrin.h (_mm512_castph512_ph128, + _mm512_castph512_ph256, _mm512_castph128_ph512, + _mm512_castph256_ph512, _mm512_set1_pch): Uglify names of local + variables and union members. + * config/i386/avx512fp16vlintrin.h (_mm256_castph256_ph128, + _mm256_castph128_ph256, _mm256_set1_pch, _mm_set1_pch): Likewise. + * config/i386/smmintrin.h (_mm_extract_ps): Likewise. + +2022-11-21 Christophe Lyon <christophe.lyon@arm.com> + + * genmultilib: Add sanity check. + +2022-11-21 Eric Botcazou <ebotcazou@adacore.com> + + * config/arm/arm.cc (arm_attribute_table) <cmse_nonsecure_call>: + Change decl_required field to false. + (arm_handle_cmse_nonsecure_call): Deal with a TYPE node. + +2022-11-21 Andrew Pinski <apinski@marvell.com> + + * gimplify.cc (gimplify_modify_expr): If + either *from_p or *to_p were error_operand + return early. + +2022-11-21 liuhongt <hongtao.liu@intel.com> + + * config/i386/i386-builtins.cc (def_builtin): Handle "shared" + avx512bf16vl-avxneconvert builtins. + +2022-11-20 Jakub Jelinek <jakub@redhat.com> + + PR target/107183 + * reg-stack.cc (next_flags_user): Add DEBUG_SEEN argument. + If >= 0 and a DEBUG_INSN would be otherwise returned, set + DEBUG_SEEN to 1 and ignore it. + (swap_rtx_condition): Add DEBUG_SEEN argument. In >= 0 + mode only set DEBUG_SEEN to 1 if problematic DEBUG_ISNSs + were seen and revert all changes on success in that case. + Don't try to recog_memoized DEBUG_INSNs. + (compare_for_stack_reg): Adjust swap_rtx_condition caller. + If it returns true and debug_seen is 1, call swap_rtx_condition + again with debug_seen -1. + +2022-11-20 Jeff Law <jlaw@ventanamicro.com> + + PR other/104044 + * config/mn10300/mn10300.cc (mn10300_print_operand): Remove + extraneous semicolon. + * config/nvptx/nvptx.cc (nvptx_goacc_reduction_fini): Likewise. + +2022-11-19 Andrew Pinski <apinski@marvell.com> + + PR middle-end/14840 + * tree-core.h (tree_code_type): Constexprify + by including all-tree.def. + (tree_code_length): Likewise. + * tree.cc (tree_code_type): Remove. + (tree_code_length): Remove. + +2022-11-19 Thomas Schwinge <thomas@codesourcery.com> + + * config/nvptx/nvptx.h (STARTFILE_SPEC): Fix 'crt0.o' for + '-mmainkernel'. + +2022-11-19 Jonathan Wakely <jwakely@redhat.com> + LIU Hao <lh_mouse@126.com> + + * system.h [INCLUDE_MUTEX]: Include header for std::mutex. + +2022-11-19 Jakub Jelinek <jakub@redhat.com> + + PR target/107628 + * config/i386/i386-protos.h (ix86_expand_fast_convert_bf_to_sf): + Declare. + * config/i386/i386-expand.cc (ix86_expand_fast_convert_bf_to_sf): New + function. + * config/i386/i386.md (cbranchbf4, cstorebf4): Use it. + +2022-11-19 Jeff Chapman II <jchapman@lock3software.com> + Andrew Sutton <asutton@lock3software.com> + Andrew Marmaduke <amarmaduke@lock3software.com> + Michael Lopez <mlopez@lock3software.com> + Jason Merrill <jason@redhat.com> + + * doc/invoke.texi: Document contracts flags. + +2022-11-18 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/bitmanip.md (*minmax): Additional pattern for + min/max against constants that are extension-invariant. + * config/riscv/iterators.md (minmax_optab): Add an iterator + that has only min and max rtl. + +2022-11-18 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/bitmanip.md + (*branch<X:mode>_mask_twobits_equals_singlebit): + Handle "if ((a & T) == C)" using Zbs, when T has 2 bits set and C + has one of these tow bits set. + * config/riscv/predicates.md (const_twobits_not_arith_operand): + New predicate. + +2022-11-18 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/bitmanip.md (*<or_optab>i<mode>_extrabit): + New pattern for binvi+binvi/xori and bseti+bseti/ori + (*andi<mode>_extrabit): New pattern for bclri+bclri/andi + * config/riscv/iterators.md (any_or): Match or and ior + * config/riscv/predicates.md (const_twobits_operand): + New predicate. + (uimm_extra_bit_operand): New predicate. + (uimm_extra_bit_or_twobits): New predicate. + (not_uimm_extra_bit_operand): New predicate. + (not_uimm_extra_bit_or_nottwobits): New predicate. + * config/riscv/riscv.h (UIMM_EXTRA_BIT_OPERAND): + Helper for the uimm_extra_bit_operand and + not_uimm_extra_bit_operand predicates. + +2022-11-18 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/bitmanip.md: Handle corner-cases for combine + when chaining slli(.uw)? + addw + * config/riscv/riscv-protos.h (riscv_shamt_matches_mask_p): + Define prototype. + * config/riscv/riscv.cc (riscv_shamt_matches_mask_p): + Helper for evaluating the relationship between two operands. + +2022-11-18 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/bitmanip.md: Add a define_split to optimize + slliw + addiw + divw into sh[123]add + divw. + +2022-11-18 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/predicates.md (shifted_const_arith_operand): New predicate. + (uimm_extra_bit_operand): New predicate. + * config/riscv/riscv.md (*branch<ANYI:mode>_shiftedarith_equals_zero): + New pattern. + (*branch<ANYI:mode>_shiftedmask_equals_zero): New pattern. + +2022-11-18 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/bitmanip.md (*bsetidisi): New pattern. + +2022-11-18 Richard Purdie <richard.purdie@linuxfoundation.org> + + * doc/invoke.texi: Document prefix-maps don't affect directives. + +2022-11-18 Andrew Pinski <apinski@marvell.com> + + PR middle-end/107705 + * function.cc (aggregate_value_p): Return 0 if + the function type was an error operand. + +2022-11-18 Andrew Pinski <apinski@marvell.com> + + PR c/106764 + PR c/106765 + PR c/107307 + * gimplify.cc (gimplify_compound_lval): Return GS_ERROR + if gimplify_expr had return GS_ERROR. + (gimplify_call_expr): Likewise. + +2022-11-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/atomics.md (*aarch64_atomic_load<ALLX:mode>_rcpc_sext): + Use <GPI:w> for destination format. + * config/aarch64/iterators.md (w_sz): Delete. + +2022-11-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/aarch64.h (TARGET_RCPC2): Define. + * config/aarch64/atomics.md (*aarch64_atomic_load<ALLX:mode>_rcpc_zext): + Adjust output template. + (*aarch64_atomic_load<ALLX:mode>_rcpc_sex): Guard on TARGET_RCPC2. + Adjust output template. + * config/aarch64/iterators.md (w_sz): New mode attr. + +2022-11-18 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107647 + * tree-vect-slp-patterns.cc (addsub_pattern::recognize): Only + allow FMA generation with -ffp-contract=fast for FP types. + (complex_mul_pattern::matches): Likewise. + +2022-11-18 Jinyang He <hejinyang@loongson.cn> + + PR target/107713 + * config/loongarch/sync.md + (atomic_cas_value_exchange_7_<mode>): New define_insn. + (atomic_exchange): Use atomic_cas_value_exchange_7_si instead of + atomic_cas_value_cmp_and_7_si. + +2022-11-17 Andrew Pinski <apinski@marvell.com> + + PR middle-end/107734 + * match.pd (perm + vector op pattern): Clear the sbitmap before + use. + +2022-11-17 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/107732 + * range-op-float.cc (foperator_abs::op1_range): Early exit when + result is undefined. + +2022-11-17 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/bitmanip.md (*bclri<mode>_nottwobits): New pattern. + (*bclridisi_nottwobits): New pattern, handling the sign-bit. + * config/riscv/predicates.md (const_nottwobits_operand): + New predicate. + +2022-11-17 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/bitmanip.md: Add a splitter to generate + polarity-reversed masks from a set bit using bexti + addi. + +2022-11-17 mtsamis <manolis.tsamis@vrull.eu> + + * config/riscv/riscv.cc (struct machine_function): Add array to store + register wrapping information. + (riscv_for_each_saved_reg): Skip registers that are wrapped separetely. + (riscv_get_separate_components): New function. + (riscv_components_for_bb): Likewise. + (riscv_disqualify_components): Likewise. + (riscv_process_components): Likewise. + (riscv_emit_prologue_components): Likewise. + (riscv_emit_epilogue_components): Likewise. + (riscv_set_handled_components): Likewise. + (TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS): Define. + (TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB): Likewise. + (TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS): Likewise. + (TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS): Likewise. + (TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS): Likewise. + (TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS): Likewise. + +2022-11-17 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/atomics.md (*aarch64_atomic_load<ALLX:mode>_rcpc_zext): + Add mode size check to condition. + (*aarch64_atomic_load<ALLX:mode>_rcpc_sext): Likewise. + +2022-11-17 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/68097 + * gimple-fold.cc (gimple_stmt_nonnegative_warnv_p): Call + range_of_stmt for floats. + +2022-11-17 Lili Cui <lili.cui@intel.com> + + * config/i386/x86-tune.def + (X86_TUNE_AVX256_MOVE_BY_PIECES): Add alderlake. + (X86_TUNE_AVX256_STORE_BY_PIECES): Ditto. + +2022-11-17 Tamar Christina <tamar.christina@arm.com> + + PR tree-optimization/107717 + * match.pd: Ensure same SSA_NAME. + +2022-11-17 Tamar Christina <tamar.christina@arm.com> + + * match.pd: Replace GET_MODE_WIDER_MODE with + custom code. + +2022-11-17 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (range_operator_float::fold_range): Make check + for maybe_isnan more readable. + +2022-11-17 Kewen Lin <linkw@linux.ibm.com> + + * gimple-fold.cc (gimple_fold_partial_load_store_mem_ref): Use + tree_fits_shwi_p rather than tree_fits_uhwi_p as bias is signed. + +2022-11-17 Jia-Wei Chen <jiawei@iscas.ac.cn> + + * config/riscv/riscv.cc (riscv_expand_epilogue): + Do not emit useless add sp, sp, 0 instrutions. + +2022-11-17 Jeff Law <jlaw@ventanamicro.com> + + * config/sh/sh_treg_combine.cc: Include tm-preds.h. + (t_reg_operand): Remove bogus prototype. + (negt_reg_operand): Likewise. + +2022-11-16 Marek Polacek <polacek@redhat.com> + + PR c++/106649 + * doc/invoke.texi: Document -Winvalid-constexpr. + +2022-11-16 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/bitmanip.md: Add split covering + "(a & (1 << BIT_NO)) ? 0 : 1". + +2022-11-16 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/bitmanip.md (*bext<mode>): Add an additional + pattern that allows the 3rd argument to zero_extract to be + an Xmode register operand. + +2022-11-16 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107686 + * tree-ssa-forwprop.cc (optimize_vector_load): Restrict + VEC_UNPACK support to integral typed bitfield refs. + +2022-11-16 Richard Biener <rguenther@suse.de> + + PR middle-end/107679 + * tree-into-ssa.cc (maybe_register_def): Use new temporary if + we require an uninitialized value for a parameter decl. + +2022-11-16 Alexander Monakov <amonakov@ispras.ru> + + PR target/107676 + * doc/invoke.texi (-mrelax-cmpxchg-loop): Reword description. + +2022-11-16 Alexander Monakov <amonakov@ispras.ru> + + PR target/87832 + * config/i386/znver.md: (znver1_fp_op_mul): Correct cycles in + the reservation. + (znver1_fp_op_mul_load): Ditto. + (znver1_mmx_mul): Ditto. + (znver1_mmx_load): Ditto. + (znver1_ssemul_ss_ps): Ditto. + (znver1_ssemul_ss_ps_load): Ditto. + (znver1_ssemul_avx256_ps): Ditto. + (znver1_ssemul_avx256_ps_load): Ditto. + (znver1_ssemul_sd_pd): Ditto. + (znver1_ssemul_sd_pd_load): Ditto. + (znver2_ssemul_sd_pd): Ditto. + (znver2_ssemul_sd_pd_load): Ditto. + (znver1_ssemul_avx256_pd): Ditto. + (znver1_ssemul_avx256_pd_load): Ditto. + (znver1_sseimul): Ditto. + (znver1_sseimul_avx256): Ditto. + (znver1_sseimul_load): Ditto. + (znver1_sseimul_avx256_load): Ditto. + (znver1_sseimul_di): Ditto. + (znver1_sseimul_load_di): Ditto. + +2022-11-16 Alexander Monakov <amonakov@ispras.ru> + + PR target/87832 + * config/i386/znver.md (znver1_fdiv): New automaton. + (znver1-fdiv): New unit. + (znver1_fp_op_div): Correct unit and cycles in the reservation. + (znver1_fp_op_div_load): Ditto. + (znver1_fp_op_idiv_load): Ditto. + (znver2_fp_op_idiv_load): Ditto. + (znver1_ssediv_ss_ps): Ditto. + (znver1_ssediv_ss_ps_load): Ditto. + (znver1_ssediv_sd_pd): Ditto. + (znver1_ssediv_sd_pd_load): Ditto. + (znver1_ssediv_avx256_ps): Ditto. + (znver1_ssediv_avx256_ps_load): Ditto. + (znver1_ssediv_avx256_pd): Ditto. + (znver1_ssediv_avx256_pd_load): Ditto. + +2022-11-16 Tobias Burnus <tobias@codesourcery.com> + Andrew Stubbs <ams@codesourcery.com> + + * config/gcn/gcn-builtins.def (KERNARG_PTR): Add. + * config/gcn/gcn.cc (gcn_init_builtin_types): Change siptr_type_node, + sfptr_type_node and voidptr_type_node from FLAT to ADDR_SPACE_DEFAULT. + (gcn_expand_builtin_1): Handle GCN_BUILTIN_KERNARG_PTR. + (gcn_oacc_dim_size): Return in ADDR_SPACE_FLAT. + +2022-11-16 David Malcolm <dmalcolm@redhat.com> + + * Makefile.in (ANALYZER_OBJS): Add analyzer/checker-event.o. + +2022-11-16 Max Filippov <jcmvbkbc@gmail.com> + + PR target/107645 + * config/m68k/predicates.md (symbolic_operand): Return false + when UNSPEC is under the CONST node. + +2022-11-16 Christoph Müllner <christoph.muellner@vrull.eu> + + * doc/invoke.texi: Fix PRU/RISC-V option list formatting. + +2022-11-16 Tobias Burnus <tobias@codesourcery.com> + + * config/nvptx/mkoffload.cc (process): Recognize '$nohost$...' + besides tailing '$nohost' as being for reverse offload. + +2022-11-16 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/107668 + * range-op-float.cc (float_binary_op_range_finish): Set VARYING + also when r is UNDEFINED. + +2022-11-16 Kewen Lin <linkw@linux.ibm.com> + + PR rtl-optimization/90259 + * function.cc (rest_of_handle_thread_prologue_and_epilogue): Add + parameter fun, and call function purge_all_dead_edges. + (pass_thread_prologue_and_epilogue::execute): Name unamed parameter + as fun, and use it for rest_of_handle_thread_prologue_and_epilogue. + +2022-11-15 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/riscv-builtins.cc (struct riscv_builtin_description): + add the pause machine-dependent builtin with no result and no + arguments; mark it as always present (pause is a true hint + that encodes into a fence-insn, if not supported with the new + pause semantics). + * config/riscv/riscv-ftypes.def: Add type for void -> void. + * config/riscv/riscv.md (riscv_pause): Add risc_pause and + UNSPECV_PAUSE + * doc/extend.texi: Document __builtin_riscv_pause. + * optabs.cc (maybe_gen_insn): Allow nops == 0 (void -> void). + +2022-11-15 David Faust <david.faust@oracle.com> + + * config/bpf/bpf.cc (bpf_expand_builtin): Avoid use of uninitialized + variable in error case. + +2022-11-15 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/106140 + * doc/invoke.texi (Static Analyzer Options): Add + -Wanalyzer-fd-phase-mismatch and -Wanalyzer-fd-type-mismatch. Add + "socket", "bind", "listen", "accept", and "connect" to the list of + functions known to the analyzer. + +2022-11-15 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/106302 + * Makefile.in (ANALYZER_OBJS): Add analyzer/analyzer-language.o. + (GTFILES): Add analyzer/analyzer-language.cc. + * doc/analyzer.texi: Document __analyzer_dump_named_constant. + +2022-11-15 Lewis Hyatt <lhyatt@gmail.com> + + * json.h (class string): Add M_LEN member to store the length of + the data. Add constructor taking an explicit length. + * json.cc (string::string): Implement the new constructor. + (string::print): Support printing strings that are not + null-terminated. Escape embdedded null bytes on output. + (test_writing_strings): Test the new null-byte-related features of + json::string. + +2022-11-15 Lewis Hyatt <lhyatt@gmail.com> + + * diagnostic.cc (diagnostic_get_location_text): Use + special_fname_builtin () rather than a hardcoded string (which was + also incorrectly left untranslated previously.) + * input.cc (special_fname_builtin): New function. + (expand_location_1): Use special_fname_builtin () rather than a + hard-coded string. + (test_builtins): Likewise. + * input.h (special_fname_builtin): Declare. + +2022-11-15 Lewis Hyatt <lhyatt@gmail.com> + + * tree-diagnostic.cc (maybe_unwind_expanded_macro_loc): Handle ad-hoc + location in return value of linemap_resolve_location(). + +2022-11-15 Jonathan Wakely <jwakely@redhat.com> + + * doc/cpp.texi (Pragmas): Use @item and @itemx for region + pragmas. + +2022-11-15 Maciej W. Rozycki <macro@embecosm.com> + + * ira-color.cc (assign_hard_reg): Remove duplicate `memset' over + `full_costs'. + +2022-11-15 Andre Vieira <andre.simoesdiasvieira@arm.com> + + * config/aarch64/atomics.md + (*aarch64_atomic_load<ALLX:mode>_rcpc_zext): New pattern. + (*aarch64_atomic_load<ALLX:mode>_rcpc_sext): New pattern. + +2022-11-15 Andre Vieira <andre.simoesdiasvieira@arm.com> + Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/aarch64.h (AARCH64_ISA_RCPC): New Macro. + (TARGET_RCPC): New Macro. + * config/aarch64/atomics.md (atomic_load<mode>): Change into an expand. + (aarch64_atomic_load<mode>_rcpc): New define_insn for ldapr. + (aarch64_atomic_load<mode>): Rename of old define_insn for ldar. + * config/aarch64/iterators.md (UNSPEC_LDAP): New unspec enum value. + * doc/invoke.texi (rcpc): Ammend documentation to mention the effects + on code generation. + +2022-11-15 Hongyu Wang <hongyu.wang@intel.com> + + PR target/98167 + * match.pd: New perm + vector op patterns for int and fp vector. + +2022-11-15 Andrew Pinski <apinski@marvell.com> + + * doc/invoke.texi: Remove Score option section. + +2022-11-15 Andrew Pinski <apinski@marvell.com> + + * doc/extend.texi: Remove picoChip builtin section. + * doc/invoke.texi: Remove picoChip option section. + +2022-11-15 Andrew Pinski <apinski@marvell.com> + + * doc/extend.texi: Remove MeP documentation. + * doc/invoke.texi: Remove MeP Options documentation. + +2022-11-15 Andrew Pinski <apinski@marvell.com> + + * doc/invoke.texi: Fix opindex for mcall-aixdesc and mcall-openbsd. + +2022-11-14 Philipp Tomsich <philipp.tomsich@vrull.eu> + + Revert: + 2022-11-14 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/riscv-cores.def (RISCV_TUNE): Add ventana-vt1. + (RISCV_CORE): Ditto. + * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Ditto. + * config/riscv/riscv.cc: Add tune_info for ventana-vt1. + * doc/invoke.texi: Document -mcpu= and -mtune with ventana-vt1. + +2022-11-14 Philipp Tomsich <philipp.tomsich@vrull.eu> + + Revert: + 2022-11-14 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/riscv.cc (enum riscv_fusion_pairs): Add symbolic + constants to identify supported fusion patterns. + (struct riscv_tune_param): Add fusible_op field. + (riscv_macro_fusion_p): Implement. + (riscv_fusion_enabled_p): Implement. + (riscv_macro_fusion_pair_p): Implement and recognize fusible + idioms for Ventana VT1. + (TARGET_SCHED_MACRO_FUSION_P): Point to riscv_macro_fusion_p. + (TARGET_SCHED_MACRO_FUSION_PAIR_P): Point to + riscv_macro_fusion_pair_p. + +2022-11-14 Maciej W. Rozycki <macro@embecosm.com> + + * ira-build.cc (create_insn_allocnos): Fix documentation. + +2022-11-14 Tamar Christina <tamar.christina@arm.com> + + * match.pd: Remove returns. + +2022-11-14 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/bitmanip.md (orcb<mode>2): Add orc.b as an + unspec. + * config/riscv/riscv.md: Add UNSPEC_ORC_B. + +2022-11-14 Tamar Christina <tamar.christina@arm.com> + + * target.def: Fix typo. + +2022-11-14 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/riscv.cc (enum riscv_fusion_pairs): Add symbolic + constants to identify supported fusion patterns. + (struct riscv_tune_param): Add fusible_op field. + (riscv_macro_fusion_p): Implement. + (riscv_fusion_enabled_p): Implement. + (riscv_macro_fusion_pair_p): Implement and recognize fusible + idioms for Ventana VT1. + (TARGET_SCHED_MACRO_FUSION_P): Point to riscv_macro_fusion_p. + (TARGET_SCHED_MACRO_FUSION_PAIR_P): Point to + riscv_macro_fusion_pair_p. + +2022-11-14 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/riscv-cores.def (RISCV_TUNE): Add ventana-vt1. + (RISCV_CORE): Ditto. + * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Ditto. + * config/riscv/riscv.cc: Add tune_info for ventana-vt1. + * doc/invoke.texi: Document -mcpu= and -mtune with ventana-vt1. + +2022-11-14 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/aarch64-option-extensions.def (cssc): Define. + * config/aarch64/aarch64.h (AARCH64_ISA_CSSC): Define. + (TARGET_CSSC): Likewise. + * config/aarch64/aarch64.md (*aarch64_abs<mode>2_cssc_ins): New define_insn. + (abs<mode>2): Adjust for the above. + (aarch64_umax<mode>3_insn): New define_insn. + (umax<mode>3): Adjust for the above. + (*aarch64_popcount<mode>2_cssc_insn): New define_insn. + (popcount<mode>2): Adjust for the above. + (<optab><mode>3): New define_insn. + * config/aarch64/constraints.md (Usm): Define. + (Uum): Likewise. + * doc/invoke.texi (AArch64 options): Document +cssc. + * config/aarch64/iterators.md (MAXMIN_NOUMAX): New code iterator. + * config/aarch64/predicates.md (aarch64_sminmax_immediate): Define. + (aarch64_sminmax_operand): Likewise. + (aarch64_uminmax_immediate): Likewise. + (aarch64_uminmax_operand): Likewise. + +2022-11-14 Tamar Christina <tamar.christina@arm.com> + + * config/aarch64/aarch64-sve2.md (@aarch64_bitmask_udiv<mode>3): New. + +2022-11-14 Tamar Christina <tamar.christina@arm.com> + + * config/aarch64/aarch64-simd.md (@aarch64_bitmask_udiv<mode>3): New. + * config/aarch64/aarch64.cc (aarch64_vectorize_can_special_div_by_constant): New. + +2022-11-14 Tamar Christina <tamar.christina@arm.com> + + * expmed.h (expand_divmod): Pass tree operands down in addition to RTX. + * expmed.cc (expand_divmod): Likewise. + * explow.cc (round_push, align_dynamic_address): Likewise. + * expr.cc (force_operand, expand_expr_divmod): Likewise. + * optabs.cc (expand_doubleword_mod, expand_doubleword_divmod): + Likewise. + * target.h: Include tree-core. + * target.def (can_special_div_by_const): New. + * targhooks.cc (default_can_special_div_by_const): New. + * targhooks.h (default_can_special_div_by_const): New. + * tree-vect-generic.cc (expand_vector_operation): Use it. + * doc/tm.texi.in: Document it. + * doc/tm.texi: Regenerate. + * tree-vect-patterns.cc (vect_recog_divmod_pattern): Check for support. + * tree-vect-stmts.cc (vectorizable_operation): Likewise. + +2022-11-14 Tamar Christina <tamar.christina@arm.com> + + * generic-match-head.cc: Include langooks. + * gimple-match-head.cc: Likewise. + * match.pd: Add fneg/fadd rule. + +2022-11-14 Srinath Parvathaneni <srinath.parvathaneni@arm.com> + + * config/arm/arm-cpus.in (cortex-x1c): Define new CPU. + * config/arm/arm-tables.opt: Regenerate. + * config/arm/arm-tune.md: Likewise. + * doc/invoke.texi: Document Cortex-X1C CPU. + +2022-11-14 Srinath Parvathaneni <srinath.parvathaneni@arm.com> + + * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-X3 + CPU. + * config/aarch64/aarch64-tune.md: Regenerate. + * doc/invoke.texi: Document Cortex-X3 CPU. + +2022-11-14 Andrew Pinski <apinski@marvell.com> + + * doc/invoke.texi: Fix @opindex + for m80387 option. + +2022-11-14 Andrew Pinski <apinski@marvell.com> + + * doc/invoke.texi: Remove the front - from + some @opindex. + +2022-11-14 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add ampere1a. + * config/aarch64/aarch64-cost-tables.h: Add ampere1a_extra_costs. + * config/aarch64/aarch64-fusion-pairs.def (AARCH64_FUSION_PAIR): + Define a new fusion pair for A+B+1/A-B-1 (i.e., add/subtract two + registers and then +1/-1). + * config/aarch64/aarch64-tune.md: Regenerate. + * config/aarch64/aarch64.cc (aarch_macro_fusion_pair_p): Implement + idiom-matcher for the new fusion pair. + * doc/invoke.texi: Add ampere1a. + +2022-11-14 Richard Biener <rguenther@suse.de> + + * match.pd: Remove duplicates. + +2022-11-14 Martin Liska <mliska@suse.cz> + + * doc/contrib.texi: Port from Sphinx. + * doc/cpp.texi: Likewise. + * doc/install.texi: Likewise. + * doc/invoke.texi: Likewise. + +2022-11-14 Martin Liska <mliska@suse.cz> + + Revert: + 2022-11-14 Martin Liska <mliska@suse.cz> + + * doc/cpp/character-sets.rst: New file. + * doc/cpp/conditional-syntax.rst: New file. + * doc/cpp/conditional-uses.rst: New file. + * doc/cpp/conditionals.rst: New file. + * doc/cpp/conf.py: New file. + * doc/cpp/copyright.rst: New file. + * doc/cpp/deleted-code.rst: New file. + * doc/cpp/diagnostics.rst: New file. + * doc/cpp/environment-variables.rst: New file. + * doc/cpp/gnu-free-documentation-license.rst: New file. + * doc/cpp/header-files.rst: New file. + * doc/cpp/header-files/alternatives-to-wrapper-ifndef.rst: New file. + * doc/cpp/header-files/computed-includes.rst: New file. + * doc/cpp/header-files/include-operation.rst: New file. + * doc/cpp/header-files/include-syntax.rst: New file. + * doc/cpp/header-files/once-only-headers.rst: New file. + * doc/cpp/header-files/search-path.rst: New file. + * doc/cpp/header-files/system-headers.rst: New file. + * doc/cpp/header-files/wrapper-headers.rst: New file. + * doc/cpp/implementation-defined-behavior.rst: New file. + * doc/cpp/implementation-details.rst: New file. + * doc/cpp/implementation-limits.rst: New file. + * doc/cpp/index.rst: New file. + * doc/cpp/indices-and-tables.rst: New file. + * doc/cpp/initial-processing.rst: New file. + * doc/cpp/invocation.rst: New file. + * doc/cpp/line-control.rst: New file. + * doc/cpp/macros.rst: New file. + * doc/cpp/macros/concatenation.rst: New file. + * doc/cpp/macros/directives-within-macro-arguments.rst: New file. + * doc/cpp/macros/function-like-macros.rst: New file. + * doc/cpp/macros/macro-arguments.rst: New file. + * doc/cpp/macros/macro-pitfalls.rst: New file. + * doc/cpp/macros/object-like-macros.rst: New file. + * doc/cpp/macros/predefined-macros.rst: New file. + * doc/cpp/macros/stringizing.rst: New file. + * doc/cpp/macros/undefining-and-redefining-macros.rst: New file. + * doc/cpp/macros/variadic-macros.rst: New file. + * doc/cpp/obsolete-features.rst: New file. + * doc/cpp/other-directives.rst: New file. + * doc/cpp/overview.rst: New file. + * doc/cpp/pragmas.rst: New file. + * doc/cpp/preprocessor-output.rst: New file. + * doc/cpp/the-preprocessing-language.rst: New file. + * doc/cpp/tokenization.rst: New file. + * doc/cpp/traditional-lexical-analysis.rst: New file. + * doc/cpp/traditional-macros.rst: New file. + * doc/cpp/traditional-miscellany.rst: New file. + * doc/cpp/traditional-mode.rst: New file. + * doc/cpp/traditional-warnings.rst: New file. + * doc/cppinternals/conf.py: New file. + * doc/cppinternals/copyright.rst: New file. + * doc/cppinternals/cppinternals.rst: New file. + * doc/cppinternals/cpplib.rst: New file. + * doc/cppinternals/files.rst: New file. + * doc/cppinternals/index.rst: New file. + * doc/cppinternals/indices-and-tables.rst: New file. + * doc/cppinternals/internal-representation-of-macros.rst: New file. + * doc/cppinternals/just-which-line-number-anyway.rst: New file. + * doc/cppinternals/lexing-a-line.rst: New file. + * doc/cppinternals/lexing-a-token.rst: New file. + * doc/cppinternals/looking-for-a-function-like-macros-opening-parenthesis.rst: New file. + * doc/cppinternals/macro-expansion-overview.rst: New file. + * doc/cppinternals/marking-tokens-ineligible-for-future-expansion.rst: New file. + * doc/cppinternals/multiple-include-optimization.rst: New file. + * doc/cppinternals/overview.rst: New file. + * doc/cppinternals/representation-of-line-numbers.rst: New file. + * doc/cppinternals/scanning-the-replacement-list-for-macros-to-expand.rst: New file. + * doc/gcc/binary-compatibility.rst: New file. + * doc/gcc/c++-implementation-defined-behavior.rst: New file. + * doc/gcc/c-implementation-defined-behavior.rst: New file. + * doc/gcc/c-implementation-defined-behavior/architecture.rst: New file. + * doc/gcc/c-implementation-defined-behavior/arrays-and-pointers.rst: New file. + * doc/gcc/c-implementation-defined-behavior/characters.rst: New file. + * doc/gcc/c-implementation-defined-behavior/declarators.rst: New file. + * doc/gcc/c-implementation-defined-behavior/environment.rst: New file. + * doc/gcc/c-implementation-defined-behavior/floating-point.rst: New file. + * doc/gcc/c-implementation-defined-behavior/hints.rst: New file. + * doc/gcc/c-implementation-defined-behavior/identifiers.rst: New file. + * doc/gcc/c-implementation-defined-behavior/integers.rst: New file. + * doc/gcc/c-implementation-defined-behavior/library-functions.rst: New file. + * doc/gcc/c-implementation-defined-behavior/locale-specific-behavior.rst: New file. + * doc/gcc/c-implementation-defined-behavior/preprocessing-directives.rst: New file. + * doc/gcc/c-implementation-defined-behavior/qualifiers.rst: New file. + * doc/gcc/c-implementation-defined-behavior/statements.rst: New file. + * doc/gcc/c-implementation-defined-behavior/structures-unions-enumerations-and-bit-fields.rst: + New file. + * doc/gcc/c-implementation-defined-behavior/translation.rst: New file. + * doc/gcc/conditionally-supported-behavior.rst: New file. + * doc/gcc/conf.py: New file. + * doc/gcc/contributing-to-gcc-development.rst: New file. + * doc/gcc/contributors-to-gcc.rst: New file. + * doc/gcc/copyright.rst: New file. + * doc/gcc/exception-handling.rst: New file. + * doc/gcc/extensions-to-the-c++-language.rst: New file. + * doc/gcc/extensions-to-the-c++-language/backwards-compatibility.rst: New file. + * doc/gcc/extensions-to-the-c++-language/c++-concepts.rst: New file. + * doc/gcc/extensions-to-the-c++-language/c++-interface-and-implementation-pragmas.rst: + New file. + * doc/gcc/extensions-to-the-c++-language/c++-specific-variable-function-and-type-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c++-language/deprecated-features.rst: New file. + * doc/gcc/extensions-to-the-c++-language/extracting-the-function-pointer-from-a-bound-pointer-to-member-function.rst: + New file. + * doc/gcc/extensions-to-the-c++-language/function-multiversioning.rst: New file. + * doc/gcc/extensions-to-the-c++-language/restricting-pointer-aliasing.rst: New file. + * doc/gcc/extensions-to-the-c++-language/type-traits.rst: New file. + * doc/gcc/extensions-to-the-c++-language/vague-linkage.rst: New file. + * doc/gcc/extensions-to-the-c++-language/when-is-a-volatile-c++-object-accessed.rst: + New file. + * doc/gcc/extensions-to-the-c++-language/wheres-the-template.rst: New file. + * doc/gcc/extensions-to-the-c-language-family.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/128-bit-integers.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/additional-floating-types.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/alternate-keywords.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/an-inline-function-is-as-fast-as-a-macro.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/arithmetic-on-void-and-function-pointers.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/arrays-of-length-zero.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/arrays-of-variable-length.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/attribute-syntax.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/binary-constants-using-the-0b-prefix.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/built-in-functions-for-memory-model-aware-atomic-operations.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/built-in-functions-to-perform-arithmetic-with-overflow-checking.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/c++-style-comments.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/case-ranges.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/cast-to-a-union-type.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/complex-numbers.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/compound-literals.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/conditionals-with-omitted-operands.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/constructing-function-calls.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/decimal-floating-types.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/aarch64-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/amd-gcn-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/arc-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/arm-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/avr-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/blackfin-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/bpf-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/c-sky-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/common-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/epiphany-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/h8-300-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/ia-64-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/m32c-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/m32r-d-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/m68k-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/mcore-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/mep-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/microblaze-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/microsoft-windows-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/mips-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/msp430-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/nds32-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/nios-ii-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/nvidia-ptx-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/powerpc-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/risc-v-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/rl78-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/rx-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/s-390-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/sh-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/symbian-os-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/v850-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/visium-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/x86-function-attributes.rst: + New file. + * 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doc/gccint/target-macros/support-for-nested-functions.rst: New file. + * doc/gccint/target-macros/the-global-targetm-variable.rst: New file. + * doc/gccint/target-makefile-fragments.rst: New file. + * doc/gccint/testsuites.rst: New test. + * doc/gccint/testsuites/ada-language-testsuites.rst: New test. + * doc/gccint/testsuites/c-language-testsuites.rst: New test. + * doc/gccint/testsuites/directives-used-within-dejagnu-tests.rst: New test. + * doc/gccint/testsuites/directives-used-within-dejagnu-tests/commands-for-use-in-dg-final.rst: + New test. + * doc/gccint/testsuites/directives-used-within-dejagnu-tests/features-for-dg-add-options.rst: + New test. + * doc/gccint/testsuites/directives-used-within-dejagnu-tests/keywords-describing-target-attributes.rst: + New test. + * doc/gccint/testsuites/directives-used-within-dejagnu-tests/selecting-targets-to-which-a-test-applies.rst: + New test. + * doc/gccint/testsuites/directives-used-within-dejagnu-tests/syntax-and-descriptions-of-test-directives.rst: + New test. + * doc/gccint/testsuites/directives-used-within-dejagnu-tests/variants-of-dg-require-support.rst: + New test. + * doc/gccint/testsuites/idioms-used-in-testsuite-code.rst: New test. + * doc/gccint/testsuites/support-for-testing-binary-compatibility.rst: New test. + * doc/gccint/testsuites/support-for-testing-gcov.rst: New test. + * doc/gccint/testsuites/support-for-testing-gimple-passes.rst: New test. + * doc/gccint/testsuites/support-for-testing-link-time-optimizations.rst: New test. + * doc/gccint/testsuites/support-for-testing-profile-directed-optimizations.rst: New test. + * doc/gccint/testsuites/support-for-testing-rtl-passes.rst: New test. + * doc/gccint/testsuites/support-for-torture-testing-using-multiple-options.rst: New test. + * doc/gccint/the-gcc-low-level-runtime-library.rst: New file. + * doc/gccint/the-gcc-low-level-runtime-library/language-independent-routines-for-exception-handling.rst: + New file. + * doc/gccint/the-gcc-low-level-runtime-library/miscellaneous-runtime-library-routines.rst: + New file. + * doc/gccint/the-gcc-low-level-runtime-library/routines-for-decimal-floating-point-emulation.rst: + New file. + * doc/gccint/the-gcc-low-level-runtime-library/routines-for-fixed-point-fractional-emulation.rst: + New file. + * doc/gccint/the-gcc-low-level-runtime-library/routines-for-floating-point-emulation.rst: + New file. + * doc/gccint/the-gcc-low-level-runtime-library/routines-for-integer-arithmetic.rst: + New file. + * doc/gccint/the-language.rst: New file. + * doc/gccint/user-experience-guidelines.rst: New file. + * doc/install/binaries.rst: New file. + * doc/install/building.rst: New file. + * doc/install/building/building-a-cross-compiler.rst: New file. + * doc/install/building/building-a-native-compiler.rst: New file. + * doc/install/building/building-in-parallel.rst: New file. + * doc/install/building/building-the-ada-compiler.rst: New file. + * doc/install/building/building-the-d-compiler.rst: New file. + * doc/install/building/building-with-profile-feedback.rst: New file. + * doc/install/conf.py: New file. + * doc/install/configuration.rst: New file. + * doc/install/copyright.rst: New file. + * doc/install/downloading-gcc.rst: New file. + * doc/install/final-installation.rst: New file. + * doc/install/gnu-free-documentation-license.rst: New file. + * doc/install/host-target-specific-installation-notes-for-gcc.rst: New file. + * doc/install/how-can-you-run-the-testsuite-on-selected-tests.rst: New test. + * doc/install/how-to-interpret-test-results.rst: New file. + * doc/install/index.rst: New file. + * doc/install/indices-and-tables.rst: New file. + * doc/install/installing-gcc.rst: New file. + * doc/install/passing-options-and-running-multiple-testsuites.rst: New test. + * doc/install/prerequisites.rst: New file. + * doc/install/submitting-test-results.rst: New file. + * doc/install/testing.rst: New file. + +2022-11-14 Martin Liska <mliska@suse.cz> + + * doc/gcc/gcc-command-options/options-controlling-c++-dialect.rst: Revert. + +2022-11-14 Martin Liska <mliska@suse.cz> + + Revert: + 2022-11-14 Martin Liska <mliska@suse.cz> + + * common/common-target.def: Port to RST. + * target.def: Port to RST. + +2022-11-14 Martin Liska <mliska@suse.cz> + + Revert: + 2022-11-09 Martin Liska <mliska@suse.cz> + + * doc/gccint/target-macros/adding-support-for-named-address-spaces.rst: Use tm.rst.in file. + * doc/gccint/target-macros/addressing-modes.rst: Likewise. + * doc/gccint/target-macros/adjusting-the-instruction-scheduler.rst: Likewise. + * doc/gccint/target-macros/anchored-addresses.rst: Likewise. + * doc/gccint/target-macros/c++-abi-parameters.rst: Likewise. + * doc/gccint/target-macros/condition-code-status.rst: Likewise. + * doc/gccint/target-macros/controlling-debugging-information-format.rst: Likewise. + * doc/gccint/target-macros/controlling-the-compilation-driver-gcc.rst: Likewise. + * doc/gccint/target-macros/d-abi-parameters.rst: Likewise. + * doc/gccint/target-macros/defining-target-specific-uses-of-attribute.rst: Likewise. + * doc/gccint/target-macros/defining-the-output-assembler-language/assembler-commands-for-exception-regions.rst: + Likewise. + * doc/gccint/target-macros/defining-the-output-assembler-language/macros-controlling-initialization-routines.rst: + Likewise. + * doc/gccint/target-macros/defining-the-output-assembler-language/output-and-generation-of-labels.rst: + Likewise. + * doc/gccint/target-macros/defining-the-output-assembler-language/output-of-assembler-instructions.rst: + Likewise. + * doc/gccint/target-macros/defining-the-output-assembler-language/output-of-data.rst: + Likewise. + * doc/gccint/target-macros/defining-the-output-assembler-language/output-of-dispatch-tables.rst: + Likewise. + * doc/gccint/target-macros/defining-the-output-assembler-language/the-overall-framework-of-an-assembler-file.rst: + Likewise. + * doc/gccint/target-macros/describing-relative-costs-of-operations.rst: Likewise. + * doc/gccint/target-macros/dividing-the-output-into-sections-texts-data.rst: Likewise. + * doc/gccint/target-macros/emulating-tls.rst: Likewise. + * doc/gccint/target-macros/implementing-the-varargs-macros.rst: Likewise. + * doc/gccint/target-macros/implicit-calls-to-library-routines.rst: Likewise. + * doc/gccint/target-macros/layout-of-source-language-data-types.rst: Likewise. + * doc/gccint/target-macros/miscellaneous-parameters.rst: Likewise. + * doc/gccint/target-macros/mode-switching-instructions.rst: Likewise. + * doc/gccint/target-macros/parameters-for-precompiled-header-validity-checking.rst: + Likewise. + * doc/gccint/target-macros/register-classes.rst: Likewise. + * doc/gccint/target-macros/register-usage.rst: Likewise. + * doc/gccint/target-macros/run-time-target-specification.rst: Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/basic-stack-layout.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/eliminating-frame-pointer-and-arg-pointer.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/function-entry-and-exit.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/generating-code-for-profiling.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/how-large-values-are-returned.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/how-scalar-function-values-are-returned.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/miscellaneous-register-hooks.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/passing-arguments-in-registers.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/passing-function-arguments-on-the-stack.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/permitting-tail-calls.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/registers-that-address-the-stack-frame.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/shrink-wrapping-separate-components.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/specifying-how-stack-checking-is-done.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/stack-smashing-protection.rst: + Likewise. + * doc/gccint/target-macros/storage-layout.rst: Likewise. + * doc/gccint/target-macros/support-for-nested-functions.rst: Likewise. + +2022-11-14 Martin Liska <mliska@suse.cz> + + Revert: + 2022-11-14 Martin Liska <mliska@suse.cz> + + * Makefile.in: Support Sphinx based documentation. + * configure: Regenerate. + * configure.ac: Support Sphinx based documentation. + * genhooks.cc (struct s_hook): Emit tm.rst.in file. + +2022-11-14 Martin Liska <mliska@suse.cz> + + Revert: + 2022-11-09 Martin Liska <mliska@suse.cz> + + * doc/gccint/target-macros/tm.rst.in: New file. + +2022-11-14 Martin Liska <mliska@suse.cz> + + Revert: + 2022-11-14 Martin Liska <mliska@suse.cz> + + * doc/analyzer.texi: Removed. + * doc/avr-mmcu.texi: Removed. + * doc/bugreport.texi: Removed. + * doc/cfg.texi: Removed. + * doc/collect2.texi: Removed. + * doc/compat.texi: Removed. + * doc/configfiles.texi: Removed. + * doc/configterms.texi: Removed. + * doc/contrib.texi: Removed. + * doc/contribute.texi: Removed. + * doc/cpp.texi: Removed. + * doc/cppdiropts.texi: Removed. + * doc/cppenv.texi: Removed. + * doc/cppinternals.texi: Removed. + * doc/cppopts.texi: Removed. + * doc/cppwarnopts.texi: Removed. + * doc/extend.texi: Removed. + * doc/fragments.texi: Removed. + * doc/frontends.texi: Removed. + * doc/gcc.texi: Removed. + * doc/gccint.texi: Removed. + * doc/gcov-dump.texi: Removed. + * doc/gcov-tool.texi: Removed. + * doc/gcov.texi: Removed. + * doc/generic.texi: Removed. + * doc/gimple.texi: Removed. + * doc/gnu.texi: Removed. + * doc/gty.texi: Removed. + * doc/headerdirs.texi: Removed. + * doc/hostconfig.texi: Removed. + * doc/implement-c.texi: Removed. + * doc/implement-cxx.texi: Removed. + * doc/include/fdl.texi: Removed. + * doc/include/funding.texi: Removed. + * doc/include/gcc-common.texi: Removed. + * doc/include/gpl_v3.texi: Removed. + * doc/install.texi: Removed. + * doc/interface.texi: Removed. + * doc/invoke.texi: Removed. + * doc/languages.texi: Removed. + * doc/libgcc.texi: Removed. + * doc/loop.texi: Removed. + * doc/lto-dump.texi: Removed. + * doc/lto.texi: Removed. + * doc/makefile.texi: Removed. + * doc/match-and-simplify.texi: Removed. + * doc/md.texi: Removed. + * doc/objc.texi: Removed. + * doc/optinfo.texi: Removed. + * doc/options.texi: Removed. + * doc/passes.texi: Removed. + * doc/plugins.texi: Removed. + * doc/poly-int.texi: Removed. + * doc/portability.texi: Removed. + * doc/rtl.texi: Removed. + * doc/service.texi: Removed. + * doc/sourcebuild.texi: Removed. + * doc/standards.texi: Removed. + * doc/tm.texi: Removed. + * doc/tree-ssa.texi: Removed. + * doc/trouble.texi: Removed. + * doc/ux.texi: Removed. + * doc/tm.texi.in: Removed. + +2022-11-14 Martin Liska <mliska@suse.cz> + + Revert: + 2022-11-09 Martin Liska <mliska@suse.cz> + + * target.def: Use proper lexers for target macros. + * doc/gccint/target-macros/tm.rst.in: Re-generate. + +2022-11-14 Martin Liska <mliska@suse.cz> + + Revert: + 2022-11-09 Martin Liska <mliska@suse.cz> + + * Makefile.in: Support --with-sphinx-build. + * configure.ac: + * configure: Regenerate. + +2022-11-14 Martin Liska <mliska@suse.cz> + + Revert: + 2022-11-14 Martin Liska <mliska@suse.cz> + + * doc/gcc/gcc-command-options/options-controlling-the-kind-of-output.rst: + Fix cross manual refs. + * doc/gcc/language-standards-supported-by-gcc/references-for-other-languages.rst: + Likewise. + +2022-11-14 Martin Liska <mliska@suse.cz> + + Revert: + 2022-11-09 Martin Liska <mliska@suse.cz> + + * doc/gccint/target-macros/defining-the-output-assembler-language/assembler-commands-for-exception-regions.rst: + Do not include tm.rst.in. + * doc/gccint/target-macros/defining-the-output-assembler-language/the-overall-framework-of-an-assembler-file.rst: + Likewise. + * doc/gccint/target-macros/run-time-target-specification.rst: + Likewise. + +2022-11-14 Martin Liska <mliska@suse.cz> + + Revert: + 2022-11-09 Martin Liska <mliska@suse.cz> + + * doc/gccint/target-macros/stack-layout-and-calling-conventions/passing-arguments-in-registers.rst: + Port to RST. + * doc/gccint/target-macros/storage-layout.rst: Likewise. + * doc/gcc/gcc-command-options/machine-dependent-options/x86-options.rst: Sync with master. + * doc/gcc/gcc-command-options/option-summary.rst: Likewise. + +2022-11-14 Martin Liska <mliska@suse.cz> + + Revert: + 2022-11-09 Martin Liska <mliska@suse.cz> + + * Makefile.in: Support installation if sphinx-build is missing. + +2022-11-14 Martin Liska <mliska@suse.cz> + + Revert: + 2022-11-09 Martin Liska <mliska@suse.cz> + + * Makefile.in: Add vpath default for .rst files. + * config/avr/avr-devices.cc: For port RST. + * config/avr/avr-mcus.def: Update path. + * config/avr/gen-avr-mmcu-texi.cc: Moved to... + * config/avr/gen-avr-mmcu-rst.cc: ...here. + * config/avr/t-avr: Update to rst. + * doc/gcc/gcc-command-options/machine-dependent-options/avr-mmcu.rst: Re-generate. + +2022-11-14 Martin Liska <mliska@suse.cz> + + Revert: + 2022-11-09 Martin Liska <mliska@suse.cz> + + * opts.cc (get_option_html_page): Port to sphinx URLs. + (get_option_url): Likewise. + (test_get_option_html_page): Likewise. + +2022-11-14 Martin Liska <mliska@suse.cz> + + Revert: + 2022-11-14 Martin Liska <mliska@suse.cz> + + * doc/cpp/character-sets.rst: + Add trailing newline. + * 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doc/install/submitting-test-results.rst: + Add trailing newline. + * doc/install/testing.rst: + Add trailing newline. + +2022-11-14 Martin Liska <mliska@suse.cz> + + Revert: + 2022-11-14 Martin Liska <mliska@suse.cz> + + * Makefile.in: Use new install URL. + * doc/gcc/gcc-command-options/machine-dependent-options/avr-options.rst: + Use intersphinx link. + * doc/gcc/gcc-command-options/options-to-control-diagnostic-messages-formatting.rst: + Use new URL. + * doc/gccint/source-tree-structure-and-build-system.rst: Use + intersphinx link. + * doc/install/host-target-specific-installation-notes-for-gcc.rst: Likewise. + * doc/install/installing-gcc.rst: Likewise. + +2022-11-14 Martin Liska <mliska@suse.cz> + + Revert: + 2022-11-09 Martin Liska <mliska@suse.cz> + Sinan <sinan.lin@linux.alibaba.com> + + * doc/gccint/analysis-and-optimization-of-gimple-tuples/ssa-operands.rst: + Add missing variable name. + +2022-11-14 Martin Liska <mliska@suse.cz> + + Revert: + 2022-11-14 Martin Liska <mliska@suse.cz> + + * doc/cpp/conf.py: Add newline at last line. + * doc/cppinternals/conf.py: Add newline at last line. + * doc/gcc/conf.py: Add newline at last line. + * doc/gccint/conf.py: Add newline at last line. + * doc/install/conf.py: Add newline at last line. + +2022-11-14 Martin Liska <mliska@suse.cz> + + * doc/gcc/gcc-command-options/options-that-control-static-analysis.rst: + Revert. + +2022-11-14 Martin Liska <mliska@suse.cz> + + * doc/cpp/pragmas.rst: Revert. + +2022-11-14 Martin Liska <mliska@suse.cz> + + * doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst: Revert. + +2022-11-14 Martin Liska <mliska@suse.cz> + + * doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst: Revert. + +2022-11-14 Martin Liska <mliska@suse.cz> + + * doc/gcc/gcc-command-options/options-that-control-static-analysis.rst: Revert. + * doc/gcc/gcc-command-options/options-to-request-or-suppress-warnings.rst: Revert. + +2022-11-14 Martin Liska <mliska@suse.cz> + + Revert: + 2022-11-13 Jonathan Wakely <jwakely@redhat.com> + + * doc/install/testing.rst: Remove anachronism about separate + source tarballs. + +2022-11-14 Martin Liska <mliska@suse.cz> + + Revert: + 2022-11-13 Martin Liska <mliska@suse.cz> + + PR other/107620 + * configure: Regenerate. + * configure.ac: Always set sphinx-build. + +2022-11-14 Martin Liska <mliska@suse.cz> + + * doc/gcc/gcc-command-options/option-summary.rst: Revert. + * doc/gcc/gcc-command-options/options-that-control-static-analysis.rst: Revert. + +2022-11-14 Haochen Jiang <haochen.jiang@intel.com> + + * common/config/i386/i386-common.cc + (OPTION_MASK_ISA2_AMX_INT8_SET): Add AMX-TILE dependency. + (OPTION_MASK_ISA2_AMX_BF16_SET): Ditto. + (OPTION_MASK_ISA2_AMX_FP16_SET): Ditto. + (OPTION_MASK_ISA2_AMX_TILE_UNSET): Disable AMX_{INT8, + BF16, FP16} when disable AMX_TILE. + +2022-11-14 Martin Liska <mliska@suse.cz> + + * doc/gcc/gcc-command-options/machine-dependent-options/x86-options.rst: + Revert. + * doc/gcc/gcc-command-options/option-summary.rst: + Revert. + +2022-11-14 Hongyu Wang <hongyu.wang@intel.com> + + * common/config/i386/i386-common.cc (ix86_optimization_table): + Enable small loop unroll at O2 by default. + * config/i386/i386.cc (ix86_loop_unroll_adjust): Adjust unroll + factor if -munroll-only-small-loops enabled and -funroll-loops/ + -funroll-all-loops are disabled. + * config/i386/i386.h (struct processor_costs): Add 2 field + small_unroll_ninsns and small_unroll_factor. + * config/i386/i386.opt: Add -munroll-only-small-loops. + * doc/gcc/gcc-command-options/machine-dependent-options/x86-options.rst: + Document -munroll-only-small-loops. + * doc/gcc/gcc-command-options/option-summary.rst: Likewise. + * loop-init.cc (pass_rtl_unroll_loops::gate): Enable rtl + loop unrolling for -O2-speed and above if target hook + loop_unroll_adjust exists. + (pass_rtl_unroll_loops::execute): Set UAP_UNROLL flag + when target hook loop_unroll_adjust exists. + * config/i386/x86-tune-costs.h: Update all processor costs + with small_unroll_ninsns = 4 and small_unroll_factor = 2. + +2022-11-13 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/106235 + * doc/gcc/gcc-command-options/option-summary.rst: Add + -Wno-analyzer-tainted-assertion. + * doc/gcc/gcc-command-options/options-that-control-static-analysis.rst: + Add -Wno-analyzer-tainted-assertion. + +2022-11-13 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/bitmanip.md: New define_split. + +2022-11-13 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/riscv.cc (riscv_rtx_costs): Recognize shNadd, + if expressed as a plus and multiplication with a power-of-2. + Split costing for MINUS from PLUS. + +2022-11-13 Martin Liska <mliska@suse.cz> + + PR other/107620 + * configure: Regenerate. + * configure.ac: Always set sphinx-build. + +2022-11-13 Joseph Myers <joseph@codesourcery.com> + + * ginclude/float.h [__STDC_VERSION__ > 201710L] + (__STDC_VERSION_FLOAT_H__): New macro. + * ginclude/stdarg.h [__STDC_VERSION__ > 201710L] + (__STDC_VERSION_STDARG_H__): New macro. + * ginclude/stdatomic.h [__STDC_VERSION__ > 201710L] + (__STDC_VERSION_STDATOMIC_H__): New macro. + * ginclude/stddef.h [__STDC_VERSION__ > 201710L] + (__STDC_VERSION_STDDEF_H__): New macro. + * ginclude/stdint-gcc.h [__STDC_VERSION__ > 201710L] + (__STDC_VERSION_STDINT_H__): New macro. + * glimits.h [__STDC_VERSION__ > 201710L] + (__STDC_VERSION_LIMITS_H__): New macro. + +2022-11-13 Jonathan Wakely <jwakely@redhat.com> + + * doc/install/testing.rst: Remove anachronism about separate + source tarballs. + +2022-11-12 Joseph Myers <joseph@codesourcery.com> + + * dfp.cc (decimal_from_binary): Convert a canonical NaN to a + canonical NaN. + +2022-11-12 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (range_tests_signbit): Move to set from here... + (range_tests_signed_zeros): ...to here. + +2022-11-12 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (build_lt): Adjust with frange_nextafter + instead of default to a closed range. + (build_gt): Same. + +2022-11-12 Aldy Hernandez <aldyh@redhat.com> + Jakub Jelinek <jakub@redhat.com> + + * range-op-float.cc (float_binary_op_range_finish): New function. + (foperator_plus::op1_range): New. + (foperator_plus::op2_range): New. + (foperator_minus::op1_range): New. + (foperator_minus::op2_range): New. + (foperator_mult::op1_range): New. + (foperator_mult::op2_range): New. + (foperator_div::op1_range): New. + (foperator_div::op2_range): New. + +2022-11-12 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/107569 + * range-op-float.cc (zero_p, contains_p, singleton_inf_p, + signbit_known_p, zero_range, inf_range, zero_to_inf_range): New + functions. + (foperator_mult_div_base): New class. + (foperator_mult, foperator_div): Derive from that and use + protected static method from it as well as above new functions + to simplify the code. + +2022-11-12 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/107569 + * range-op-float.cc (foperator_div): New class. + (floating_op_table::floating_op_table): Use foperator_div + for RDIV_EXPR. + +2022-11-12 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/107569 + PR tree-optimization/107591 + * range-op.h (range_operator_float::rv_fold): Add relation_kind + argument. + * range-op-float.cc (range_operator_float::fold_range): Name + last argument trio and pass trio.op1_op2 () as last argument to + rv_fold. + (range_operator_float::rv_fold): Add relation_kind argument. + (foperator_plus::rv_fold, foperator_minus::rv_fold): Likewise. + (foperator_mult): New class. + (floating_op_table::floating_op_table): Use foperator_mult for + MULT_EXPR. + +2022-11-12 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/loongarch.md (UNSPEC_FLOGB): New unspec. + (type): Add flogb. + (logb_non_negative<mode>2): New instruction template. + (logb<mode>2): New define_expand. + +2022-11-12 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/loongarch.md (UNSPEC_FSCALEB): New unspec. + (type): Add fscaleb. + (IMODE): New mode attr. + (ldexp<mode>3): New instruction template. + +2022-11-12 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/loongarch.md (UNSPEC_FTINT): New unspec. + (UNSPEC_FTINTRM): Likewise. + (UNSPEC_FTINTRP): Likewise. + (LRINT): New define_int_iterator. + (lrint_pattern): New define_int_attr. + (lrint_submenmonic): Likewise. + (lrint_allow_inexact): Likewise. + (ANYFI): New define_mode_iterator. + (lrint<ANYF><ANYFI>): New instruction template. + +2022-11-12 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/loongarch.md (frint_<fmt>): Rename to .. + (rint<mode>2): .. this. + +2022-11-11 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/106147 + * doc/gcc/gcc-command-options/options-that-control-static-analysis.rst: + Add -Wanalyzer-infinite-recursion. + * doc/gcc/gcc-command-options/options-to-request-or-suppress-warnings.rst + (-Winfinite-recursion): Mention -Wanalyzer-infinite-recursion. + +2022-11-11 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/106147 + * Makefile.in (ANALYZER_OBJS): Add analyzer/infinite-recursion.o. + +2022-11-11 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/107523 + * gimple-range.cc (gimple_ranger::update_stmt): Use fur_stmt + rather than fur_depend. + +2022-11-11 Andrew MacLeod <amacleod@redhat.com> + + * tree-vrp.cc (rvrp_folder::rvrp_folder): Init m_last_bb_stmt. + (rvrp_folder::pre_fold_bb): Set m_last_bb_stmt. + (rvrp_folder::pre_fold_stmt): Check for transitive inferred ranges. + (rvrp_folder::fold_stmt): Check in pre_fold_stmt instead. + +2022-11-11 Srinath Parvathaneni <srinath.parvathaneni@arm.com> + + * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-X1C + CPU. + * config/aarch64/aarch64-tune.md: Regenerate. + * doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst: + Document Cortex-X1C CPU. + +2022-11-11 Srinath Parvathaneni <srinath.parvathaneni@arm.com> + + * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-A715 + CPU. + * config/aarch64/aarch64-tune.md: Regenerate. + * doc/gcc/gcc-command-options/machine-dependent-options/aarch64-options.rst: + Document Cortex-A715 CPU. + +2022-11-11 Richard Biener <rguenther@suse.de> + Nikita Voronov <nik_1357@mail.ru> + + PR tree-optimization/107554 + * tree-ssa-strlen.cc (strlen_pass::count_nonzero_bytes): + Use unsigned HOST_WIDE_INT type for the strlen. + +2022-11-11 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105142 + * gimple-fold.cc (fosa_unwind): New global. + (follow_outer_ssa_edges): When the SSA definition to follow + is does not dominate fosa_bb, temporarily clear flow-sensitive + info. Make sure to not expand stmts with not defined overflow. + (maybe_fold_comparisons_from_match_pd): Set up unwind stack + for follow_outer_ssa_edges and unwind flow-sensitive info + clearing after matching. + +2022-11-11 Aldy Hernandez <aldyh@redhat.com> + + * range-op.cc (operator_mult::fold_range): Remove. + (operator_div::fold_range): Remove. + (operator_bitwise_and): Remove. + +2022-11-11 Aldy Hernandez <aldyh@redhat.com> + + * range-op.cc (update_known_bitmask): Avoid unnecessary intersection. + +2022-11-11 Aldy Hernandez <aldyh@redhat.com> + + * range-op.cc (range_operator::fold_range): Call + update_known_bitmask. + (operator_bitwise_and::fold_range): Avoid setting nonzero bits + when range is undefined. + +2022-11-11 Aldy Hernandez <aldyh@redhat.com> + + * range-op.cc (class operator_div): Remove tree code. + (operator_div::wi_op_overflows): Handle EXACT_DIV_EXPR as + TRUNC_DIV_EXPR. + +2022-11-11 Aldy Hernandez <aldyh@redhat.com> + + * range-op.cc: (range_op_table::set): Set m_code. + (integral_table::integral_table): Handle shared entries. + (pointer_table::pointer_table): Same. + * range-op.h (class range_operator): Add m_code. + +2022-11-11 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107618 + * tree-ssa-copy.cc (stmt_may_generate_copy): Simulate all + assignments with a single SSA use. + (copy_prop_visit_assignment): Use gimple_fold_stmt_to_constant_1 + to perform simple constant folding. + (copy_prop::visit_stmt): Visit all assignments. + +2022-11-11 Richard Biener <rguenther@suse.de> + + PR tree-optimization/84646 + * tree-ssa-dce.cc (pass_dce::set_pass_param): Add param + wheter to run update-address-taken. + (pass_dce::execute): Honor it. + * passes.def: Exchange last DCE and CD-DCE invocations. + Swap pass_tail_calls and the last DCE. + +2022-11-11 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + Monk Chiang <monk.chiang@sifive.com> + + * config/riscv/riscv-v.cc (emit_pred_move): Adjust for scalable register spilling. + (legitimize_move): Ditto. + * config/riscv/riscv.cc (riscv_v_adjust_scalable_frame): New function. + (riscv_first_stack_step): Adjust for scalable register spilling. + (riscv_expand_prologue): Ditto. + (riscv_expand_epilogue): Ditto. + (riscv_dwarf_poly_indeterminate_value): New function. + (TARGET_DWARF_POLY_INDETERMINATE_VALUE): New target hook support for register spilling. + * config/riscv/riscv.h (RISCV_DWARF_VLENB): New macro. + (RISCV_PROLOGUE_TEMP2_REGNUM): Ditto. + (RISCV_PROLOGUE_TEMP2): Ditto. + * config/riscv/vector-iterators.md: New iterators. + * config/riscv/vector.md (*mov<mode>): Fix it for register spilling. + (*mov<mode>_whole): New pattern. + (*mov<mode>_fract): New pattern. + (@pred_mov<mode>): Fix it for register spilling. + +2022-11-11 Jonathan Wakely <jwakely@redhat.com> + + PR c/85487 + * doc/cpp/pragmas.rst (Pragmas): Document region pragmas. + +2022-11-11 Haochen Jiang <haochen.jiang@intel.com> + + * config/i386/i386-builtin.def (BDESC): Add + OPTION_MASK_ISA2_PREFETCHI for prefetchi builtin. + * config/i386/i386-expand.cc (ix86_expand_builtin): + Add ISA check before emit_insn. + * config/i386/prfchiintrin.h: Add target for intrin. + +2022-11-10 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/99671 + * tristate.h (tristate::is_unknown): New. + +2022-11-10 David Malcolm <dmalcolm@redhat.com> + + * doc/gcc/gcc-command-options/options-that-control-static-analysis.rst: + Add -Wanalyzer-deref-before-check. + +2022-11-10 Marek Polacek <polacek@redhat.com> + + * doc/gcc/gcc-command-options/options-controlling-c++-dialect.rst: + Extend the description of -Wdangling-reference. + +2022-11-10 Andrew Pinski <apinski@marvell.com> + + * config/bfin/bfin.h (SLOW_SHORT_ACCESS): Delete. + * config/i386/i386.h (SLOW_SHORT_ACCESS): Delete. + * system.h: Poison SLOW_SHORT_ACCESS + +2022-11-10 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (frange::set_nonnegative): Remove NAN sign handling. + (range_tests_signed_zeros): Adjust test. + +2022-11-10 Richard Biener <rguenther@suse.de> + + PR tree-optimization/84646 + * tree-ssa-forwprop.cc (pass_forwprop::execute): Improve + copy propagation across PHIs. + +2022-11-10 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/riscv-cores.def (RISCV_TUNE): Update + sifive-7-series to point to the sifive_7 pipeline description. + +2022-11-10 Richard Biener <rguenther@suse.de> + + PR tree-optimization/84646 + * tree-ssa-ccp.cc (set_lattice_value): Make sure we + allow a const -> copy transition and avoid using meet + in that case. + +2022-11-10 Martin Liska <mliska@suse.cz> + + * doc/cpp/conf.py: Add newline at last line. + * doc/cppinternals/conf.py: Add newline at last line. + * doc/gcc/conf.py: Add newline at last line. + * doc/gccint/conf.py: Add newline at last line. + * doc/install/conf.py: Add newline at last line. + +2022-11-10 Richard Biener <rguenther@suse.de> + + * tree-ssa-loop-unswitch.cc (init_loop_unswitch_info): First collect + candidates and determine the outermost loop to unswitch. + (tree_ssa_unswitch_loops): First perform all guard hoisting, + then perform unswitching on innermost loop predicates. + (find_unswitching_predicates_for_bb): Keep track of the + outermost loop to unswitch. + (evaluate_bbs): Adjust exit test. + (tree_unswitch_single_loop): Dump whether we unswitched an outer + loop. + (tree_unswitch_loop): Remove assert we unswitch only innermost + loops. + +2022-11-10 Jakub Jelinek <jakub@redhat.com> + + PR target/107585 + PR target/107546 + * config/i386/i386-expand.cc (ix86_expand_int_sse_cmp): Use + gen_int_mode rather than GEN_INT. + +2022-11-09 Martin Liska <mliska@suse.cz> + Sinan <sinan.lin@linux.alibaba.com> + + * doc/gccint/analysis-and-optimization-of-gimple-tuples/ssa-operands.rst: + Add missing variable name. + +2022-11-09 Aldy Hernandez <aldyh@redhat.com> + + * value-range-storage.cc (frange_storage_slot::get_frange): Clear + NAN if appropriate. + * value-range.cc (range_tests_floats): New test. + +2022-11-09 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (class foperator_plus): Remove op[12]_range. + (class foperator_minus): Same. + +2022-11-09 Qing Zhao <qing.zhao@oracle.com> + + * gimple-array-bounds.cc (trailing_array): Replace + array_at_struct_end_p with new name and update comments. + * gimple-fold.cc (get_range_strlen_tree): Likewise. + * gimple-ssa-warn-restrict.cc (builtin_memref::builtin_memref): + Likewise. + * graphite-sese-to-poly.cc (bounds_are_valid): Likewise. + * tree-if-conv.cc (idx_within_array_bound): Likewise. + * tree-object-size.cc (addr_object_size): Likewise. + * tree-ssa-alias.cc (component_ref_to_zero_sized_trailing_array_p): + Likewise. + (stmt_kills_ref_p): Likewise. + * tree-ssa-loop-niter.cc (idx_infer_loop_bounds): Likewise. + * tree-ssa-strlen.cc (maybe_set_strlen_range): Likewise. + * tree.cc (array_at_struct_end_p): Rename to ... + (array_ref_flexible_size_p): ... this. + (component_ref_size): Replace array_at_struct_end_p with new name. + * tree.h (array_at_struct_end_p): Rename to ... + (array_ref_flexible_size_p): ... this. + +2022-11-09 Martin Liska <mliska@suse.cz> + + * Makefile.in: Use new install URL. + * doc/gcc/gcc-command-options/machine-dependent-options/avr-options.rst: + Use intersphinx link. + * doc/gcc/gcc-command-options/options-to-control-diagnostic-messages-formatting.rst: + Use new URL. + * doc/gccint/source-tree-structure-and-build-system.rst: Use + intersphinx link. + * doc/install/host-target-specific-installation-notes-for-gcc.rst: Likewise. + * doc/install/installing-gcc.rst: Likewise. + +2022-11-09 Richard Biener <rguenther@suse.de> + + PR tree-optimization/84646 + * tree-ssa-threadbackward.cc (back_threader::maybe_register_path): + Remove premature cycle rejection. + +2022-11-09 Martin Liska <mliska@suse.cz> + + * doc/cpp/character-sets.rst: + Add trailing newline. + * doc/cpp/conditional-syntax.rst: + Add trailing newline. + * doc/cpp/conditional-uses.rst: + Add trailing newline. + * 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doc/gccint/testsuites/support-for-testing-profile-directed-optimizations.rst: + Add trailing newline. + * doc/gccint/testsuites/support-for-testing-rtl-passes.rst: + Add trailing newline. + * doc/gccint/testsuites/support-for-torture-testing-using-multiple-options.rst: + Add trailing newline. + * doc/gccint/the-gcc-low-level-runtime-library.rst: + Add trailing newline. + * doc/gccint/the-gcc-low-level-runtime-library/language-independent-routines-for-exception-handling.rst: + Add trailing newline. + * doc/gccint/the-gcc-low-level-runtime-library/miscellaneous-runtime-library-routines.rst: + Add trailing newline. + * doc/gccint/the-gcc-low-level-runtime-library/routines-for-decimal-floating-point-emulation.rst: + Add trailing newline. + * doc/gccint/the-gcc-low-level-runtime-library/routines-for-fixed-point-fractional-emulation.rst: + Add trailing newline. + * doc/gccint/the-gcc-low-level-runtime-library/routines-for-floating-point-emulation.rst: + Add trailing newline. + * doc/gccint/the-gcc-low-level-runtime-library/routines-for-integer-arithmetic.rst: + Add trailing newline. + * doc/gccint/the-language.rst: + Add trailing newline. + * doc/gccint/user-experience-guidelines.rst: + Add trailing newline. + * doc/install/binaries.rst: + Add trailing newline. + * doc/install/building.rst: + Add trailing newline. + * doc/install/building/building-a-cross-compiler.rst: + Add trailing newline. + * doc/install/building/building-a-native-compiler.rst: + Add trailing newline. + * doc/install/building/building-in-parallel.rst: + Add trailing newline. + * doc/install/building/building-the-ada-compiler.rst: + Add trailing newline. + * doc/install/building/building-the-d-compiler.rst: + Add trailing newline. + * doc/install/building/building-with-profile-feedback.rst: + Add trailing newline. + * doc/install/configuration.rst: + Add trailing newline. + * doc/install/copyright.rst: + Add trailing newline. + * doc/install/downloading-gcc.rst: + Add trailing newline. + * doc/install/final-installation.rst: + Add trailing newline. + * doc/install/gnu-free-documentation-license.rst: + Add trailing newline. + * doc/install/host-target-specific-installation-notes-for-gcc.rst: + Add trailing newline. + * doc/install/how-can-you-run-the-testsuite-on-selected-tests.rst: + Add trailing newline. + * doc/install/how-to-interpret-test-results.rst: + Add trailing newline. + * doc/install/index.rst: + Add trailing newline. + * doc/install/indices-and-tables.rst: + Add trailing newline. + * doc/install/installing-gcc.rst: + Add trailing newline. + * doc/install/passing-options-and-running-multiple-testsuites.rst: + Add trailing newline. + * doc/install/prerequisites.rst: + Add trailing newline. + * doc/install/submitting-test-results.rst: + Add trailing newline. + * doc/install/testing.rst: + Add trailing newline. + +2022-11-09 Martin Liska <mliska@suse.cz> + + * opts.cc (get_option_html_page): Port to sphinx URLs. + (get_option_url): Likewise. + (test_get_option_html_page): Likewise. + +2022-11-09 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/107569 + * range-op-float.cc (foperator_abs::op1_range): Clear NaNs + from the negatives frange before unioning it into r. + +2022-11-09 Martin Liska <mliska@suse.cz> + + * Makefile.in: Add vpath default for .rst files. + * config/avr/avr-devices.cc: For port RST. + * config/avr/avr-mcus.def: Update path. + * config/avr/gen-avr-mmcu-texi.cc: Moved to... + * config/avr/gen-avr-mmcu-rst.cc: ...here. + * config/avr/t-avr: Update to rst. + * doc/gcc/gcc-command-options/machine-dependent-options/avr-mmcu.rst: Re-generate. + +2022-11-09 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/riscv.cc (riscv_rtx_costs): Add BSWAP. + +2022-11-09 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/loongarch.cc (loongarch_emit_int_compare): + Avoid signed overflow. + +2022-11-09 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (foperator_plus::op1_range): New. + (foperator_plus::op2_range): New. + (foperator_minus::op1_range): New. + (foperator_minus::op2_range): New. + +2022-11-09 Martin Liska <mliska@suse.cz> + + * Makefile.in: Support installation if sphinx-build is missing. + +2022-11-09 Martin Liska <mliska@suse.cz> + + * doc/gccint/target-macros/stack-layout-and-calling-conventions/passing-arguments-in-registers.rst: + Port to RST. + * doc/gccint/target-macros/storage-layout.rst: Likewise. + * doc/gcc/gcc-command-options/machine-dependent-options/x86-options.rst: Sync with master. + * doc/gcc/gcc-command-options/option-summary.rst: Likewise. + +2022-11-09 Martin Liska <mliska@suse.cz> + + * doc/gccint/target-macros/defining-the-output-assembler-language/assembler-commands-for-exception-regions.rst: + Do not include tm.rst.in. + * doc/gccint/target-macros/defining-the-output-assembler-language/the-overall-framework-of-an-assembler-file.rst: + Likewise. + * doc/gccint/target-macros/run-time-target-specification.rst: + Likewise. + +2022-11-09 Martin Liska <mliska@suse.cz> + + * doc/gcc/gcc-command-options/options-controlling-the-kind-of-output.rst: + Fix cross manual refs. + * doc/gcc/language-standards-supported-by-gcc/references-for-other-languages.rst: + Likewise. + +2022-11-09 Martin Liska <mliska@suse.cz> + + * Makefile.in: Support --with-sphinx-build. + * configure.ac: + * configure: Regenerate. + +2022-11-09 Martin Liska <mliska@suse.cz> + + * target.def: Use proper lexers for target macros. + * doc/gccint/target-macros/tm.rst.in: Re-generate. + +2022-11-09 Martin Liska <mliska@suse.cz> + + * doc/analyzer.texi: Removed. + * doc/avr-mmcu.texi: Removed. + * doc/bugreport.texi: Removed. + * doc/cfg.texi: Removed. + * doc/collect2.texi: Removed. + * doc/compat.texi: Removed. + * doc/configfiles.texi: Removed. + * doc/configterms.texi: Removed. + * doc/contrib.texi: Removed. + * doc/contribute.texi: Removed. + * doc/cpp.texi: Removed. + * doc/cppdiropts.texi: Removed. + * doc/cppenv.texi: Removed. + * doc/cppinternals.texi: Removed. + * doc/cppopts.texi: Removed. + * doc/cppwarnopts.texi: Removed. + * doc/extend.texi: Removed. + * doc/fragments.texi: Removed. + * doc/frontends.texi: Removed. + * doc/gcc.texi: Removed. + * doc/gccint.texi: Removed. + * doc/gcov-dump.texi: Removed. + * doc/gcov-tool.texi: Removed. + * doc/gcov.texi: Removed. + * doc/generic.texi: Removed. + * doc/gimple.texi: Removed. + * doc/gnu.texi: Removed. + * doc/gty.texi: Removed. + * doc/headerdirs.texi: Removed. + * doc/hostconfig.texi: Removed. + * doc/implement-c.texi: Removed. + * doc/implement-cxx.texi: Removed. + * doc/include/fdl.texi: Removed. + * doc/include/funding.texi: Removed. + * doc/include/gcc-common.texi: Removed. + * doc/include/gpl_v3.texi: Removed. + * doc/install.texi: Removed. + * doc/interface.texi: Removed. + * doc/invoke.texi: Removed. + * doc/languages.texi: Removed. + * doc/libgcc.texi: Removed. + * doc/loop.texi: Removed. + * doc/lto-dump.texi: Removed. + * doc/lto.texi: Removed. + * doc/makefile.texi: Removed. + * doc/match-and-simplify.texi: Removed. + * doc/md.texi: Removed. + * doc/objc.texi: Removed. + * doc/optinfo.texi: Removed. + * doc/options.texi: Removed. + * doc/passes.texi: Removed. + * doc/plugins.texi: Removed. + * doc/poly-int.texi: Removed. + * doc/portability.texi: Removed. + * doc/rtl.texi: Removed. + * doc/service.texi: Removed. + * doc/sourcebuild.texi: Removed. + * doc/standards.texi: Removed. + * doc/tm.texi: Removed. + * doc/tree-ssa.texi: Removed. + * doc/trouble.texi: Removed. + * doc/ux.texi: Removed. + * doc/tm.texi.in: Removed. + +2022-11-09 Martin Liska <mliska@suse.cz> + + * doc/gccint/target-macros/tm.rst.in: New file. + +2022-11-09 Martin Liska <mliska@suse.cz> + + * Makefile.in: Support Sphinx based documentation. + * configure: Regenerate. + * configure.ac: Support Sphinx based documentation. + * genhooks.cc (struct s_hook): Emit tm.rst.in file. + +2022-11-09 Martin Liska <mliska@suse.cz> + + * doc/gccint/target-macros/adding-support-for-named-address-spaces.rst: Use tm.rst.in file. + * doc/gccint/target-macros/addressing-modes.rst: Likewise. + * doc/gccint/target-macros/adjusting-the-instruction-scheduler.rst: Likewise. + * doc/gccint/target-macros/anchored-addresses.rst: Likewise. + * doc/gccint/target-macros/c++-abi-parameters.rst: Likewise. + * doc/gccint/target-macros/condition-code-status.rst: Likewise. + * doc/gccint/target-macros/controlling-debugging-information-format.rst: Likewise. + * doc/gccint/target-macros/controlling-the-compilation-driver-gcc.rst: Likewise. + * doc/gccint/target-macros/d-abi-parameters.rst: Likewise. + * doc/gccint/target-macros/defining-target-specific-uses-of-attribute.rst: Likewise. + * doc/gccint/target-macros/defining-the-output-assembler-language/assembler-commands-for-exception-regions.rst: + Likewise. + * doc/gccint/target-macros/defining-the-output-assembler-language/macros-controlling-initialization-routines.rst: + Likewise. + * doc/gccint/target-macros/defining-the-output-assembler-language/output-and-generation-of-labels.rst: + Likewise. + * doc/gccint/target-macros/defining-the-output-assembler-language/output-of-assembler-instructions.rst: + Likewise. + * doc/gccint/target-macros/defining-the-output-assembler-language/output-of-data.rst: + Likewise. + * doc/gccint/target-macros/defining-the-output-assembler-language/output-of-dispatch-tables.rst: + Likewise. + * doc/gccint/target-macros/defining-the-output-assembler-language/the-overall-framework-of-an-assembler-file.rst: + Likewise. + * doc/gccint/target-macros/describing-relative-costs-of-operations.rst: Likewise. + * doc/gccint/target-macros/dividing-the-output-into-sections-texts-data.rst: Likewise. + * doc/gccint/target-macros/emulating-tls.rst: Likewise. + * doc/gccint/target-macros/implementing-the-varargs-macros.rst: Likewise. + * doc/gccint/target-macros/implicit-calls-to-library-routines.rst: Likewise. + * doc/gccint/target-macros/layout-of-source-language-data-types.rst: Likewise. + * doc/gccint/target-macros/miscellaneous-parameters.rst: Likewise. + * doc/gccint/target-macros/mode-switching-instructions.rst: Likewise. + * doc/gccint/target-macros/parameters-for-precompiled-header-validity-checking.rst: + Likewise. + * doc/gccint/target-macros/register-classes.rst: Likewise. + * doc/gccint/target-macros/register-usage.rst: Likewise. + * doc/gccint/target-macros/run-time-target-specification.rst: Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/basic-stack-layout.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/eliminating-frame-pointer-and-arg-pointer.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/function-entry-and-exit.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/generating-code-for-profiling.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/how-large-values-are-returned.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/how-scalar-function-values-are-returned.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/miscellaneous-register-hooks.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/passing-arguments-in-registers.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/passing-function-arguments-on-the-stack.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/permitting-tail-calls.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/registers-that-address-the-stack-frame.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/shrink-wrapping-separate-components.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/specifying-how-stack-checking-is-done.rst: + Likewise. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/stack-smashing-protection.rst: + Likewise. + * doc/gccint/target-macros/storage-layout.rst: Likewise. + * doc/gccint/target-macros/support-for-nested-functions.rst: Likewise. + +2022-11-09 Martin Liska <mliska@suse.cz> + + * common/common-target.def: Port to RST. + * target.def: Port to RST. + +2022-11-09 Martin Liska <mliska@suse.cz> + + * doc/cpp/character-sets.rst: New file. + * doc/cpp/conditional-syntax.rst: New file. + * doc/cpp/conditional-uses.rst: New file. + * doc/cpp/conditionals.rst: New file. + * doc/cpp/conf.py: New file. + * doc/cpp/copyright.rst: New file. + * doc/cpp/deleted-code.rst: New file. + * doc/cpp/diagnostics.rst: New file. + * doc/cpp/environment-variables.rst: New file. + * doc/cpp/gnu-free-documentation-license.rst: New file. + * doc/cpp/header-files.rst: New file. + * doc/cpp/header-files/alternatives-to-wrapper-ifndef.rst: New file. + * doc/cpp/header-files/computed-includes.rst: New file. + * doc/cpp/header-files/include-operation.rst: New file. + * doc/cpp/header-files/include-syntax.rst: New file. + * doc/cpp/header-files/once-only-headers.rst: New file. + * doc/cpp/header-files/search-path.rst: New file. + * doc/cpp/header-files/system-headers.rst: New file. + * doc/cpp/header-files/wrapper-headers.rst: New file. + * doc/cpp/implementation-defined-behavior.rst: New file. + * doc/cpp/implementation-details.rst: New file. + * doc/cpp/implementation-limits.rst: New file. + * doc/cpp/index.rst: New file. + * doc/cpp/indices-and-tables.rst: New file. + * doc/cpp/initial-processing.rst: New file. + * doc/cpp/invocation.rst: New file. + * doc/cpp/line-control.rst: New file. + * doc/cpp/macros.rst: New file. + * doc/cpp/macros/concatenation.rst: New file. + * doc/cpp/macros/directives-within-macro-arguments.rst: New file. + * doc/cpp/macros/function-like-macros.rst: New file. + * doc/cpp/macros/macro-arguments.rst: New file. + * doc/cpp/macros/macro-pitfalls.rst: New file. + * doc/cpp/macros/object-like-macros.rst: New file. + * doc/cpp/macros/predefined-macros.rst: New file. + * doc/cpp/macros/stringizing.rst: New file. + * doc/cpp/macros/undefining-and-redefining-macros.rst: New file. + * doc/cpp/macros/variadic-macros.rst: New file. + * doc/cpp/obsolete-features.rst: New file. + * doc/cpp/other-directives.rst: New file. + * doc/cpp/overview.rst: New file. + * doc/cpp/pragmas.rst: New file. + * doc/cpp/preprocessor-output.rst: New file. + * doc/cpp/the-preprocessing-language.rst: New file. + * doc/cpp/tokenization.rst: New file. + * doc/cpp/traditional-lexical-analysis.rst: New file. + * doc/cpp/traditional-macros.rst: New file. + * doc/cpp/traditional-miscellany.rst: New file. + * doc/cpp/traditional-mode.rst: New file. + * doc/cpp/traditional-warnings.rst: New file. + * doc/cppinternals/conf.py: New file. + * doc/cppinternals/copyright.rst: New file. + * doc/cppinternals/cppinternals.rst: New file. + * doc/cppinternals/cpplib.rst: New file. + * doc/cppinternals/files.rst: New file. + * doc/cppinternals/index.rst: New file. + * doc/cppinternals/indices-and-tables.rst: New file. + * doc/cppinternals/internal-representation-of-macros.rst: New file. + * doc/cppinternals/just-which-line-number-anyway.rst: New file. + * doc/cppinternals/lexing-a-line.rst: New file. + * doc/cppinternals/lexing-a-token.rst: New file. + * doc/cppinternals/looking-for-a-function-like-macros-opening-parenthesis.rst: New file. + * doc/cppinternals/macro-expansion-overview.rst: New file. + * doc/cppinternals/marking-tokens-ineligible-for-future-expansion.rst: New file. + * doc/cppinternals/multiple-include-optimization.rst: New file. + * doc/cppinternals/overview.rst: New file. + * doc/cppinternals/representation-of-line-numbers.rst: New file. + * doc/cppinternals/scanning-the-replacement-list-for-macros-to-expand.rst: New file. + * doc/gcc/binary-compatibility.rst: New file. + * doc/gcc/c++-implementation-defined-behavior.rst: New file. + * doc/gcc/c-implementation-defined-behavior.rst: New file. + * doc/gcc/c-implementation-defined-behavior/architecture.rst: New file. + * doc/gcc/c-implementation-defined-behavior/arrays-and-pointers.rst: New file. + * doc/gcc/c-implementation-defined-behavior/characters.rst: New file. + * doc/gcc/c-implementation-defined-behavior/declarators.rst: New file. + * doc/gcc/c-implementation-defined-behavior/environment.rst: New file. + * doc/gcc/c-implementation-defined-behavior/floating-point.rst: New file. + * doc/gcc/c-implementation-defined-behavior/hints.rst: New file. + * doc/gcc/c-implementation-defined-behavior/identifiers.rst: New file. + * doc/gcc/c-implementation-defined-behavior/integers.rst: New file. + * doc/gcc/c-implementation-defined-behavior/library-functions.rst: New file. + * doc/gcc/c-implementation-defined-behavior/locale-specific-behavior.rst: New file. + * doc/gcc/c-implementation-defined-behavior/preprocessing-directives.rst: New file. + * doc/gcc/c-implementation-defined-behavior/qualifiers.rst: New file. + * doc/gcc/c-implementation-defined-behavior/statements.rst: New file. + * doc/gcc/c-implementation-defined-behavior/structures-unions-enumerations-and-bit-fields.rst: + New file. + * doc/gcc/c-implementation-defined-behavior/translation.rst: New file. + * doc/gcc/conditionally-supported-behavior.rst: New file. + * doc/gcc/conf.py: New file. + * doc/gcc/contributing-to-gcc-development.rst: New file. + * doc/gcc/contributors-to-gcc.rst: New file. + * doc/gcc/copyright.rst: New file. + * doc/gcc/exception-handling.rst: New file. + * doc/gcc/extensions-to-the-c++-language.rst: New file. + * doc/gcc/extensions-to-the-c++-language/backwards-compatibility.rst: New file. + * doc/gcc/extensions-to-the-c++-language/c++-concepts.rst: New file. + * doc/gcc/extensions-to-the-c++-language/c++-interface-and-implementation-pragmas.rst: + New file. + * doc/gcc/extensions-to-the-c++-language/c++-specific-variable-function-and-type-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c++-language/deprecated-features.rst: New file. + * doc/gcc/extensions-to-the-c++-language/extracting-the-function-pointer-from-a-bound-pointer-to-member-function.rst: + New file. + * doc/gcc/extensions-to-the-c++-language/function-multiversioning.rst: New file. + * doc/gcc/extensions-to-the-c++-language/restricting-pointer-aliasing.rst: New file. + * doc/gcc/extensions-to-the-c++-language/type-traits.rst: New file. + * doc/gcc/extensions-to-the-c++-language/vague-linkage.rst: New file. + * doc/gcc/extensions-to-the-c++-language/when-is-a-volatile-c++-object-accessed.rst: + New file. + * doc/gcc/extensions-to-the-c++-language/wheres-the-template.rst: New file. + * doc/gcc/extensions-to-the-c-language-family.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/128-bit-integers.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/additional-floating-types.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/alternate-keywords.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/an-inline-function-is-as-fast-as-a-macro.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/arithmetic-on-void-and-function-pointers.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/arrays-of-length-zero.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/arrays-of-variable-length.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/attribute-syntax.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/binary-constants-using-the-0b-prefix.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/built-in-functions-for-memory-model-aware-atomic-operations.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/built-in-functions-to-perform-arithmetic-with-overflow-checking.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/c++-style-comments.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/case-ranges.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/cast-to-a-union-type.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/complex-numbers.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/compound-literals.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/conditionals-with-omitted-operands.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/constructing-function-calls.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/decimal-floating-types.rst: New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/aarch64-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/amd-gcn-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/arc-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/arm-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/avr-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/blackfin-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/bpf-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/c-sky-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/common-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/epiphany-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/h8-300-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/ia-64-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/m32c-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/m32r-d-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/m68k-function-attributes.rst: + New file. + * doc/gcc/extensions-to-the-c-language-family/declaring-attributes-of-functions/mcore-function-attributes.rst: + New file. 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doc/gccint/target-macros/mode-switching-instructions.rst: New file. + * doc/gccint/target-macros/parameters-for-precompiled-header-validity-checking.rst: + New file. + * doc/gccint/target-macros/position-independent-code.rst: New file. + * doc/gccint/target-macros/register-classes.rst: New file. + * doc/gccint/target-macros/register-usage.rst: New file. + * doc/gccint/target-macros/run-time-target-specification.rst: New file. + * doc/gccint/target-macros/stack-layout-and-calling-conventions.rst: New file. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/basic-stack-layout.rst: + New file. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/caller-saves-register-allocation.rst: + New file. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/eliminating-frame-pointer-and-arg-pointer.rst: + New file. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/exception-handling-support.rst: + New file. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/function-entry-and-exit.rst: + New file. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/generating-code-for-profiling.rst: + New file. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/how-large-values-are-returned.rst: + New file. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/how-scalar-function-values-are-returned.rst: + New file. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/miscellaneous-register-hooks.rst: + New file. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/passing-arguments-in-registers.rst: + New file. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/passing-function-arguments-on-the-stack.rst: + New file. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/permitting-tail-calls.rst: + New file. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/registers-that-address-the-stack-frame.rst: + New file. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/shrink-wrapping-separate-components.rst: + New file. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/specifying-how-stack-checking-is-done.rst: + New file. + * doc/gccint/target-macros/stack-layout-and-calling-conventions/stack-smashing-protection.rst: + New file. + * doc/gccint/target-macros/storage-layout.rst: New file. + * doc/gccint/target-macros/support-for-nested-functions.rst: New file. + * doc/gccint/target-macros/the-global-targetm-variable.rst: New file. + * doc/gccint/target-makefile-fragments.rst: New file. + * doc/gccint/testsuites.rst: New test. + * doc/gccint/testsuites/ada-language-testsuites.rst: New test. + * doc/gccint/testsuites/c-language-testsuites.rst: New test. + * doc/gccint/testsuites/directives-used-within-dejagnu-tests.rst: New test. + * doc/gccint/testsuites/directives-used-within-dejagnu-tests/commands-for-use-in-dg-final.rst: + New test. + * doc/gccint/testsuites/directives-used-within-dejagnu-tests/features-for-dg-add-options.rst: + New test. + * doc/gccint/testsuites/directives-used-within-dejagnu-tests/keywords-describing-target-attributes.rst: + New test. + * doc/gccint/testsuites/directives-used-within-dejagnu-tests/selecting-targets-to-which-a-test-applies.rst: + New test. + * doc/gccint/testsuites/directives-used-within-dejagnu-tests/syntax-and-descriptions-of-test-directives.rst: + New test. + * doc/gccint/testsuites/directives-used-within-dejagnu-tests/variants-of-dg-require-support.rst: + New test. + * doc/gccint/testsuites/idioms-used-in-testsuite-code.rst: New test. + * doc/gccint/testsuites/support-for-testing-binary-compatibility.rst: New test. + * doc/gccint/testsuites/support-for-testing-gcov.rst: New test. + * doc/gccint/testsuites/support-for-testing-gimple-passes.rst: New test. + * doc/gccint/testsuites/support-for-testing-link-time-optimizations.rst: New test. + * doc/gccint/testsuites/support-for-testing-profile-directed-optimizations.rst: New test. + * doc/gccint/testsuites/support-for-testing-rtl-passes.rst: New test. + * doc/gccint/testsuites/support-for-torture-testing-using-multiple-options.rst: New test. + * doc/gccint/the-gcc-low-level-runtime-library.rst: New file. + * doc/gccint/the-gcc-low-level-runtime-library/language-independent-routines-for-exception-handling.rst: + New file. + * doc/gccint/the-gcc-low-level-runtime-library/miscellaneous-runtime-library-routines.rst: + New file. + * doc/gccint/the-gcc-low-level-runtime-library/routines-for-decimal-floating-point-emulation.rst: + New file. + * doc/gccint/the-gcc-low-level-runtime-library/routines-for-fixed-point-fractional-emulation.rst: + New file. + * doc/gccint/the-gcc-low-level-runtime-library/routines-for-floating-point-emulation.rst: + New file. + * doc/gccint/the-gcc-low-level-runtime-library/routines-for-integer-arithmetic.rst: + New file. + * doc/gccint/the-language.rst: New file. + * doc/gccint/user-experience-guidelines.rst: New file. + * doc/install/binaries.rst: New file. + * doc/install/building.rst: New file. + * doc/install/building/building-a-cross-compiler.rst: New file. + * doc/install/building/building-a-native-compiler.rst: New file. + * doc/install/building/building-in-parallel.rst: New file. + * doc/install/building/building-the-ada-compiler.rst: New file. + * doc/install/building/building-the-d-compiler.rst: New file. + * doc/install/building/building-with-profile-feedback.rst: New file. + * doc/install/conf.py: New file. + * doc/install/configuration.rst: New file. + * doc/install/copyright.rst: New file. + * doc/install/downloading-gcc.rst: New file. + * doc/install/final-installation.rst: New file. + * doc/install/gnu-free-documentation-license.rst: New file. + * doc/install/host-target-specific-installation-notes-for-gcc.rst: New file. + * doc/install/how-can-you-run-the-testsuite-on-selected-tests.rst: New test. + * doc/install/how-to-interpret-test-results.rst: New file. + * doc/install/index.rst: New file. + * doc/install/indices-and-tables.rst: New file. + * doc/install/installing-gcc.rst: New file. + * doc/install/passing-options-and-running-multiple-testsuites.rst: New test. + * doc/install/prerequisites.rst: New file. + * doc/install/submitting-test-results.rst: New file. + * doc/install/testing.rst: New file. + +2022-11-09 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (class foperator_minus): New. + (floating_op_table::floating_op_table): Add MINUS_EXPR entry. + +2022-11-09 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (range_operator_float::fold_range): Abstract + out from foperator_plus. + (range_operator_float::rv_fold): New. + (foperator_plus::fold_range): Remove. + (foperator_plus::rv_fold): New. + (propagate_nans): Remove. + * range-op.h (class range_operator_float): Add rv_fold. + +2022-11-09 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (foperator_plus::fold_range): Set NAN for + addition of different signed infinities. + (range_op_float_tests): New test. + +2022-11-09 liuhongt <hongtao.liu@intel.com> + + PR target/107540 + * config/i386/sse.md (avx512f_movddup512<mask_name>): Change + type from sselog to sselog1. + (avx_movddup256<mask_name>): Ditto. + +2022-11-08 David Faust <david.faust@oracle.com> + + * config/bpf/bpf.cc (struct core_walk_data): Add field `which'... + (bpf_resolve_overloaded_builtin): ... set it here. Use values of enum + bpf_builtins for error checks. + (bpf_core_walk): Use values of enum bpf_builtins. + (bpf_core_newdecl): Likewise. + (bpf_expand_builtin): Likewise. + +2022-11-08 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/24021 + * range-op-float.cc (propagate_nans): New. + (frange_nextafter): New. + (frange_arithmetic): New. + (class foperator_plus): New. + (floating_op_table::floating_op_table): Add PLUS_EXPR entry. + +2022-11-08 Aldy Hernandez <aldyh@redhat.com> + + * real.cc (real_isdenormal): New. + (encode_ieee_single): Call real_isdenormal. + (encode_ieee_double): Same. + (encode_ieee_extended): Same. + (encode_ieee_quad): Same. + (encode_ieee_half): Same. + (encode_arm_bfloat_half): Same. + * real.h (real_isdenormal): Add mode argument. Rewrite for + normalized values. + * value-range.cc (frange::flush_denormals_to_zero): Pass mode to + real_isdenormal. + +2022-11-08 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107389 + * gimple-low.cc (lower_builtin_assume_aligned): New. + (lower_stmt): Call it. + +2022-11-08 Aldy Hernandez <aldyh@redhat.com> + + * range-op.cc (operator_div::fold_range): Call + update_known_bitmask. + * tree-ssa-ccp.cc (bit_value_binop): Handle divisions by powers of + 2 as a right shift. + +2022-11-08 Kwok Cheung Yeung <kcy@codesourcery.com> + + * config/gcn/gcn.cc (gcn_expand_builtin_1): Expand first argument + of GCN_BUILTIN_LDEXPV to V64DFmode. + +2022-11-08 Kwok Cheung Yeung <kcy@codesourcery.com> + + * config/gcn/gcn-builtins.def (FABSV, FLOORVF, FLOORV): New builtins. + * config/gcn/gcn.cc (gcn_expand_builtin_1): Expand GCN_BUILTIN_FABSV, + GCN_BUILTIN_FLOORVF and GCN_BUILTIN_FLOORV. + +2022-11-08 Aldy Hernandez <aldyh@redhat.com> + + * range-op.cc (irange_to_masked_value): New. + (update_known_bitmask): New. + (operator_mult::fold_range): Call update_known_bitmask. + +2022-11-08 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/107547 + * tree-call-cdce.cc (get_no_error_domain): Handle CASE_FLT_FN_FLOATN_NX + of BUILT_IN_{ACOS,ASIN,ACOSH,ATANH,LOG,LOG2,LOG10,LOG1P}. Handle + BUILT_IN_{COSH,SINH,EXP,EXPM1,EXP2}F{16,32,64,128}. + +2022-11-08 Jakub Jelinek <jakub@redhat.com> + + PR target/107546 + * config/i386/predicates.md (vector_or_const_vector_operand): New + predicate. + * config/i386/sse.md (vec_cmp<mode><sseintvecmodelower>, + vec_cmpv2div2di, vec_cmpu<mode><sseintvecmodelower>, + vec_cmpuv2div2di): Use nonimmediate_or_const_vector_operand + predicate instead of nonimmediate_operand and + vector_or_const_vector_operand instead of vector_operand. + * config/i386/i386-expand.cc (ix86_expand_int_sse_cmp): For + LE/LEU or GE/GEU with CONST_VECTOR cop1 try to transform those + into LE/LEU or GT/GTU with larger or smaller by one cop1 if + there is no wrap-around. Force CONST_VECTOR cop0 or cop1 into + REG. Formatting fix. + +2022-11-08 Max Filippov <jcmvbkbc@gmail.com> + + PR rtl-optimization/107482 + * ira-color.cc (assign_hard_reg): Only call + update_costs_from_copies when retry_p is false. + +2022-11-08 konglin1 <lingling.kong@intel.com> + + Revert: + 2022-11-07 konglin1 <lingling.kong@intel.com> + + * config/i386/i386.opt:Add -mprefer-remote-atomic. + * config/i386/sync.md (atomic_<plus_logic><mode>): + New define_expand. + (atomic_add<mode>): Rename to below one. + (atomic_add<mode>_1): To this. + (atomic_<logic><mode>): Ditto. + (atomic_<logic><mode>_1): Ditto. + * doc/invoke.texi: Add -mprefer-remote-atomic. + +2022-11-08 Haochen Jiang <haochen.jiang@intel.com> + + * config/i386/i386-options.cc (m_CORE_ATOM): New. + * config/i386/x86-tune.def + (X86_TUNE_SCHEDULE): Initial tune for CORE_ATOM. + (X86_TUNE_PARTIAL_REG_DEPENDENCY): Ditto. + (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY): Ditto. + (X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY): Ditto. + (X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY): Ditto. + (X86_TUNE_DEST_FALSE_DEP_FOR_GLC): Ditto. + (X86_TUNE_MEMORY_MISMATCH_STALL): Ditto. + (X86_TUNE_USE_LEAVE): Ditto. + (X86_TUNE_PUSH_MEMORY): Ditto. + (X86_TUNE_USE_INCDEC): Ditto. + (X86_TUNE_INTEGER_DFMODE_MOVES): Ditto. + (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB): Ditto. + (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES): Ditto. + (X86_TUNE_USE_SAHF): Ditto. + (X86_TUNE_USE_BT): Ditto. + (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI): Ditto. + (X86_TUNE_ONE_IF_CONV_INSN): Ditto. + (X86_TUNE_AVOID_MFENCE): Ditto. + (X86_TUNE_USE_SIMODE_FIOP): Ditto. + (X86_TUNE_EXT_80387_CONSTANTS): Ditto. + (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL): Ditto. + (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Ditto. + (X86_TUNE_SSE_TYPELESS_STORES): Ditto. + (X86_TUNE_SSE_LOAD0_BY_PXOR): Ditto. + (X86_TUNE_AVOID_4BYTE_PREFIXES): Ditto. + (X86_TUNE_USE_GATHER_2PARTS): Ditto. + (X86_TUNE_USE_GATHER_4PARTS): Ditto. + (X86_TUNE_USE_GATHER): Ditto. + +2022-11-08 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/104530 + * gimple-range-cache.cc (ranger_cache::register_inferred_value): + New. Split from: + (ranger_cache::apply_inferred_ranges): Move setting cache to + separate function. + * gimple-range-cache.h (register_inferred_value): New prototype. + * gimple-range-infer.cc (infer_range_manager::has_range_p): New. + * gimple-range-infer.h (has_range_p): New prototype. + * gimple-range.cc (register_transitive_inferred_ranges): New. + * gimple-range.h (register_transitive_inferred_ranges): New proto. + * tree-vrp.cc (rvrp_folder::fold_stmt): Check for transitive inferred + ranges at the end of the block before folding final stmt. + +2022-11-07 David Faust <david.faust@oracle.com> + + * config/bpf/bpf.cc (handle_attr_preserve): Use maybe_make_core_relo(). + +2022-11-07 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/55157 + * range-op.cc (operator_mult::wi_fold): Optimize multiplications + by powers of 2. + +2022-11-07 H.J. Lu <hjl.tools@gmail.com> + + PR middle-end/102566 + * tree-ssa-ccp.cc (optimize_atomic_bit_test_and): Also handle + if (_5 < 0) and if (_5 >= 0). + +2022-11-07 Richard Purdie <richard.purdie@linuxfoundation.org> + + * file-prefix-map.cc (remap_filename): Handle NULL filenames. + +2022-11-07 Alexander Monakov <amonakov@ispras.ru> + + PR tree-optimization/107505 + * tree-ssa-sink.cc (statement_sink_location): Additionally + reject ECF_RETURNS_TWICE calls. + +2022-11-07 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/107541 + * range-op.cc (operator_div::fold_range): Restrict power of 2 + optimization to positive numbers. + +2022-11-07 Richard Biener <rguenther@suse.de> + + * tree-ssa-loop-unswitch.cc (unswitch_predicate::count): New. + (unswitch_predicate::unswitch_predicate): Initialize count. + (init_loop_unswitch_info): First collect candidates and + determine the outermost loop to unswitch. + (tree_ssa_unswitch_loops): First perform all guard hoisting, + then perform unswitching on innermost loop predicates. + (find_unswitching_predicates_for_bb): Keep track of the + most profitable predicate to unswitch on. + (tree_unswitch_single_loop): Unswitch given predicate if + not NULL. + +2022-11-07 Martin Liska <mliska@suse.cz> + Gerald Pfeifer <gerald@pfeifer.com> + + * doc/invoke.texi: Improve wording. + +2022-11-07 Martin Liska <mliska@suse.cz> + + * range-op.cc: Add final override keywords. + +2022-11-07 Kewen Lin <linkw@linux.ibm.com> + + PR tree-optimization/107412 + * gimple-fold.cc (gimple_fold_mask_load_store_mem_ref): Rename to ... + (gimple_fold_partial_load_store_mem_ref): ... this, add one parameter + mask_p indicating it's for mask or length, and add some handlings for + IFN LEN_{LOAD,STORE}. + (gimple_fold_mask_load): Rename to ... + (gimple_fold_partial_load): ... this, add one parameter mask_p. + (gimple_fold_mask_store): Rename to ... + (gimple_fold_partial_store): ... this, add one parameter mask_p. + (gimple_fold_call): Add the handlings for IFN LEN_{LOAD,STORE}, + and adjust calls on gimple_fold_mask_load_store_mem_ref to + gimple_fold_partial_load_store_mem_ref. + +2022-11-07 Hu, Lin1 <lin1.hu@intel.com> + + * common/config/i386/cpuinfo.h + (get_intel_cpu): Handle Grand Ridge. + * common/config/i386/i386-common.cc + (processor_names): Add grandridge. + (processor_alias_table): Ditto. + * common/config/i386/i386-cpuinfo.h: + (enum processor_types): Add INTEL_GRANDRIDGE. + * config.gcc: Add -march=grandridge. + * config/i386/driver-i386.cc (host_detect_local_cpu): + Handle grandridge. + * config/i386/i386-c.cc (ix86_target_macros_internal): + Ditto. + * config/i386/i386-options.cc (m_GRANDRIDGE): New define. + (processor_cost_table): Add grandridge. + * config/i386/i386.h (enum processor_type): + Add PROCESSOR_GRANDRIDGE. + (PTA_GRANDRIDGE): Ditto. + * doc/extend.texi: Add grandridge. + * doc/invoke.texi: Ditto. + +2022-11-07 konglin1 <lingling.kong@intel.com> + + * config/i386/i386.opt:Add -mprefer-remote-atomic. + * config/i386/sync.md (atomic_<plus_logic><mode>): + New define_expand. + (atomic_add<mode>): Rename to below one. + (atomic_add<mode>_1): To this. + (atomic_<logic><mode>): Ditto. + (atomic_<logic><mode>_1): Ditto. + * doc/invoke.texi: Add -mprefer-remote-atomic. + +2022-11-07 konglin1 <lingling.kong@intel.com> + + * common/config/i386/cpuinfo.h (get_available_features): + Detect raoint. + * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_RAOINT_SET, + OPTION_MASK_ISA2_RAOINT_UNSET): New. + (ix86_handle_option): Handle -mraoint. + * common/config/i386/i386-cpuinfo.h (enum processor_features): + Add FEATURE_RAOINT. + * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for + raoint. + * config.gcc: Add raointintrin.h + * config/i386/cpuid.h (bit_RAOINT): New. + * config/i386/i386-builtin.def (BDESC): Add new builtins. + * config/i386/i386-c.cc (ix86_target_macros_internal): Define + __RAOINT__. + * config/i386/i386-isa.def (RAOINT): Add DEF_PTA(RAOINT). + * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): + Add -mraoint. + * config/i386/sync.md (rao_a<raointop><mode>): New define insn. + * config/i386/i386.opt: Add option -mraoint. + * config/i386/x86gprintrin.h: Include raointintrin.h. + * doc/extend.texi: Document raoint. + * doc/invoke.texi: Document -mraoint. + * doc/sourcebuild.texi: Document target raoint. + * config/i386/raointintrin.h: New file. + +2022-11-07 Haochen Jiang <haochen.jiang@intel.com> + + * common/config/i386/cpuinfo.h + (get_intel_cpu): Handle Granite Rapids. + * common/config/i386/i386-common.cc: + (processor_names): Add graniterapids. + (processor_alias_table): Ditto. + * common/config/i386/i386-cpuinfo.h + (enum processor_subtypes): Add INTEL_GRANTIERAPIDS. + * config.gcc: Add -march=graniterapids. + * config/i386/driver-i386.cc (host_detect_local_cpu): + Handle graniterapids. + * config/i386/i386-c.cc (ix86_target_macros_internal): + Ditto. + * config/i386/i386-options.cc (m_GRANITERAPIDS): New. + (processor_cost_table): Add graniterapids. + * config/i386/i386.h (enum processor_type): + Add PROCESSOR_GRANITERAPIDS. + (PTA_GRANITERAPIDS): Ditto. + * doc/extend.texi: Add graniterapids. + * doc/invoke.texi: Ditto. + +2022-11-07 Haochen Jiang <haochen.jiang@intel.com> + Hongtao Liu <hongtao.liu@intel.com> + + * common/config/i386/cpuinfo.h (get_available_features): + Detect PREFETCHI. + * common/config/i386/i386-common.cc + (OPTION_MASK_ISA2_PREFETCHI_SET, + OPTION_MASK_ISA2_PREFETCHI_UNSET): New. + (ix86_handle_option): Handle -mprefetchi. + * common/config/i386/i386-cpuinfo.h + (enum processor_features): Add FEATURE_PREFETCHI. + * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY + for prefetchi. + * config.gcc: Add prfchiintrin.h. + * config/i386/cpuid.h (bit_PREFETCHI): New. + * config/i386/i386-builtin-types.def: + Add DEF_FUNCTION_TYPE (VOID, PCVOID, INT) + and DEF_FUNCTION_TYPE (VOID, PCVOID, INT, INT, INT). + * config/i386/i386-builtin.def (BDESC): Add new builtins. + * config/i386/i386-c.cc (ix86_target_macros_internal): + Define __PREFETCHI__. + * config/i386/i386-expand.cc: Handle new builtins. + * config/i386/i386-isa.def (PREFETCHI): + Add DEF_PTA(PREFETCHI). + * config/i386/i386-options.cc + (ix86_valid_target_attribute_inner_p): Handle prefetchi. + * config/i386/i386.md (prefetchi): New define_insn. + * config/i386/i386.opt: Add option -mprefetchi. + * config/i386/predicates.md (local_func_symbolic_operand): + New predicates. + * config/i386/x86gprintrin.h: Include prfchiintrin.h. + * config/i386/xmmintrin.h (enum _mm_hint): New enum for + prefetchi. + (_mm_prefetch): Handle the highest bit of enum. + * doc/extend.texi: Document prefetchi. + * doc/invoke.texi: Document -mprefetchi. + * doc/sourcebuild.texi: Document target prefetchi. + * config/i386/prfchiintrin.h: New file. + +2022-11-06 Uroš Bizjak <ubizjak@gmail.com> + + * optabs.cc (can_vec_set_var_idx_p): Use operand[2] + mode when checking vec_set_optab. + +2022-11-06 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/loongarch.md (UNSPEC_FCOPYSIGN): New unspec. + (type): Add fcopysign. + (copysign<mode>3): New instruction template. + +2022-11-06 Bernhard Reutner-Fischer <aldot@gcc.gnu.org> + + * multiple_target.cc (expand_target_clones): Free memory. + +2022-11-06 Bernhard Reutner-Fischer <aldot@gcc.gnu.org> + + * cgraph.cc (cgraph_node::make_local): Remove redundant set_section. + * multiple_target.cc (create_dispatcher_calls): Likewise. + +2022-11-05 Jonathan Wakely <jwakely@redhat.com> + + PR c/41041 + * doc/cppopts.texi: Document -fwide-exec-charset defaults + correctly. + +2022-11-05 Alexandre Oliva <oliva@adacore.com> + + * common.opt (fmultiflags): New. + * doc/invoke.texi: Document it. + * gcc.cc (driver_self_specs): Discard it. + * opts.cc (common_handle_option): Ignore it in the driver. + +2022-11-04 Jeff Chapman II <jchapman@lock3software.com> + Jason Merrill <jason@redhat.com> + + * input.cc (get_source_text_between): New fn. + * input.h (get_source_text_between): Declare. + +2022-11-04 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/107342 + * range-op.cc (operator_mult::fold_range): New. + (operator_div::fold_range): New. + +2022-11-04 Eric Botcazou <ebotcazou@adacore.com> + + * fold-const.cc (operand_compare::operand_equal_p) <COMPONENT_REF>: + Do not take into account operand 2. + (operand_compare::hash_operand) <COMPONENT_REF>: Likewise. + +2022-11-04 Eric Botcazou <ebotcazou@adacore.com> + + * expr.cc (emit_group_store): Do not use subword paradoxical subregs + +2022-11-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/aarch64-sve2.md: Fix typo in Cryptographic + extensions comment. + +2022-11-04 Thomas Schwinge <thomas@codesourcery.com> + + * config.gcc [target *-intelmic-* | *-intelmicemul-*]: Remove. + * config/i386/i386-options.cc (ix86_omp_device_kind_arch_isa) + [ACCEL_COMPILER]: Remove. + * config/i386/intelmic-mkoffload.cc: Remove. + * config/i386/intelmic-offload.h: Likewise. + * config/i386/t-intelmic: Likewise. + * config/i386/t-omp-device: Likewise. + * configure.ac [target *-intelmic-* | *-intelmicemul-*]: Remove. + * configure: Regenerate. + * doc/install.texi (--enable-offload-targets=[...]): Update. + * doc/sourcebuild.texi: Remove 'liboffloadmic' documentation. + +2022-11-04 Thomas Schwinge <thomas@codesourcery.com> + + * Makefile.in (OBJS): Remove 'dbxout.o'. + * config/nvptx/nvptx.cc: Don't '#include "dbxout.h"'. + * dbxout.cc: Remove. + * dbxout.h: Likewise. + * target-def.h (TARGET_ASM_CONSTRUCTOR, TARGET_ASM_DESTRUCTOR): + Default to 'default_asm_out_constructor', + 'default_asm_out_destructor'. + * targhooks.cc (default_asm_out_constructor) + (default_asm_out_destructor): New. + * targhooks.h (default_asm_out_constructor) + (default_asm_out_destructor): Declare. + +2022-11-04 Thomas Schwinge <thomas@codesourcery.com> + + * Makefile.in (OBJS): Add 'dbxout.o'. + * config/nvptx/nvptx.cc: '#include "dbxout.h"'. + * dbxout.cc: New. + * dbxout.h: Likewise. + * target-def.h (TARGET_ASM_CONSTRUCTOR, TARGET_ASM_DESTRUCTOR): + Default to 'default_stabs_asm_out_constructor', + 'default_stabs_asm_out_destructor'. + +2022-11-04 Hongyu Wang <hongyu.wang@intel.com> + Haochen Jiang <haochen.jiang@intel.com> + + * common/config/i386/cpuinfo.h (get_available_features): Detect + amx-fp16. + * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_FP16_SET, + OPTION_MASK_ISA2_AMX_FP16_UNSET): New macros. + (ix86_handle_option): Handle -mamx-fp16. + * common/config/i386/i386-cpuinfo.h (enum processor_features): + Add FEATURE_AMX_FP16. + * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for + amx-fp16. + * config.gcc: Add amxfp16intrin.h. + * config/i386/cpuid.h (bit_AMX_FP16): New. + * config/i386/i386-c.cc (ix86_target_macros_internal): Define + __AMX_FP16__. + * config/i386/i386-isa.def: Add DEF_PTA for AMX_FP16. + * config/i386/i386-options.cc (isa2_opts): Add -mamx-fp16. + (ix86_valid_target_attribute_inner_p): Add new ATTR. + (ix86_option_override_internal): Handle AMX-FP16. + * config/i386/i386.opt: Add -mamx-fp16. + * config/i386/immintrin.h: Include amxfp16intrin.h. + * doc/extend.texi: Document -mamx-fp16. + * doc/invoke.texi: Document amx-fp16. + * doc/sourcebuild.texi: Document amx_fp16. + * config/i386/amxfp16intrin.h: New file. + +2022-11-04 Haochen Jiang <haochen.jiang@intel.com> + + * common/config/i386/cpuinfo.h (get_intel_cpu): + Add Sierra Forest. + * common/config/i386/i386-common.cc + (processor_names): Add Sierra Forest. + (processor_alias_table): Ditto. + * common/config/i386/i386-cpuinfo.h + (enum processor_types): Add INTEL_SIERRAFOREST. + * config.gcc: Add -march=sierraforest. + * config/i386/driver-i386.cc (host_detect_local_cpu): + Handle Sierra Forest. + * config/i386/i386-c.cc (ix86_target_macros_internal): + Ditto. + * config/i386/i386-options.cc (m_SIERRAFOREST): New define. + (processor_cost_table): Add sierra forest. + * config/i386/i386.h (enum processor_type): + Add PROCESSOR_SIERRA_FOREST. + (PTA_SIERRAFOREST): Ditto. + * doc/extend.texi: Add sierra forest. + * doc/invoke.texi: Ditto. + +2022-11-04 Haochen Jiang <haochen.jiang@intel.com> + + * common/config/i386/cpuinfo.h (get_available_features): + Detect cmpccxadd. + * common/config/i386/i386-common.cc + (OPTION_MASK_ISA2_CMPCCXADD_SET, + OPTION_MASK_ISA2_CMPCCXADD_UNSET): New. + (ix86_handle_option): Handle -mcmpccxadd. + * common/config/i386/i386-cpuinfo.h (enum processor_features): + Add FEATURE_CMPCCXADD. + * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for + cmpccxadd. + * config.gcc: Add cmpccxaddintrin.h. + * config/i386/cpuid.h (bit_CMPCCXADD): New. + * config/i386/i386-builtin-types.def: + Add DEF_FUNCTION_TYPE(INT, PINT, INT, INT, INT) + and DEF_FUNCTION_TYPE(LONGLONG, PLONGLONG, LONGLONG, LONGLONG, INT). + * config/i386/i386-builtin.def (BDESC): Add new builtins. + * config/i386/i386-c.cc (ix86_target_macros_internal): Define + __CMPCCXADD__. + * config/i386/i386-expand.cc (ix86_expand_special_args_builtin): + Add new parameter to indicate constant position. + Handle INT_FTYPE_PINT_INT_INT_INT + and LONGLONG_FTYPE_PLONGLONG_LONGLONG_LONGLONG_INT. + * config/i386/i386-isa.def (CMPCCXADD): Add DEF_PTA(CMPCCXADD). + * config/i386/i386-options.cc (isa2_opts): Add -mcmpccxadd. + (ix86_valid_target_attribute_inner_p): Handle cmpccxadd. + * config/i386/i386.opt: Add option -mcmpccxadd. + * config/i386/sync.md (cmpccxadd_<mode>): New define insn. + * config/i386/x86gprintrin.h: Include cmpccxaddintrin.h. + * doc/extend.texi: Document cmpccxadd. + * doc/invoke.texi: Document -mcmpccxadd. + * doc/sourcebuild.texi: Document target cmpccxadd. + * config/i386/cmpccxaddintrin.h: New file. + +2022-11-03 Jason Merrill <jason@redhat.com> + + * doc/invoke.texi: -fconcepts no longer implies + -fconcepts-ts before C++20. + +2022-11-03 Kwok Cheung Yeung <kcy@codesourcery.com> + + * config/gcn/gcn-valu.md (math_unop_insn): New attribute. + (<math_unop><mode>2, <math_unop><mode>2<exec>, <math_unop><mode>2, + <math_unop><mode>2<exec>, *<math_unop><mode>2_insn, + *<math_unop><mode>2<exec>_insn): Use math_unop_insn to generate + assembler output. + +2022-11-03 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range.cc (gimple_ranger::update_stmt): New. + * gimple-range.h (gimple_ranger::update_stmt): New prototype. + * tree-ssa-operands.cc (update_stmt_operands): Notify range + query that stmt has changed. + * value-query.h (range_query::update_stmt): New. + +2022-11-03 David Malcolm <dmalcolm@redhat.com> + + * make-unique.h: New file. + +2022-11-03 Uroš Bizjak <ubizjak@gmail.com> + + PR target/107404 + * config/i386/i386.md (eliminate reg-reg move by inverting the + condition of a cmove #2 peephole2): Check if eliminated move + initialized a register, used in the moved instruction. + +2022-11-03 Andrew Stubbs <ams@codesourcery.com> + + PR target/107510 + * config/gcn/gcn.cc (gcn_expand_reduc_scalar): Remove duplicate + UNSPEC_SMIN_DPP_SHR conditionals. + +2022-11-02 Christoph Müllner <christoph.muellner@vrull.eu> + + * common/config/riscv/riscv-common.cc: Add zawrs extension. + * config/riscv/riscv-opts.h (MASK_ZAWRS): New. + (TARGET_ZAWRS): New. + * config/riscv/riscv.opt: New. + +2022-11-02 Rasmus Villemoes <rv@rasmusvillemoes.dk> + + PR driver/93371 + * gcc.cc (ASM_MAP): Honour -ffile-prefix-map. + +2022-11-02 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (frange::contains_p): Fix signed zero handling. + (range_tests_signed_zeros): New test. + +2022-11-02 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + + * builtins.cc (mathfn_built_in_2): #undef HUGE_VAL, NAN. + +2022-11-02 Xionghu Luo <xionghuluo@tencent.com> + + PR target/100866 + * config/rs6000/altivec.md: (*altivec_vrl<VI_char>): Named to... + (altivec_vrl<VI_char>): ...this. + * config/rs6000/vsx.md (revb_<mode>): Call vspltish and vrlh when + target is Power8 and mode is V8HI. + +2022-11-01 David Seifert <soap@gentoo.org> + + * configure.ac: Add AC_CACHE_CHECK(..., gcc_cv_sys_sdt_h). + * configure: Regenerate. + +2022-11-01 Richard Purdie <richard.purdie@linuxfoundation.org> + + * file-prefix-map.cc (remap_filename): Allow remapping of relative paths. + +2022-11-01 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/107490 + * range-op-float.cc (foperator_unordered_lt::op1_range): Handle + NANs. + (foperator_unordered_lt::op2_range): Same. + (foperator_unordered_le::op1_range): Same. + (foperator_unordered_le::op2_range): Same. + (foperator_unordered_gt::op1_range): Same. + (foperator_unordered_gt::op2_range): Same. + (foperator_unordered_ge::op1_range): Same. + (foperator_unordered_ge::op2_range): Same. + +2022-11-01 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/107497 + * tree-vrp.cc (remove_unreachable::remove_and_update_globals): + Check that ssa-name still exists before accessing it. + +2022-11-01 Andrew MacLeod <amacleod@redhat.com> + + * params.opt (param_vrp1_mode): Make ranger default. + +2022-11-01 Andrew MacLeod <amacleod@redhat.com> + + * tree-vrp.cc (class remove_unreachable): New. + (remove_unreachable::maybe_register_block): New. + (remove_unreachable::remove_and_update_globals): New. + (rvrp_folder::rvrp_folder): Initialize m_unreachable. + (rvrp_folder::post_fold_bb): Maybe register unreachable block. + (rvrp_folder::m_unreachable): New member. + (execute_ranger_vrp): Add final_pass flag, remove unreachables. + +2022-11-01 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-cache.cc (ranger_cache::fill_block_cache): Allow + exit block to be specified. + (ranger_cache::range_from_dom): If exit block is specified, use + the immediate predecessor instead of the dominator to start. + * gimple-range.cc (gimple_ranger::range_on_exit): Allow query + for exit block. + +2022-11-01 Andrew MacLeod <amacleod@redhat.com> + + * value-range.cc (irange::intersect_nonzero_bits): If new + non-zero mask is the same as original, flag no change. + +2022-11-01 Alexander Monakov <amonakov@ispras.ru> + + PR target/87832 + * config/i386/znver.md (znver1_idiv): New automaton. + (znver1-idiv): New unit. + (znver1_idiv_DI): Correct unit and cycles in the reservation. + (znver1_idiv_SI): Ditto. + (znver1_idiv_HI): Ditto. + (znver1_idiv_QI): Ditto. + (znver1_idiv_mem_DI): Ditto. + (znver1_idiv_mem_SI): Ditto. + (znver1_idiv_mem_HI): Ditto. + (znver1_idiv_mem_QI): Ditto. + (znver3_idiv_DI): Ditto. + (znver3_idiv_SI): Ditto. + (znver3_idiv_HI): Ditto. + (znver3_idiv_QI): Ditto. + (znver3_idiv_mem_DI): Ditto. + (znver3_idiv_mem_SI): Ditto. + (znver3_idiv_mem_HI): Ditto. + (znver3_idiv_mem_QI): Ditto. + +2022-11-01 liuhongt <hongtao.liu@intel.com> + + PR target/107057 + * config/i386/sse.md (*vec_interleave_highv2df): Remove + constraint 1. + (*vec_interleave_lowv2df): Ditto. + (vec_concatv2df): Ditto. + (*avx512f_unpcklpd512<mask_name>): Ditto and renamed to .. + (avx512f_unpcklpd512<mask_name>): .. this. + (avx512f_movddup512<mask_name>): Change to define_insn. + (avx_movddup256<mask_name>): Ditto. + (*avx_unpcklpd256<mask_name>): Remove constraint 1 and renamed + to .. + (avx_unpcklpd256<mask_name>): .. this. + * config/i386/i386.cc (ix86_vec_interleave_v2df_operator_ok): + Disallow MEM_P (op1) && MEM_P (op2). + +2022-11-01 liuhongt <hongtao.liu@intel.com> + + PR target/55583 + * config/i386/i386.md (*x86_64_shld_1): Rename to .. + (x86_64_shld_1): .. this. + (*x86_shld_1): Rename to .. + (x86_shld_1): .. this. + (*x86_64_shrd_1): Rename to .. + (x86_64_shrd_1): .. this. + (*x86_shrd_1): Rename to .. + (x86_shrd_1): .. this. + (*x86_64_shld_shrd_1_nozext): New pre_reload splitter. + (*x86_shld_shrd_1_nozext): Ditto. + (*x86_64_shrd_shld_1_nozext): Ditto. + (*x86_shrd_shld_1_nozext): Ditto. + +2022-11-01 Cui,Lili <lili.cui@intel.com> + + * ipa-inline-analysis.cc (do_estimate_edge_time): Add function attribute + judgement for INLINE_HINT_known_hot hint. + +2022-10-31 Guillermo E. Martinez <guillermo.e.martinez@oracle.com> + + * btfout.cc (btf_calc_num_vbytes): Compute enumeration size depending of + enumerator type btf_enum{,64}. + (btf_asm_type): Update btf_kflag according to enumeration type sign + using dtd_enum_unsigned field for both: BTF_KIND_ENUM{,64}. + (btf_asm_enum_const): New argument to represent the size of + the BTF enum type, writing the enumerator constant value for + 32 bits, if it's 64 bits then explicitly writes lower 32-bits + value and higher 32-bits value. + (output_asm_btf_enum_list): Add enumeration size argument. + * ctfc.cc (ctf_add_enum): New argument to represent CTF enum + basic information. + (ctf_add_generic): Use of ei_{name. size, unsigned} to build the + dtd structure containing enumeration information. + (ctf_add_enumerator): Update comment mention support for BTF + enumeration in 64-bits. + * dwarf2ctf.cc (gen_ctf_enumeration_type): Extract signedness + for enumeration type and use it in ctf_add_enum. + * ctfc.h (ctf_dmdef): Update dmd_value to HOST_WIDE_INT to allow + use 32/64 bits enumerators. + information. + (ctf_dtdef): New field to describe enum signedness. + +2022-10-31 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-vector-builtins-bases.cc: Change constexpr back to CONSTEXPR. + * config/riscv/riscv-vector-builtins-shapes.cc (SHAPE): Ditto. + * config/riscv/riscv-vector-builtins.cc (struct registered_function_hasher): Ditto. + * config/riscv/riscv-vector-builtins.h (struct rvv_arg_type_info): Ditto. + +2022-10-31 Andrew Stubbs <ams@codesourcery.com> + + * config/gcn/gcn-valu.md (fminmaxop): New iterator. + (<fexpander><mode>3): New define_expand. + (<fexpander><mode>3<exec>): Likewise. + (reduc_<fexpander>_scal_<mode>): Likewise. + * config/gcn/gcn.md (fexpander): New attribute. + +2022-10-31 Andrew Stubbs <ams@codesourcery.com> + + * config/gcn/gcn-valu.md (V64_SI): Delete iterator. + (V64_DI): Likewise. + (V64_1REG): Likewise. + (V64_INT_1REG): Likewise. + (V64_2REG): Likewise. + (V64_ALL): Likewise. + (V64_FP): Likewise. + (reduc_<reduc_op>_scal_<mode>): Use V_ALL. Use gen_vec_extract. + (fold_left_plus_<mode>): Use V_FP. + (*<reduc_op>_dpp_shr_<mode>): Use V_1REG. + (*<reduc_op>_dpp_shr_<mode>): Use V_DI. + (*plus_carry_dpp_shr_<mode>): Use V_INT_1REG. + (*plus_carry_in_dpp_shr_<mode>): Use V_SI. + (*plus_carry_dpp_shr_<mode>): Use V_DI. + (mov_from_lane63_<mode>): Delete. + (mov_from_lane63_<mode>): Delete. + * config/gcn/gcn.cc (gcn_expand_reduc_scalar): Support partial vectors. + * config/gcn/gcn.md (unspec): Remove UNSPEC_MOV_FROM_LANE63. + +2022-10-31 Andrew Stubbs <ams@codesourcery.com> + + * config/gcn/gcn.cc (gcn_simd_clone_compute_vecsize_and_simdlen): + Set base_type as ARG_UNUSED. + +2022-10-31 Jakub Jelinek <jakub@redhat.com> + + * builtin-types.def (BT_COMPLEX_FLOAT16, BT_COMPLEX_FLOAT32, + BT_COMPLEX_FLOAT64, BT_COMPLEX_FLOAT128, BT_COMPLEX_FLOAT32X, + BT_COMPLEX_FLOAT64X, BT_COMPLEX_FLOAT128X, + BT_FN_COMPLEX_FLOAT16_COMPLEX_FLOAT16, + BT_FN_COMPLEX_FLOAT32_COMPLEX_FLOAT32, + BT_FN_COMPLEX_FLOAT64_COMPLEX_FLOAT64, + BT_FN_COMPLEX_FLOAT128_COMPLEX_FLOAT128, + BT_FN_COMPLEX_FLOAT32X_COMPLEX_FLOAT32X, + BT_FN_COMPLEX_FLOAT64X_COMPLEX_FLOAT64X, + BT_FN_COMPLEX_FLOAT128X_COMPLEX_FLOAT128X, + BT_FN_FLOAT16_COMPLEX_FLOAT16, BT_FN_FLOAT32_COMPLEX_FLOAT32, + BT_FN_FLOAT64_COMPLEX_FLOAT64, BT_FN_FLOAT128_COMPLEX_FLOAT128, + BT_FN_FLOAT32X_COMPLEX_FLOAT32X, BT_FN_FLOAT64X_COMPLEX_FLOAT64X, + BT_FN_FLOAT128X_COMPLEX_FLOAT128X, + BT_FN_COMPLEX_FLOAT16_COMPLEX_FLOAT16_COMPLEX_FLOAT16, + BT_FN_COMPLEX_FLOAT32_COMPLEX_FLOAT32_COMPLEX_FLOAT32, + BT_FN_COMPLEX_FLOAT64_COMPLEX_FLOAT64_COMPLEX_FLOAT64, + BT_FN_COMPLEX_FLOAT128_COMPLEX_FLOAT128_COMPLEX_FLOAT128, + BT_FN_COMPLEX_FLOAT32X_COMPLEX_FLOAT32X_COMPLEX_FLOAT32X, + BT_FN_COMPLEX_FLOAT64X_COMPLEX_FLOAT64X_COMPLEX_FLOAT64X, + BT_FN_COMPLEX_FLOAT128X_COMPLEX_FLOAT128X_COMPLEX_FLOAT128X): New. + * builtins.def (CABS_TYPE, CACOSH_TYPE, CARG_TYPE, CASINH_TYPE, + CPOW_TYPE, CPROJ_TYPE): Define and undefine later. + (BUILT_IN_CABS, BUILT_IN_CACOSH, BUILT_IN_CACOS, BUILT_IN_CARG, + BUILT_IN_CASINH, BUILT_IN_CASIN, BUILT_IN_CATANH, BUILT_IN_CATAN, + BUILT_IN_CCOSH, BUILT_IN_CCOS, BUILT_IN_CEXP, BUILT_IN_CLOG, + BUILT_IN_CPOW, BUILT_IN_CPROJ, BUILT_IN_CSINH, BUILT_IN_CSIN, + BUILT_IN_CSQRT, BUILT_IN_CTANH, BUILT_IN_CTAN): Add + DEF_EXT_LIB_FLOATN_NX_BUILTINS. + * fold-const-call.cc (fold_const_call_sc, fold_const_call_cc, + fold_const_call_ccc): Add various CASE_CFN_*_FN: cases when + CASE_CFN_* is present. + * gimple-ssa-backprop.cc (backprop::process_builtin_call_use): + Likewise. + * builtins.cc (expand_builtin, fold_builtin_1): Likewise. + * fold-const.cc (negate_mathfn_p, tree_expr_finite_p, + tree_expr_maybe_signaling_nan_p, tree_expr_maybe_nan_p, + tree_expr_maybe_real_minus_zero_p, tree_call_nonnegative_warnv_p): + Likewise. + +2022-10-31 Jakub Jelinek <jakub@redhat.com> + + * builtin-types.def (BT_FN_BFLOAT16_BFLOAT16_BFLOAT16): New. + * builtins.def (BUILT_IN_NEXTAFTERF16B): New builtin. + * fold-const-call.cc (fold_const_call_sss): Handle + CFN_BUILT_IN_NEXTAFTERF16B. + +2022-10-31 Jakub Jelinek <jakub@redhat.com> + + * builtin-types.def (BT_FLOAT16_PTR, BT_FLOAT32_PTR, BT_FLOAT64_PTR, + BT_FLOAT128_PTR, BT_FLOAT32X_PTR, BT_FLOAT64X_PTR, BT_FLOAT128X_PTR): + New DEF_PRIMITIVE_TYPE. + (BT_FN_INT_FLOAT16, BT_FN_INT_FLOAT32, BT_FN_INT_FLOAT64, + BT_FN_INT_FLOAT128, BT_FN_INT_FLOAT32X, BT_FN_INT_FLOAT64X, + BT_FN_INT_FLOAT128X, BT_FN_LONG_FLOAT16, BT_FN_LONG_FLOAT32, + BT_FN_LONG_FLOAT64, BT_FN_LONG_FLOAT128, BT_FN_LONG_FLOAT32X, + BT_FN_LONG_FLOAT64X, BT_FN_LONG_FLOAT128X, BT_FN_LONGLONG_FLOAT16, + BT_FN_LONGLONG_FLOAT32, BT_FN_LONGLONG_FLOAT64, + BT_FN_LONGLONG_FLOAT128, BT_FN_LONGLONG_FLOAT32X, + BT_FN_LONGLONG_FLOAT64X, BT_FN_LONGLONG_FLOAT128X): New + DEF_FUNCTION_TYPE_1. + (BT_FN_FLOAT16_FLOAT16_FLOAT16PTR, BT_FN_FLOAT32_FLOAT32_FLOAT32PTR, + BT_FN_FLOAT64_FLOAT64_FLOAT64PTR, BT_FN_FLOAT128_FLOAT128_FLOAT128PTR, + BT_FN_FLOAT32X_FLOAT32X_FLOAT32XPTR, + BT_FN_FLOAT64X_FLOAT64X_FLOAT64XPTR, + BT_FN_FLOAT128X_FLOAT128X_FLOAT128XPTR, BT_FN_FLOAT16_FLOAT16_INT, + BT_FN_FLOAT32_FLOAT32_INT, BT_FN_FLOAT64_FLOAT64_INT, + BT_FN_FLOAT128_FLOAT128_INT, BT_FN_FLOAT32X_FLOAT32X_INT, + BT_FN_FLOAT64X_FLOAT64X_INT, BT_FN_FLOAT128X_FLOAT128X_INT, + BT_FN_FLOAT16_FLOAT16_INTPTR, BT_FN_FLOAT32_FLOAT32_INTPTR, + BT_FN_FLOAT64_FLOAT64_INTPTR, BT_FN_FLOAT128_FLOAT128_INTPTR, + BT_FN_FLOAT32X_FLOAT32X_INTPTR, BT_FN_FLOAT64X_FLOAT64X_INTPTR, + BT_FN_FLOAT128X_FLOAT128X_INTPTR, BT_FN_FLOAT16_FLOAT16_LONG, + BT_FN_FLOAT32_FLOAT32_LONG, BT_FN_FLOAT64_FLOAT64_LONG, + BT_FN_FLOAT128_FLOAT128_LONG, BT_FN_FLOAT32X_FLOAT32X_LONG, + BT_FN_FLOAT64X_FLOAT64X_LONG, BT_FN_FLOAT128X_FLOAT128X_LONG): New + DEF_FUNCTION_TYPE_2. + (BT_FN_FLOAT16_FLOAT16_FLOAT16_INTPTR, + BT_FN_FLOAT32_FLOAT32_FLOAT32_INTPTR, + BT_FN_FLOAT64_FLOAT64_FLOAT64_INTPTR, + BT_FN_FLOAT128_FLOAT128_FLOAT128_INTPTR, + BT_FN_FLOAT32X_FLOAT32X_FLOAT32X_INTPTR, + BT_FN_FLOAT64X_FLOAT64X_FLOAT64X_INTPTR, + BT_FN_FLOAT128X_FLOAT128X_FLOAT128X_INTPTR): New DEF_FUNCTION_TYPE_3. + * builtins.def (ACOSH_TYPE, ATAN2_TYPE, ATANH_TYPE, COSH_TYPE, + FDIM_TYPE, HUGE_VAL_TYPE, HYPOT_TYPE, ILOGB_TYPE, LDEXP_TYPE, + LGAMMA_TYPE, LLRINT_TYPE, LOG10_TYPE, LRINT_TYPE, MODF_TYPE, + NEXTAFTER_TYPE, REMQUO_TYPE, SCALBLN_TYPE, SCALBN_TYPE, SINH_TYPE): + Define and undefine later. + (FMIN_TYPE, SQRT_TYPE): Undefine at a later line. + (INF_TYPE): Define at a later line. + (BUILT_IN_ACOSH, BUILT_IN_ACOS, BUILT_IN_ASINH, BUILT_IN_ASIN, + BUILT_IN_ATAN2, BUILT_IN_ATANH, BUILT_IN_ATAN, BUILT_IN_CBRT, + BUILT_IN_COSH, BUILT_IN_COS, BUILT_IN_ERFC, BUILT_IN_ERF, + BUILT_IN_EXP2, BUILT_IN_EXP, BUILT_IN_EXPM1, BUILT_IN_FDIM, + BUILT_IN_FMOD, BUILT_IN_FREXP, BUILT_IN_HYPOT, BUILT_IN_ILOGB, + BUILT_IN_LDEXP, BUILT_IN_LGAMMA, BUILT_IN_LLRINT, BUILT_IN_LLROUND, + BUILT_IN_LOG10, BUILT_IN_LOG1P, BUILT_IN_LOG2, BUILT_IN_LOGB, + BUILT_IN_LOG, BUILT_IN_LRINT, BUILT_IN_LROUND, BUILT_IN_MODF, + BUILT_IN_NEXTAFTER, BUILT_IN_POW, BUILT_IN_REMAINDER, BUILT_IN_REMQUO, + BUILT_IN_SCALBLN, BUILT_IN_SCALBN, BUILT_IN_SINH, BUILT_IN_SIN, + BUILT_IN_TANH, BUILT_IN_TAN, BUILT_IN_TGAMMA): Add + DEF_EXT_LIB_FLOATN_NX_BUILTINS. + (BUILT_IN_HUGE_VAL): Use HUGE_VAL_TYPE instead of INF_TYPE in + DEF_GCC_FLOATN_NX_BUILTINS. + * fold-const-call.cc (fold_const_call_ss): Add various CASE_CFN_*_FN: + cases when CASE_CFN_* is present. + (fold_const_call_sss): Likewise. + * builtins.cc (mathfn_built_in_2): Use CASE_MATHFN_FLOATN instead of + CASE_MATHFN for various builtins in SEQ_OF_CASE_MATHFN macro. + (builtin_with_linkage_p): Add CASE_FLT_FN_FLOATN_NX for various + builtins next to CASE_FLT_FN. + * fold-const.cc (tree_call_nonnegative_warnv_p): Add CASE_CFN_*_FN: + next to CASE_CFN_*: for various builtins. + * tree-call-cdce.cc (can_test_argument_range): Add + CASE_FLT_FN_FLOATN_NX next to CASE_FLT_FN for various builtins. + (edom_only_function): Likewise. + +2022-10-31 konglin1 <lingling.kong@intel.com> + + * common/config/i386/i386-common.cc + (OPTION_MASK_ISA2_AVXNECONVERT_SET, + OPTION_MASK_ISA2_AVXNECONVERT_UNSET): New. + (ix86_handle_option): Handle -mavxneconvert, unset + avxneconvert when avx2 is disabled. + * common/config/i386/i386-cpuinfo.h (processor_types): Add + FEATURE_AVXNECONVERT. + * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for + avxneconvert. + * common/config/i386/cpuinfo.h (get_available_features): + Detect avxneconvert. + * config.gcc: Add avxneconvertintrin.h + * config/i386/avxneconvertintrin.h: New. + * config/i386/avx512bf16vlintrin.h (_mm256_cvtneps_pbh): + Unified builtin with avxneconvert. + (_mm_cvtneps_pbh): Ditto. + * config/i386/cpuid.h (bit_AVXNECONVERT): New. + * config/i386/i386-builtin-types.def: Add + DEF_POINTER_TYPE (PCV8HF, V8HF, CONST), + DEF_POINTER_TYPE (PCV8BF, V8BF, CONST), + DEF_POINTER_TYPE (PCV16HF, V16HF, CONST), + DEF_POINTER_TYPE (PCV16BF, V16BF, CONST), + DEF_FUNCTION_TYPE (V4SF, PCBFLOAT16), + DEF_FUNCTION_TYPE (V4SF, PCFLOAT16), + DEF_FUNCTION_TYPE (V8SF, PCBFLOAT16), + DEF_FUNCTION_TYPE (V8SF, PCFLOAT16), + DEF_FUNCTION_TYPE (V4SF, PCV8BF), + DEF_FUNCTION_TYPE (V4SF, PCV8HF), + DEF_FUNCTION_TYPE (V8SF, PCV16HF), + DEF_FUNCTION_TYPE (V8SF, PCV16BF), + * config/i386/i386-builtin.def: Add new builtins. + * config/i386/i386-c.cc (ix86_target_macros_internal): Define + __AVXNECONVERT__. + * config/i386/i386-expand.cc (ix86_expand_special_args_builtin): + Handle V4SF_FTYPE_PCBFLOAT16,V8SF_FTYPE_PCBFLOAT16, V4SF_FTYPE_PCFLOAT16, + V8SF_FTYPE_PCFLOAT16,V4SF_FTYPE_PCV8BF, + V4SF_FTYPE_PCV8HF,V8SF_FTYPE_PCV16BF,V8SF_FTYPE_PCV16HF. + * config/i386/i386-isa.def : Add DEF_PTA(AVXNECONVERT) New. + * config/i386/i386-options.cc (isa2_opts): Add -mavxneconvert. + (ix86_valid_target_attribute_inner_p): Handle avxneconvert. + * config/i386/i386.md: Add attr avx512bf16vl and avxneconvert. + * config/i386/i386.opt: Add option -mavxneconvert. + * config/i386/immintrin.h: Inculde avxneconvertintrin.h. + * config/i386/sse.md (vbcstnebf162ps_<mode>): New define_insn. + (vbcstnesh2ps_<mode>): Ditto. + (vcvtnee<bf16_ph>2ps_<mode>):Ditto. + (vcvtneo<bf16_ph>2ps_<mode>):Ditto. + (vcvtneps2bf16_v4sf): Ditto. + (*vcvtneps2bf16_v4sf): Ditto. + (vcvtneps2bf16_v8sf): Ditto. + * doc/invoke.texi: Document -mavxneconvert. + * doc/extend.texi: Document avxneconvert. + * doc/sourcebuild.texi: Document target avxneconvert. + +2022-10-31 konglin1 <lingling.kong@intel.com> + + * config/i386/avx512bf16intrin.h (__attribute__): Change short to bf16. + (_mm_cvtsbh_ss): Ditto. + (_mm512_cvtne2ps_pbh): Ditto. + (_mm512_mask_cvtne2ps_pbh): Ditto. + (_mm512_maskz_cvtne2ps_pbh): Ditto. + * config/i386/avx512bf16vlintrin.h (__attribute__): Ditto. + (_mm256_cvtne2ps_pbh): Ditto. + (_mm256_mask_cvtne2ps_pbh): Ditto. + (_mm256_maskz_cvtne2ps_pbh): Ditto. + (_mm_cvtne2ps_pbh): Ditto. + (_mm_mask_cvtne2ps_pbh): Ditto. + (_mm_maskz_cvtne2ps_pbh): Ditto. + (_mm_cvtness_sbh): Ditto. + * config/i386/i386-builtin-types.def (V8BF): Add new + DEF_VECTOR_TYPE for BFmode. + (V16BF): Ditto. + (V32BF): Ditto. + * config/i386/i386-builtin.def (BDESC): Fixed builtins. + * config/i386/i386-expand.cc (ix86_expand_args_builtin): Changed + avx512bf16 ix86_builtin_func_type included HI to BF. + * config/i386/immintrin.h: Add SSE2 depend for avx512bf16. + * config/i386/sse.md (TARGET_AVX512VL): Changed HI vector to BF + vector. + (avx512f_cvtneps2bf16_v4sf): New define_expand. + (*avx512f_cvtneps2bf16_v4sf): New define_insn. + (avx512f_cvtneps2bf16_v4sf_maskz):Ditto. + (avx512f_cvtneps2bf16_v4sf_mask): Ditto. + (avx512f_cvtneps2bf16_v4sf_mask_1): Ditto. + +2022-10-31 liuhongt <hongtao.liu@intel.com> + + PR target/107261 + * config/i386/i386-modes.def (VECTOR_MODE): Support V2BFmode. + * config/i386/i386.cc (classify_argument): Handle V4BFmode and + V2BFmode. + (ix86_convert_const_vector_to_integer): Ditto. + * config/i386/i386.h (VALID_AVX512FP16_REG_MODE): Remove + V2BFmode. + (VALID_SSE2_REG_MODE): Add V4BFmode and V2BFmode. + (VALID_MMX_REG_MODE): Add V4BFmode. + * config/i386/i386.md (mode): Add V4BF and V2BF. + (MODE_SIZE): Ditto. + * config/i386/mmx.md (MMXMODE) Add V4BF. + (V_32): Add V2BF. + (V_16_32_64): Add V4BF and V2BF. + (mmxinsnmode): Add V4BF and V2BF. + (*mov<mode>_internal): Hanlde V4BFmode and V2BFmode. + +2022-10-29 Eric Botcazou <ebotcazou@adacore.com> + + * configure.ac (sjlj-exceptions): Restore dropped line. + * configure: Regenerate. + +2022-10-29 Eric Botcazou <ebotcazou@adacore.com> + + * alias.cc (init_alias_analysis): Do not record sets to the hard + frame pointer if the frame pointer has not been eliminated. + +2022-10-29 Iain Buclaw <ibuclaw@gdcproject.org> + + * config/darwin-d.cc (TARGET_D_MINFO_START_NAME): Rename to ... + (TARGET_D_MINFO_SECTION_START): ...this. + (TARGET_D_MINFO_END_NAME): Rename to ... + (TARGET_D_MINFO_SECTION_END): ... this. + * config/elfos.h (TARGET_D_MINFO_SECTION): Remove. + (TARGET_D_MINFO_START_NAME): Remove. + (TARGET_D_MINFO_END_NAME): Remove. + * config/i386/cygwin-d.cc (TARGET_D_MINFO_SECTION): Remove. + (TARGET_D_MINFO_START_NAME): Remove. + (TARGET_D_MINFO_END_NAME): Remove. + * config/i386/winnt-d.cc (TARGET_D_MINFO_SECTION): Remove. + (TARGET_D_MINFO_START_NAME): Remove. + (TARGET_D_MINFO_END_NAME): Remove. + * doc/tm.texi: Regenerate. + * doc/tm.texi.in (TARGET_D_MINFO_START_NAME): Rename to ... + (TARGET_D_MINFO_SECTION_START): ...this. + (TARGET_D_MINFO_END_NAME): Rename to ... + (TARGET_D_MINFO_SECTION_END): ...this. + +2022-10-29 Iain Buclaw <ibuclaw@gdcproject.org> + + * config.gcc: Split out glibc-d.o into linux-d.o, kfreebsd-d.o, + kopensolaris-d.o, and gnu-d.o. Split out cygwin-d.o from winnt-d.o. + * config/arm/linux-eabi.h (EXTRA_TARGET_D_OS_VERSIONS): Remove. + * config/gnu.h (GNU_USER_TARGET_D_OS_VERSIONS): Remove. + * config/i386/cygwin.h (EXTRA_TARGET_D_OS_VERSIONS): Remove. + * config/i386/linux-common.h (EXTRA_TARGET_D_OS_VERSIONS): Remove. + * config/i386/mingw32.h (EXTRA_TARGET_D_OS_VERSIONS): Remove. + * config/i386/t-cygming: Add cygwin-d.o. + * config/i386/winnt-d.cc (winnt_d_os_builtins): Only add + MinGW-specific version condition. + * config/kfreebsd-gnu.h (GNU_USER_TARGET_D_OS_VERSIONS): Remove. + * config/kopensolaris-gnu.h (GNU_USER_TARGET_D_OS_VERSIONS): Remove. + * config/linux-android.h (ANDROID_TARGET_D_OS_VERSIONS): Remove. + * config/linux.h (GNU_USER_TARGET_D_OS_VERSIONS): Remove. + * config/mips/linux-common.h (EXTRA_TARGET_D_OS_VERSIONS): Remove. + * config/t-glibc: Remove glibc-d.o, add gnu-d.o, kfreebsd-d.o, + kopensolaris-d.o. + * config/t-linux: Add linux-d.o. + * config/glibc-d.cc: Remove file. + * config/gnu-d.cc: New file. + * config/i386/cygwin-d.cc: New file. + * config/kfreebsd-d.cc: New file. + * config/kopensolaris-d.cc: New file. + * config/linux-d.cc: New file. + +2022-10-29 Jeff Law <jeffreyalaw@gmail.com> + + * config/h8300/h8300.cc (pre_incdec_with_reg): Make reg argument + an unsigned int + * config/h8300/h8300-protos.h (pre_incdec_with_reg): Adjust prototype. + +2022-10-28 Joseph Myers <joseph@codesourcery.com> + + * config/aarch64/aarch64.cc (aarch64_setup_incoming_varargs): + Check TYPE_NO_NAMED_ARGS_STDARG_P. + * config/alpha/alpha.cc (alpha_setup_incoming_varargs): Likewise. + * config/arc/arc.cc (arc_setup_incoming_varargs): Likewise. + * config/arm/arm.cc (arm_setup_incoming_varargs): Likewise. + * config/csky/csky.cc (csky_setup_incoming_varargs): Likewise. + * config/epiphany/epiphany.cc (epiphany_setup_incoming_varargs): + Likewise. + * config/fr30/fr30.cc (fr30_setup_incoming_varargs): Likewise. + * config/frv/frv.cc (frv_setup_incoming_varargs): Likewise. + * config/ft32/ft32.cc (ft32_setup_incoming_varargs): Likewise. + * config/i386/i386.cc (ix86_setup_incoming_varargs): Likewise. + * config/ia64/ia64.cc (ia64_setup_incoming_varargs): Likewise. + * config/loongarch/loongarch.cc + (loongarch_setup_incoming_varargs): Likewise. + * config/m32r/m32r.cc (m32r_setup_incoming_varargs): Likewise. + * config/mcore/mcore.cc (mcore_setup_incoming_varargs): Likewise. + * config/mips/mips.cc (mips_setup_incoming_varargs): Likewise. + * config/mmix/mmix.cc (mmix_setup_incoming_varargs): Likewise. + * config/nds32/nds32.cc (nds32_setup_incoming_varargs): Likewise. + * config/nios2/nios2.cc (nios2_setup_incoming_varargs): Likewise. + * config/riscv/riscv.cc (riscv_setup_incoming_varargs): Likewise. + * config/rs6000/rs6000-call.cc (setup_incoming_varargs): Likewise. + * config/sh/sh.cc (sh_setup_incoming_varargs): Likewise. + * config/visium/visium.cc (visium_setup_incoming_varargs): + Likewise. + * config/vms/vms-c.cc (vms_c_common_override_options): Do not set + flag_allow_parameterless_variadic_functions. + * doc/invoke.texi (-fallow-parameterless-variadic-functions): Do + not document option. + * function.cc (assign_parms): Call assign_parms_setup_varargs for + TYPE_NO_NAMED_ARGS_STDARG_P case. + * ginclude/stdarg.h [__STDC_VERSION__ > 201710L] (va_start): Make + variadic macro. Pass second argument of 0 to __builtin_va_start. + * target.def (setup_incoming_varargs): Update documentation. + * doc/tm.texi: Regenerate. + * tree-core.h (struct tree_type_common): Add + no_named_args_stdarg_p. + * tree-streamer-in.cc (unpack_ts_type_common_value_fields): Unpack + TYPE_NO_NAMED_ARGS_STDARG_P. + * tree-streamer-out.cc (pack_ts_type_common_value_fields): Pack + TYPE_NO_NAMED_ARGS_STDARG_P. + * tree.cc (type_cache_hasher::equal): Compare + TYPE_NO_NAMED_ARGS_STDARG_P. + (build_function_type): Add argument no_named_args_stdarg_p. + (build_function_type_list_1, build_function_type_array_1) + (reconstruct_complex_type): Update calls to build_function_type. + (stdarg_p, prototype_p): Return true for (...) functions. + (gimple_canonical_types_compatible_p): Compare + TYPE_NO_NAMED_ARGS_STDARG_P. + * tree.h (TYPE_NO_NAMED_ARGS_STDARG_P): New. + (build_function_type): Update prototype. + +2022-10-28 Andre Vieira <andre.simoesdiasvieira@arm.com> + + PR tree-optimization/107346 + * tree-vect-data-refs.cc (vect_check_gather_scatter): Reject offsets + that aren't multiples of BITS_PER_UNIT. + +2022-10-28 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107407 + * tree-ssa-dse.cc (dse_classify_store): Perform backedge + varying index check when collecting PHI uses rather than + after optimizing processing of the candidate defs. + +2022-10-28 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107447 + * tree-ssa-loop-im.cc (determine_max_movement): Do not + hoist returns-twice calls. + +2022-10-28 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107435 + * tree-vect-loop.cc (vectorizable_recurr): Convert initial + value to vector component type. + +2022-10-28 Julian Brown <julian@codesourcery.com> + Thomas Schwinge <thomas@codesourcery.com> + + PR middle-end/90115 + * omp-low.cc (oacc_privatization_candidate_p): Artificial vars are not + privatization candidates. + +2022-10-28 Martin Liska <mliska@suse.cz> + + PR sanitizer/107298 + * doc/invoke.texi: Document sanitizers can trigger warnings. + +2022-10-28 Thomas Schwinge <thomas@codesourcery.com> + + * doc/makefile.texi (Makefile Targets): Document + 'distclean-stage[N]'. + +2022-10-28 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (range_tests_floats): Use HONOR_INFINITIES. + +2022-10-27 Eric Botcazou <ebotcazou@adacore.com> + + * config/aarch64/aarch64.h (DONT_USE_BUILTIN_SETJMP): Delete. + +2022-10-27 H.J. Lu <hjl.tools@gmail.com> + + PR target/107172 + * config/i386/i386.md (UNSPEC_CC_NE): New. + Replace ne:CCC/ne:CCO with UNSPEC_CC_NE in neg patterns. + +2022-10-27 Andrew Pinski <apinski@marvell.com> + + * tree-ssa-phiopt.cc: Include tree-ssa-dce.h + (replace_phi_edge_with_variable): + New argument, dce_ssa_names. Call simple_dce_from_worklist. + (match_simplify_replacement): If we inserted a sequence, + mark the lhs of the new sequence to be possible dce. + Always move the statement and mark the lhs (if it is a name) + as possible to remove. + +2022-10-27 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-protos.h: Replace constexpr with + CONSTEXPR. + * config/aarch64/aarch64-sve-builtins-base.cc: Likewise. + * config/aarch64/aarch64-sve-builtins-functions.h: Likewise. + * config/aarch64/aarch64-sve-builtins-shapes.cc: Likewise. + * config/aarch64/aarch64-sve-builtins-sve2.cc: Likewise. + * config/aarch64/aarch64-sve-builtins.cc: Likewise. + * config/aarch64/aarch64.cc: Likewise. + * config/aarch64/driver-aarch64.cc: Likewise + +2022-10-27 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/107394 + * value-range-storage.cc (frange_storage_slot::get_frange): Use + frange constructor. + +2022-10-27 Thomas Schwinge <thomas@codesourcery.com> + + * optc-save-gen.awk: Clarify 'Init' option property usage for + streaming optimization. + +2022-10-27 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com> + Yvan ROUX <yvan.roux@foss.st.com> + + * ira.cc: Resize array after reg number increased. + +2022-10-27 Jiawei <jiawei@iscas.ac.cn> + Sinan Lin <sinan@isrc.iscas.ac.cn> + + * config/riscv/constraints.md (TARGET_ZFINX ? GR_REGS): Set GPRS + use while Zfinx is enable. + * config/riscv/riscv.cc (riscv_hard_regno_mode_ok): Limit odd + registers use when Zdinx enable in RV32 cases. + (riscv_option_override): New target enable MASK_FDIV. + (riscv_libgcc_floating_mode_supported_p): New error info when + use incompatible arch&abi. + (riscv_excess_precision): New target enable FLOAT16. + +2022-10-27 Jiawei <jiawei@iscas.ac.cn> + + * config/riscv/iterators.md (TARGET_ZFINX):New target. + (TARGET_ZDINX): Ditto. + (TARGET_ZHINX): Ditto. + * config/riscv/riscv-builtins.cc (AVAIL): Ditto. + (riscv_atomic_assign_expand_fenv): Ditto. + * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Ditto. + * config/riscv/riscv.md: Ditto. + +2022-10-27 Jiawei <jiawei@iscas.ac.cn> + Sinan Lin <sinan@isrc.iscas.ac.cn> + + * common/config/riscv/riscv-common.cc: New extensions. + * config/riscv/arch-canonicalize: New imply relations. + * config/riscv/riscv-opts.h (MASK_ZFINX): New mask. + (MASK_ZDINX): Ditto. + (MASK_ZHINX): Ditto. + (MASK_ZHINXMIN): Ditto. + (TARGET_ZFINX): New target. + (TARGET_ZDINX): Ditto. + (TARGET_ZHINX): Ditto. + (TARGET_ZHINXMIN): Ditto. + * config/riscv/riscv.opt: New target variable. + +2022-10-26 David Faust <david.faust@oracle.com> + + * config/bpf/bpf.cc: Support __builtin_preserve_field_info. + (enum bpf_builtins): Add new builtin. + (bpf_init_builtins): Likewise. + (bpf_core_field_info): New function. + (bpf_expand_builtin): Accomodate new builtin. Refactor adding new + relocation to... + (maybe_make_core_relo): ... here. New function. + (bpf_resolve_overloaded_builtin): Accomodate new builtin. + (bpf_core_newdecl): Likewise. + (bpf_core_walk): Likewise. + (bpf_core_is_maybe_aggregate_access): Improve logic. + (struct core_walk_data): New. + * config/bpf/coreout.cc (bpf_core_reloc_add): Allow adding different + relocation kinds. + * config/bpf/coreout.h: Analogous change. + * doc/extend.texi: Document BPF __builtin_preserve_field_info. + +2022-10-26 Marek Polacek <polacek@redhat.com> + + PR c++/106393 + * doc/invoke.texi: Document -Wdangling-reference. + +2022-10-26 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md (movdi): + Copy operands[0...1] to ops[0...3] and then use the latter before + calling xtensa_split_DI_reg_imm() and emitting insns. + +2022-10-26 Alexander Monakov <amonakov@ispras.ru> + + PR other/107353 + * ipa-visibility.cc (function_and_variable_visibility): + Conditionally upgrade TLS model instead of asserting. + +2022-10-26 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-fold.cc (fold_using_range::fold_stmt): Check if + stmt is non-negative and adjust the range. + +2022-10-26 Martin Liska <mliska@suse.cz> + + * common/config/i386/cpuinfo.h (has_cpu_feature): Add comment. + (reset_cpu_feature): New. + (get_zhaoxin_cpu): Use reset_cpu_feature. + +2022-10-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv.cc (riscv_expand_epilogue): Fix statement. + +2022-10-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + PR target/107357 + * config/riscv/riscv-modes.def (VECTOR_BOOL_MODE): Set to minimum size. + (ADJUST_NUNITS): Adjust according to -march. + (ADJUST_BYTESIZE): Ditto. + * config/riscv/riscv-protos.h (riscv_v_ext_enabled_vector_mode_p): + Remove. + (riscv_v_ext_vector_mode_p): Change function implementation. + * config/riscv/riscv-vector-builtins.cc (rvv_switcher::rvv_switcher): + Change to riscv_v_ext_vector_mode_p. + (register_builtin_type): Ditto. + * config/riscv/riscv.cc (riscv_v_ext_vector_mode_p): Change to enabled + modes. + (ENTRY): Ditto. + (riscv_v_ext_enabled_vector_mode_p): Remove. + (riscv_v_adjust_nunits): New function. + (riscv_vector_mode_supported_p): Use riscv_v_ext_vector_mode_p instead. + * config/riscv/riscv.h (riscv_v_adjust_nunits): New function. + +2022-10-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config.gcc (riscv*): Add riscv-v.o to extra_objs. + * config/riscv/constraints.md (vu): New constraint. + (vi): Ditto. + (Wc0): Ditto. + (Wc1): Ditto. + * config/riscv/predicates.md (vector_length_operand): New. + (reg_or_mem_operand): Ditto. + (vector_move_operand): Ditto. + (vector_mask_operand): Ditto. + (vector_merge_operand): Ditto. + * config/riscv/riscv-protos.h (riscv_regmode_natural_size) New. + (riscv_vector::const_vec_all_same_in_range_p): Ditto. + (riscv_vector::legitimize_move): Ditto. + (tail_policy): Ditto. + (mask_policy): Ditto. + * config/riscv/riscv-v.cc: New. + * config/riscv/riscv-vector-builtins-bases.cc + (vsetvl::expand): Refactor how LMUL encoding. + * config/riscv/riscv.cc (riscv_print_operand): Update how LMUL + print and mask operand print. + (riscv_regmode_natural_size): New. + * config/riscv/riscv.h (REGMODE_NATURAL_SIZE): New. + * config/riscv/riscv.md (mode): Add vector modes. + * config/riscv/t-riscv (riscv-v.o) New. + * config/riscv/vector-iterators.md: New. + * config/riscv/vector.md (vundefined<mode>): New. + (mov<mode>): New. + (*mov<mode>): New. + (@vsetvl<mode>_no_side_effects): New. + (@pred_mov<mode>): New. + +2022-10-26 Monk Chiang <monk.chiang@sifive.com> + + * common/config/riscv/riscv-common.cc (riscv_ext_version_table): + Add svinval and svnapot extension. + (riscv_ext_flag_table): Ditto. + * config/riscv/riscv-opts.h (MASK_SVINVAL): New. + (MASK_SVNAPOT): Ditto. + (TARGET_SVINVAL): Ditto. + (TARGET_SVNAPOT): Ditto. + * config/riscv/riscv.opt (riscv_sv_subext): New. + +2022-10-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-modes.def: Adjust table indentation in commnet. + +2022-10-26 Martin Liska <mliska@suse.cz> + + * configure: Regenerate. + +2022-10-26 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (frange::set): Use HONOR_*. + (frange::verify_range): Same. + * value-range.h (frange_val_min): Same. + (frange_val_max): Same. + +2022-10-26 Jiufu Guo <guojiufu@linux.ibm.com> + + PR target/106460 + * config/rs6000/rs6000.cc (rs6000_cannot_force_const_mem): Return true + for HIGH code rtx. + +2022-10-26 Kito Cheng <kito.cheng@sifive.com> + + * common/config/riscv/riscv-common.cc (riscv_ext_version_table): + Add `h`. + (riscv_supported_std_ext): Ditto. + (multi_letter_subset_rank): Remove `h`. + (riscv_subset_list::parse_std_ext): Handle `h` as single letter + extension. + (riscv_subset_list::parse): Ditto. + +2022-10-25 Eugene Rozenfeld <erozen@microsoft.com> + + * auto-profile.cc (get_combined_location): Include discriminator in the + returned combined location. + (read_function_instance): Read discriminators from profiles. + +2022-10-25 H.J. Lu <hjl.tools@gmail.com> + + PR target/107304 + * expr.cc (get_inner_reference): Always use TYPE_MODE for vector + field with vector raw mode. + +2022-10-25 Segher Boessenkool <segher@kernel.crashing.org> + + * config/rs6000/rs6000.md (CCEITHER): Delete. + (CCANY): New. + (un): Delete. + (isel_<un>signed_<GPR:mode>): Rename to... + (isel_<CCANY:mode>_<GPR:mode>): ... this. Adjust. + (*isel_reversed_<un>signed_<GPR:mode>): Rename to... + (*isel_reversed_<CCANY:mode>_<GPR:mode>): ... this. Adjust. + (setbc_<un>signed_<GPR:mode>): Rename to... + (setbc_<CCANY:mode>_<GPR:mode>C): ... this. Adjust." + (*setbcr_<un>signed_<GPR:mode>): Rename to ... + (*setbcr_<CCANY:mode>_<GPR:mode>): ... this. Adjust. + (*setnbc_<un>signed_<GPR:mode>): Rename to ... + (*setnbc_<CCANY:mode>_<GPR:mode>): ... this. Adjust. + (*setnbcr_<un>signed_<GPR:mode>): Rename to ... + (*setnbcr_<CCANY:mode>_<GPR:mode>): ... this. Adjust. + (eq<mode>3 for GPR): Adjust. + (ne<mode>3 for GPR): Adjust. + * config/rs6000/rs6000-string.cc (do_isel): Adjust. + * config/rs6000/rs6000.cc (rs6000_emit_int_cmove): Adjust. + +2022-10-25 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107176 + PR tree-optimization/66375 + PR tree-optimization/42512 + * tree-scalar-evolution.cc (follow_ssa_edge_expr): Revert + the PR66375 fix, do not not associate PLUS_EXPR to be able + to use tail-recursion. + (follow_ssa_edge_binary): Likewise. + (interpret_loop_phi): Revert PR42512 fix, do not throw + away analyze_evolution_in_loop result after the fact. + (follow_ssa_edge_expr): When reaching halting_phi initalize + the evolution to the symbolic value of the PHI result. + (add_to_evolution_1): When adding the first evolution verify + we can handle the expression wrapping the symbolic evolution + and replace that in full using the initial condition. + (class scev_dfs): New, contains ... + (follow_ssa_edge_expr, follow_ssa_edge_binary, + follow_ssa_edge_in_condition_phi_branch, + follow_ssa_edge_in_condition_phi, + follow_ssa_edge_inner_loop_phi, + add_to_evolution, add_to_evolution_1): ... these with + loop and halting_phi arguments in class data. + (scev_dfs::get_ev): New toplevel DFS entry, start with + a chrec_dont_know evolution. + (analyze_evolution_in_loop): Use scev_dfs. + +2022-10-25 Eric Botcazou <ebotcazou@adacore.com> + + * profile.cc (branch_prob): Be prepared for ignored functions with + DECL_SOURCE_LOCATION set to UNKNOWN_LOCATION. + +2022-10-25 Richard Biener <rguenther@suse.de> + + * tree-scalar-evolution.cc (follow_ssa_edge_expr): Move + STRIP_USELESS_TYPE_CONVERSIONS to where it matters. + +2022-10-25 Tejas Joshi <TejasSanjay.Joshi@amd.com> + + * common/config/i386/i386-common.cc (processor_alias_table): Use + CPU_ZNVER3 for znver4. + * config/i386/znver.md: Remove znver4 reservations. + +2022-10-25 Jakub Jelinek <jakub@redhat.com> + + * gimplify.cc (gimple_boolify): Fix comment typos, prduce -> produce + and There -> These. + +2022-10-25 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/107368 + * gimplify.cc (gimplify_call_expr): For complex IFN_ASSUME + conditions call gimple_boolify on the condition. + +2022-10-25 YunQiang Su <yunqiang.su@cipunited.com> + + * config.gcc: add -with-compact-branches=policy build option. + * doc/install.texi: Likewise. + * config/mips/mips.h: Likewise. + +2022-10-25 YunQiang Su <yunqiang.su@cipunited.com> + + * config/mips/mips.cc (mips_option_override): not trigger error + for compact-branches=always for pre-R6. + * config/mips/mips.h (TARGET_RTP_PIC): not trigger error for + compact-branches=always for pre-R6. + (TARGET_CB_NEVER): Likewise. + (TARGET_CB_ALWAYS): Likewise. + (struct mips_cpu_info): define macros for compact branch policy. + * doc/invoke.texi: Document "always" with pre-R6. + +2022-10-25 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/107369 + * gimplify.cc (gimplify_call_expr): If seen_error, handle complex + IFN_ASSUME the same as for -O0. + +2022-10-25 YunQiang Su <yunqiang.su@cipunited.com> + + * configure.ac: AC_DEFINE(ENABLE_MULTIARCH, 1) + * configure: Regenerated. + * config.in: Regenerated. + * config/mips/mips.h: don't define STANDARD_STARTFILE_PREFIX_1 + if ENABLE_MULTIARCH is defined. + * config/mips/t-linux64: define correct multiarch path when + multiarch is enabled. + +2022-10-25 Richard Biener <rguenther@suse.de> + + PR tree-optimization/100756 + * tree-ssa-loop-niter.cc (expand_simple_operations): Also + expand multiplications by invariants. + +2022-10-25 Kewen Lin <linkw@linux.ibm.com> + + PR tree-optimization/107338 + * tree-vect-patterns.cc (vect_recog_bitfield_ref_pattern): Move + shfit_n calculation before the adjustments for widening loads. + +2022-10-25 Martin Liska <mliska@suse.cz> + + * common/config/riscv/riscv-common.cc + (riscv_get_valid_option_values): Get out of ifdef. + +2022-10-25 Martin Liska <mliska@suse.cz> + + PR target/107364 + * common/config/i386/i386-cpuinfo.h (enum processor_vendor): + Fix pedantic warning. + +2022-10-24 Martin Liska <mliska@suse.cz> + + PR analyzer/107366 + * diagnostic-format-sarif.cc + (sarif_builder::maybe_make_physical_location_object): Gracefully + reject locations with NULL filename. + +2022-10-24 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/106300 + * doc/invoke.texi (Static Analyzer Options): Add "pipe" and + "pipe2" to the list of functions the analyzer has hardcoded + knowledge of. + +2022-10-24 Jason Merrill <jason@redhat.com> + + * tree.h (build_string_literal): New one-argument overloads that + take tree (identifier) and const char *. + * builtins.cc (fold_builtin_FILE) + (fold_builtin_FUNCTION) + * gimplify.cc (gimple_add_init_for_auto_var) + * vtable-verify.cc (verify_bb_vtables): Simplify calls. + +2022-10-24 Martin Liska <mliska@suse.cz> + + PR target/107364 + * common/config/i386/i386-cpuinfo.h (enum processor_vendor): + Reorder enum values as BUILTIN_VENDOR_MAX should not point + in the middle of the valid enum values. + +2022-10-24 Marek Polacek <polacek@redhat.com> + + PR c++/107276 + * tree.cc (maybe_wrap_with_location): Don't create a location wrapper + when the type is erroneous. + +2022-10-24 Wilco Dijkstra <wdijkstr@arm.com> + + PR target/106583 + * config/aarch64/aarch64.cc (aarch64_internal_mov_immediate) + Add support for a bitmask immediate with 2 MOVKs. + (aarch64_check_bitmask): New function after refactorization. + (aarch64_bitmask_imm): Simplify replication of small modes. + Split function into 64-bit only version for efficiency. + (aarch64_move_imm): Move near other immediate functions. + (aarch64_uimm12_shift): Likewise. + (aarch64_clamp_to_uimm12_shift): Likewise. + (aarch64_movk_shift): Likewise. + (aarch64_replicate_bitmask_imm): Likewise. + (aarch64_and_split_imm1): Likewise. + (aarch64_and_split_imm2): Likewise. + (aarch64_and_bitmask_imm): Likewise. + (aarch64_movw_imm): Likewise. + +2022-10-24 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/107355 + * range-op-float.cc (foperator_abs::op1_range): Handle NAN. + +2022-10-24 Tobias Burnus <tobias@codesourcery.com> + + PR middle-end/107236 + * omp-expand.cc (expand_omp_target): Set calls_declare_variant_alt + in DECL_CONTEXT and not to cfun->decl. + * cgraphclones.cc (cgraph_node::create_clone): Copy also the + node's calls_declare_variant_alt value. + +2022-10-24 Kito Cheng <kito.cheng@sifive.com> + + * common/config/riscv/riscv-common.cc (riscv_tunes): New. + (riscv_get_valid_option_values): New. + (TARGET_GET_VALID_OPTION_VALUES): New. + * config/riscv/riscv-cores.def (RISCV_TUNE): New, define options + for tune here. + (RISCV_CORE): Fix comment. + * config/riscv/riscv.cc (riscv_tune_info_table): Move definition to + riscv-cores.def. + +2022-10-24 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/107365 + * value-range.cc (frange::verify_range): Predicate NAN check in + VARYING range on HONOR_NANS instead of flag_finite_math_only. + (range_tests_floats): Same. + (range_tests_floats_various): New. + (range_tests): Call range_tests_floats_various. + +2022-10-24 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com> + Yvan ROUX <yvan.roux@foss.st.com> + + * lto-wrapper.cc: Quote paths in makefile. + +2022-10-24 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem) (const_poly_int)). + +2022-10-24 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-vector-builtins-bases.cc: Replace CONSTEXPR + with constexpr throughout. + * config/riscv/riscv-vector-builtins-shapes.cc (SHAPE): Likewise. + * config/riscv/riscv-vector-builtins.cc + (struct registered_function_hasher): Likewise. + * config/riscv/riscv-vector-builtins.h (struct rvv_arg_type_info): + Likewise. + +2022-10-24 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-vector-switch.def (ENTRY): Remove unused TI/TF vector modes. + +2022-10-24 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv.h (REG_CLASS_CONTENTS): Fix ALL_REGS. + +2022-10-22 Michael Eager <eager@eagercon.com> + + * config/microblaze/microblaze.cc + (microblaze_legitimize_address): Initialize 'reg' to NULL, check for NULL. + (microblaze_address_insns): Replace abort() with gcc_unreachable(). + (print_operand_address): Same. + (microblaze_expand_move): Initialize 'p1' to NULL, check for NULL. + (get_branch_target): Replace abort() with gcc_unreachable(). + +2022-10-22 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (range_tests_floats): Predicate [-Inf, +Inf] test + with !flag_finite_math_only. + +2022-10-22 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.cc (xtensa_conditional_register_usage): + Remove register A0 from FIXED_REGS if the CALL0 ABI. + (xtensa_expand_epilogue): Change to emit '(use (reg:SI A0_REG))' + unconditionally after restoring callee-saved registers for + sibling-call functions, in order to prevent misleading that + register A0 is free to use. + +2022-10-21 Jakub Jelinek <jakub@redhat.com> + + PR target/107322 + * config/i386/i386-expand.cc (ix86_prepare_fp_compare_args): For + BFmode comparisons promote arguments to SFmode and recurse. + (ix86_expand_int_movcc, ix86_expand_fp_movcc): Return false early + if comparison operands are BFmode and operands[1] is not + ix86_fp_comparison_operator. + +2022-10-21 Tejas Joshi <TejasSanjay.Joshi@amd.com> + + * common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver4. + * common/config/i386/i386-common.cc (processor_names): Add znver4. + (processor_alias_table): Add znver4 and modularize old znvers. + * common/config/i386/i386-cpuinfo.h (processor_subtypes): + AMDFAM19H_ZNVER4. + * config.gcc (x86_64-*-* |...): Likewise. + * config/i386/driver-i386.cc (host_detect_local_cpu): Let + -march=native recognize znver4 cpus. + * config/i386/i386-c.cc (ix86_target_macros_internal): Add znver4. + * config/i386/i386-options.cc (m_ZNVER4): New definition. + (m_ZNVER): Include m_ZNVER4. + (processor_cost_table): Add znver4. + * config/i386/i386.cc (ix86_reassociation_width): Likewise. + * config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER4. + (PTA_ZNVER1): New definition. + (PTA_ZNVER2): Likewise. + (PTA_ZNVER3): Likewise. + (PTA_ZNVER4): Likewise. + * config/i386/i386.md (define_attr "cpu"): Add znver4 and rename + md file. + * config/i386/x86-tune-costs.h (znver4_cost): New definition. + * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver4. + (ix86_adjust_cost): Likewise. + * config/i386/znver1.md: Rename to znver.md. + * config/i386/znver.md: Add new reservations for znver4. + * doc/extend.texi: Add details about znver4. + * doc/invoke.texi: Likewise. + +2022-10-21 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107323 + * tree-loop-distribution.cc (pg_unmark_merged_alias_ddrs): + New function. + (loop_distribution::break_alias_scc_partitions): Revert + postorder save/restore from the PR94125 fix. Instead + make sure to not ignore edges from SCCs we are going to + merge. + +2022-10-21 Monk Chiang <monk.chiang@sifive.com> + + * config/riscv/riscv.md: Add atomic type attribute. + * config/riscv/sync.md: Add atomic type for atomic instructions. + +2022-10-21 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/54346 + * match.pd ((vec_perm (vec_perm@0 @1 @2 VECTOR_CST) @0 VECTOR_CST)): + Optimize nested VEC_PERM_EXPRs even if target can't handle the + new one provided we don't increase number of VEC_PERM_EXPRs the + target can't handle. + +2022-10-21 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config.gcc: Add riscv-vector-builtins-bases.o and riscv-vector-builtins-shapes.o + * config/riscv/riscv-vector-builtins.cc (DEF_RVV_I_OPS): New macro. + (DEF_RVV_FUNCTION): Ditto. + (handle_pragma_vector): Add intrinsic framework. + * config/riscv/riscv.cc (riscv_print_operand): Add operand print for vsetvl/vsetvlmax. + * config/riscv/riscv.md: include vector.md. + * config/riscv/t-riscv: Add riscv-vector-builtins-bases.o and riscv-vector-builtins-shapes.o + * config/riscv/riscv-vector-builtins-bases.cc: New file. + * config/riscv/riscv-vector-builtins-bases.h: New file. + * config/riscv/riscv-vector-builtins-functions.def: New file. + * config/riscv/riscv-vector-builtins-shapes.cc: New file. + * config/riscv/riscv-vector-builtins-shapes.h: New file. + * config/riscv/riscv-vector-builtins-types.def: New file. + * config/riscv/vector.md: New file. + +2022-10-21 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config.gcc: Add gt files since function_instance is GTY ((user)). + * config/riscv/riscv-builtins.cc (riscv_init_builtins): Add RVV intrinsic framework. + (riscv_builtin_decl): Ditto. + (riscv_expand_builtin): Ditto. + * config/riscv/riscv-protos.h (builtin_decl): New function. + (expand_builtin): Ditto. + (enum riscv_builtin_class): New enum to classify RVV intrinsic and RISC-V general built-in. + * config/riscv/riscv-vector-builtins.cc (class GTY): New declaration. + (struct registered_function_hasher): New struct. + (DEF_RVV_OP_TYPE): New macro. + (DEF_RVV_TYPE): Ditto. + (DEF_RVV_PRED_TYPE): Ditto. + (GTY): New declaration. + (add_attribute): New function. + (check_required_extensions): Ditto. + (rvv_arg_type_info::get_tree_type): Ditto. + (function_instance::function_instance): Ditto. + (function_instance::operator==): Ditto. + (function_instance::any_type_float_p): Ditto. + (function_instance::get_return_type): Ditto. + (function_instance::get_arg_type): Ditto. + (function_instance::hash): Ditto. + (function_instance::call_properties): Ditto. + (function_instance::reads_global_state_p): Ditto. + (function_instance::modifies_global_state_p): Ditto. + (function_instance::could_trap_p): Ditto. + (function_builder::function_builder): Ditto. + (function_builder::~function_builder): Ditto. + (function_builder::allocate_argument_types): Ditto. + (function_builder::register_function_group): Ditto. + (function_builder::append_name): Ditto. + (function_builder::finish_name): Ditto. + (function_builder::get_attributes): Ditto. + (function_builder::add_function): Ditto. + (function_builder::add_unique_function): Ditto. + (function_call_info::function_call_info): Ditto. + (function_expander::function_expander): Ditto. + (function_expander::add_input_operand): Ditto. + (function_expander::generate_insn): Ditto. + (registered_function_hasher::hash): Ditto. + (registered_function_hasher::equal): Ditto. + (builtin_decl): Ditto. + (expand_builtin): Ditto. + (gt_ggc_mx): Define for using GCC garbage collect. + (gt_pch_nx): Define for using GCC garbage collect. + * config/riscv/riscv-vector-builtins.def (DEF_RVV_OP_TYPE): New macro. + (DEF_RVV_PRED_TYPE): Ditto. + (vbool64_t): Add suffix. + (vbool32_t): Ditto. + (vbool16_t): Ditto. + (vbool8_t): Ditto. + (vbool4_t): Ditto. + (vbool2_t): Ditto. + (vbool1_t): Ditto. + (vint8mf8_t): Ditto. + (vuint8mf8_t): Ditto. + (vint8mf4_t): Ditto. + (vuint8mf4_t): Ditto. + (vint8mf2_t): Ditto. + (vuint8mf2_t): Ditto. + (vint8m1_t): Ditto. + (vuint8m1_t): Ditto. + (vint8m2_t): Ditto. + (vuint8m2_t): Ditto. + (vint8m4_t): Ditto. + (vuint8m4_t): Ditto. + (vint8m8_t): Ditto. + (vuint8m8_t): Ditto. + (vint16mf4_t): Ditto. + (vuint16mf4_t): Ditto. + (vint16mf2_t): Ditto. + (vuint16mf2_t): Ditto. + (vint16m1_t): Ditto. + (vuint16m1_t): Ditto. + (vint16m2_t): Ditto. + (vuint16m2_t): Ditto. + (vint16m4_t): Ditto. + (vuint16m4_t): Ditto. + (vint16m8_t): Ditto. + (vuint16m8_t): Ditto. + (vint32mf2_t): Ditto. + (vuint32mf2_t): Ditto. + (vint32m1_t): Ditto. + (vuint32m1_t): Ditto. + (vint32m2_t): Ditto. + (vuint32m2_t): Ditto. + (vint32m4_t): Ditto. + (vuint32m4_t): Ditto. + (vint32m8_t): Ditto. + (vuint32m8_t): Ditto. + (vint64m1_t): Ditto. + (vuint64m1_t): Ditto. + (vint64m2_t): Ditto. + (vuint64m2_t): Ditto. + (vint64m4_t): Ditto. + (vuint64m4_t): Ditto. + (vint64m8_t): Ditto. + (vuint64m8_t): Ditto. + (vfloat32mf2_t): Ditto. + (vfloat32m1_t): Ditto. + (vfloat32m2_t): Ditto. + (vfloat32m4_t): Ditto. + (vfloat32m8_t): Ditto. + (vfloat64m1_t): Ditto. + (vfloat64m2_t): Ditto. + (vfloat64m4_t): Ditto. + (vfloat64m8_t): Ditto. + (vv): Ditto. + (vx): Ditto. + (v): Ditto. + (wv): Ditto. + (wx): Ditto. + (x_x_v): Ditto. + (vf2): Ditto. + (vf4): Ditto. + (vf8): Ditto. + (vvm): Ditto. + (vxm): Ditto. + (x_x_w): Ditto. + (v_v): Ditto. + (v_x): Ditto. + (vs): Ditto. + (mm): Ditto. + (m): Ditto. + (vf): Ditto. + (vm): Ditto. + (wf): Ditto. + (vfm): Ditto. + (v_f): Ditto. + (ta): Ditto. + (tu): Ditto. + (ma): Ditto. + (mu): Ditto. + (tama): Ditto. + (tamu): Ditto. + (tuma): Ditto. + (tumu): Ditto. + (tam): Ditto. + (tum): Ditto. + * config/riscv/riscv-vector-builtins.h (GCC_RISCV_VECTOR_BUILTINS_H): New macro. + (RVV_REQUIRE_RV64BIT): Ditto. + (RVV_REQUIRE_ZVE64): Ditto. + (RVV_REQUIRE_ELEN_FP_32): Ditto. + (RVV_REQUIRE_ELEN_FP_64): Ditto. + (enum operand_type_index): New enum. + (DEF_RVV_OP_TYPE): New macro. + (enum predication_type_index): New enum. + (DEF_RVV_PRED_TYPE): New macro. + (enum rvv_base_type): New enum. + (struct rvv_builtin_suffixes): New struct. + (struct rvv_arg_type_info): Ditto. + (struct rvv_type_info): Ditto. + (struct rvv_op_info): Ditto. + (class registered_function): New class. + (class function_base): Ditto. + (class function_shape): Ditto. + (struct function_group_info): New struct. + (class GTY): New class. + (class function_builder): Ditto. + (class function_call_info): Ditto. + (function_call_info::function_returns_void_p): New function. + (class function_expander): New class. + (function_instance::operator!=): New function. + (function_expander::expand): Ditto. + (function_expander::add_input_operand): Ditto. + (function_base::call_properties): Ditto. + +2022-10-21 Haochen Jiang <haochen.jiang@intel.com> + + * config/i386/sse.md (ssedvecmode): Rename from VI1SI. + (ssedvecmodelower): Rename from vi1si. + (sdot_prod<mode>): New define_expand. + (udot_prod<mode>): Ditto. + +2022-10-21 Kong Lingling <lingling.kong@intel.com> + Hongyu Wang <hongyu.wang@intel.com> + Haochen Jiang <haochen.jiang@intel.com> + + * common/config/i386/cpuinfo.h (get_available_features): Detect + avxvnniint8. + * common/config/i386/i386-common.cc + (OPTION_MASK_ISA2_AVXVNNIINT8_SET): New. + (OPTION_MASK_ISA2_AVXVNNIINT8_UNSET): Ditto. + (ix86_handle_option): Handle -mavxvnniint8. + * common/config/i386/i386-cpuinfo.h (enum processor_features): + Add FEATURE_AVXVNNIINT8. + * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for + avxvnniint8. + * config.gcc: Add avxvnniint8intrin.h. + * config/i386/avxvnniint8intrin.h: New file. + * config/i386/cpuid.h (bit_AVXVNNIINT8): New. + * config/i386/i386-builtin.def: Add new builtins. + * config/i386/i386-c.cc (ix86_target_macros_internal): Define + __AVXVNNIINT8__. + * config/i386/i386-options.cc (isa2_opts): Add -mavxvnniint8. + (ix86_valid_target_attribute_inner_p): Handle avxvnniint8. + * config/i386/i386-isa.def: Add DEF_PTA(AVXVNNIINT8) New.. + * config/i386/i386.opt: Add option -mavxvnniint8. + * config/i386/immintrin.h: Include avxvnniint8intrin.h. + * config/i386/sse.md (UNSPEC_VPMADDUBSWACCD + UNSPEC_VPMADDUBSWACCSSD,UNSPEC_VPMADDWDACCD, + UNSPEC_VPMADDWDACCSSD): Rename according to new style. + (vpdp<vpdotprodtype>_<mode>): New define_insn. + * doc/extend.texi: Document avxvnniint8. + * doc/invoke.texi: Document -mavxvnniint8. + * doc/sourcebuild.texi: Document target avxvnniint8. + +2022-10-21 Hongyu Wang <hongyu.wang@intel.com> + + * common/config/i386/i386-common.cc + (OPTION_MASK_ISA_AVXIFMA_SET, OPTION_MASK_ISA2_AVXIFMA_UNSET, + OPTION_MASK_ISA2_AVX2_UNSET): New macro. + (ix86_handle_option): Handle -mavxifma. + * common/config/i386/i386-cpuinfo.h (processor_types): Add + FEATURE_AVXIFMA. + * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for + avxifma. + * common/config/i386/cpuinfo.h (get_available_features): + Detect avxifma. + * config.gcc: Add avxifmaintrin.h + * config/i386/avx512ifmavlintrin.h: (_mm_madd52lo_epu64): Change + to macro. + (_mm_madd52hi_epu64): Likewise. + (_mm256_madd52lo_epu64): Likewise. + (_mm256_madd52hi_epu64): Likewise. + * config/i386/avxifmaintrin.h: New header. + * config/i386/cpuid.h (bit_AVXIFMA): New. + * config/i386/i386-builtin.def: Add new builtins, and correct + pattern names for AVX512IFMA. + * config/i386/i386-builtins.cc (def_builtin): Handle AVX-IFMA + builtins like AVX-VNNI. + * config/i386/i386-c.cc (ix86_target_macros_internal): Define + __AVXIFMA__. + * config/i386/i386-expand.cc (ix86_check_builtin_isa_match): + Relax ISA masks for AVXIFMA. + * config/i386/i386-isa.def: Add AVXIFMA. + * config/i386/i386-options.cc (isa2_opts): Add -mavxifma. + (ix86_valid_target_attribute_inner_p): Handle avxifma. + * config/i386/i386.md (isa): Add attr avxifma and avxifmavl. + * config/i386/i386.opt: Add option -mavxifma. + * config/i386/immintrin.h: Inculde avxifmaintrin.h. + * config/i386/sse.md (avx_vpmadd52<vpmadd52type>_<mode>): + Remove. + (vpamdd52<vpmadd52type><mode><sd_maskz_name>): Remove. + (vpamdd52huq<mode>_maskz): Rename to ... + (vpmadd52huq<mode>_maskz): ... this. + (vpamdd52luq<mode>_maskz): Rename to ... + (vpmadd52luq<mode>_maskz): ... this. + (vpmadd52<vpmadd52type><mode>): New define_insn. + (vpmadd52<vpmadd52type>v8di): Likewise. + (vpmadd52<vpmadd52type><mode>_maskz_1): Likewise. + (vpamdd52<vpmadd52type><mode>_mask): Rename to ... + (vpmadd52<vpmadd52type><mode>_mask): ... this. + * doc/invoke.texi: Document -mavxifma. + * doc/extend.texi: Document avxifma. + * doc/sourcebuild.texi: Document target avxifma. + +2022-10-20 Aldy Hernandez <aldyh@redhat.com> + + PR c++/106654 + * value-query.cc (get_range_global): Handle non integer ranges for + default def SSA names. + +2022-10-20 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (foperator_unordered_lt::op1_range): New. + (foperator_unordered_lt::op2_range): New. + +2022-10-20 Artem Klimov <jakmobius@gmail.com> + Alexander Monakov <amonakov@gcc.gnu.org> + + PR middle-end/99619 + * ipa-visibility.cc (function_and_variable_visibility): Promote + TLS access model afer visibility optimizations. + * varasm.cc (have_optimized_refs): New helper. + (optimize_dyn_tls_for_decl_p): New helper. Use it ... + (decl_default_tls_model): ... here in place of 'optimize' check. + +2022-10-20 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (foperator_unordered_le::op1_range): Adjust + false side with a NAN operand. + (foperator_unordered_le::op2_range): Same. + (foperator_unordered_gt::op1_range): Same. + (foperator_unordered_gt::op2_range): Same. + (foperator_unordered_ge::op1_range): Same. + (foperator_unordered_ge::op2_range): Same. + (foperator_unordered_equal::op1_range): Same. + +2022-10-20 Andre Vieira <andre.simoesdiasvieira@arm.com> + + PR tree-optimization/107326 + * tree-vect-patterns.cc (vect_recog_bitfield_ref_pattern): Change + vectype when widening container. + +2022-10-20 Aldy Hernandez <aldyh@redhat.com> + + * value-range.h (frange::set_varying): Do not set NAN flags for + !HONOR_NANS. + * value-range.cc (frange::normalize_kind): Adjust for no NAN when + !HONOR_NANS. + (frange::verify_range): Same. + * range-op-float.cc (maybe_isnan): Remove flag_finite_math_only check. + +2022-10-20 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (finite_operand_p): Remove. + (finite_operands_p): Rename to... + (maybe_isnan): ...this. + (frelop_early_resolve): Use maybe_isnan instead of finite_operands_p. + (foperator_equal::fold_range): Same. + (foperator_equal::op1_range): Same. + (foperator_not_equal::fold_range): Same. + (foperator_lt::fold_range): Same. + (foperator_le::fold_range): Same. + (foperator_gt::fold_range): Same. + (foperator_ge::fold_range): Same. + +2022-10-20 Jakub Jelinek <jakub@redhat.com> + + * passes.cc (pass_manager::register_pass): Fix a comment + typo - copmilation -> compilation. + +2022-10-20 Richard Biener <rguenther@suse.de> + + * tree-vect-loop.cc (vect_phi_first_order_recurrence_p): + Disallow latch PHI defs. + (vectorizable_recurr): Revert previous change. + +2022-10-20 Julian Brown <julian@codesourcery.com> + + PR target/105421 + * config/gcn/gcn.cc (gcn_detect_incoming_pointer_arg): Any pointer + argument forces FLAT addressing mode, not just + pointer-to-non-aggregate. + +2022-10-20 Thomas Schwinge <thomas@codesourcery.com> + + * configure.ac (AC_CONFIG_MACRO_DIRS): Instantiate. + * configure: Regenerate. + +2022-10-20 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-sve-builtins.h + (gimple_folder::fold_to_cstu): New member function. + * config/aarch64/aarch64-sve-builtins.cc + (gimple_folder::fold_to_cstu): Define. + * config/aarch64/aarch64-sve-builtins-base.cc + (svcnt_bhwd_impl::fold): Use it. + +2022-10-20 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-sve-builtins-functions.h (quiet) + (rtx_code_function, rtx_code_function_rotated, unspec_based_function) + (unspec_based_function_rotated, unspec_based_function_exact_insn) + (unspec_based_fused_function, unspec_based_fused_lane_function): + Replace constructors with using directives. + * config/aarch64/aarch64-sve-builtins-base.cc (svcnt_bhwd_pat_impl) + (svcreate_impl, svdotprod_lane_impl, svget_impl, svld1_extend_impl) + (svld1_gather_extend_impl, svld234_impl, svldff1_gather_extend) + (svset_impl, svst1_scatter_truncate_impl, svst1_truncate_impl) + (svst234_impl, svundef_impl): Likewise. + * config/aarch64/aarch64-sve-builtins-sve2.cc + (svldnt1_gather_extend_impl, svmovl_lb_impl): Likewise. + (svstnt1_scatter_truncate_impl): Likewise. + +2022-10-20 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-sve-builtins-base.cc: Replace CONSTEXPR + with constexpr throughout. + * config/aarch64/aarch64-sve-builtins-functions.h: Likewise. + * config/aarch64/aarch64-sve-builtins-shapes.cc: Likewise. + * config/aarch64/aarch64-sve-builtins-sve2.cc: Likewise. + * config/aarch64/aarch64-sve-builtins.cc: Likewise. + +2022-10-20 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-sve.md (*aarch64_brk<brk_op>_cc): Remove + merging alternative. + (*aarch64_brk<brk_op>_ptest): Likewise. + +2022-10-20 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/iterators.md (SVE_BRKP): New iterator. + * config/aarch64/aarch64-sve.md (*aarch64_brkn_cc): New pattern. + (*aarch64_brkn_ptest): Likewise. + (*aarch64_brk<brk_op>_cc): Restrict to SVE_BRKP. + (*aarch64_brk<brk_op>_ptest): Likewise. + +2022-10-20 Richard Biener <rguenther@suse.de> + + PR c/107305 + PR c/107306 + * tree-cfg.h (verify_gimple_in_seq): Add parameter to + indicate whether to emit an ICE. Add return value. + (verify_gimple_in_cfg): Likewise. + * tree-cfg.cc (verify_gimple_in_seq): Likewise. + (verify_gimple_in_cfg): Likewise. + +2022-10-20 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107240 + * tree-vect-patterns.cc (vect_recog_bit_insert_pattern): Attempt to + simplify shifted value first. + +2022-10-20 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-gori.h (compute_operand_range): Make public. + * gimple-range-infer.cc (gimple_infer_range::check_assume_func): New. + (gimple_infer_range::gimple_infer_range): Check for assume calls. + * gimple-range-infer.h (check_assume_func): Add prototype. + * gimple-range.cc (assume_query::assume_range_p): New. + (assume_query::range_of_expr): New. + (assume_query::assume_query): New. + (assume_query::calculate_op): New. + (assume_query::calculate_phi): New. + (assume_query::check_taken_edge): New. + (assume_query::calculate_stmt): New. + (assume_query::dump): New. + * gimple-range.h (class assume_query): New. + * tree-vrp.cc (pass_assumptions::execute): Add processing. + +2022-10-19 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (build_le): Document result. + (build_lt): Same. + (build_ge): Same. + (foperator_ge::op2_range): Check result of build_*. + (foperator_unordered_le::op1_range): Same. + (foperator_unordered_le::op2_range): Same. + (foperator_unordered_gt::op1_range): Same. + (foperator_unordered_gt::op2_range): Same. + (foperator_unordered_ge::op1_range): Same. + (foperator_unordered_ge::op2_range): Same. + +2022-10-19 Marek Polacek <polacek@redhat.com> + + PR c++/85043 + * doc/invoke.texi: Update documentation of -Wuseless-cast. + +2022-10-19 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-cache.cc (ranger_cache::range_from_dom): Use + Value_Range not int_range_max. + +2022-10-19 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/107312 + * range.h (range_true_and_false): Special case 1-bit signed types. + * value-range.cc (range_tests_misc): New test. + +2022-10-19 LIU Hao <lh_mouse@126.com> + + * config/i386/mingw-mcfgthread.h: New file + * config/i386/mingw32.h: Add builtin macro and default libraries + for mcfgthread when thread model is `mcf` + * config.gcc: Include 'i386/mingw-mcfgthread.h' when thread model + is `mcf` + * configure.ac: Recognize `mcf` as a valid thread model + * config.in: Regenerate + * configure: Regenerate + +2022-10-19 Lewis Hyatt <lhyatt@gmail.com> + + * gengtype.cc (output_escaped_param): Add missing const. + (get_string_option): Add missing check for option type. + (walk_type): Support new "string_length" GTY option. + (write_types_process_field): Likewise. + * ggc-common.cc (gt_pch_note_object): Add optional length argument. + * ggc.h (gt_pch_note_object): Adjust prototype for new argument. + (gt_pch_n_S2): Declare... + * stringpool.cc (gt_pch_n_S2): ...new function. + * doc/gty.texi: Document new GTY((string_length)) option. + +2022-10-19 Martin Liska <mliska@suse.cz> + + * doc/extend.texi: Remove useless @tie{} directives. + +2022-10-19 Martin Jambor <mjambor@suse.cz> + + PR tree-optimization/107206 + * tree-sra.cc (struct access): New field grp_result_of_prop_from_lhs. + (analyze_access_subtree): Do not create replacements for accesses with + this flag when not toally scalarizing. + (propagate_subaccesses_from_lhs): Set the new flag. + +2022-10-19 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> + + PR target/106355 + * config/s390/s390.cc (s390_call_saved_register_used): For a + parameter with BLKmode fix determining number of consecutive + registers. + +2022-10-19 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa-protos.h + (xtensa_split1_finished_p, xtensa_split_DI_reg_imm): New prototypes. + * config/xtensa/xtensa.cc + (xtensa_split1_finished_p, xtensa_split_DI_reg_imm, xtensa_lra_p): + New functions. + (TARGET_LRA_P): Replace the dummy hook with xtensa_lra_p. + (xt_true_regnum): Rework. + * config/xtensa/xtensa.h (CALL_REALLY_USED_REGISTERS): + Switch from CALL_USED_REGISTERS, and revise the comment. + * config/xtensa/constraints.md (Y): + Use !xtensa_split1_finished_p() instead of can_create_pseudo_p(). + * config/xtensa/predicates.md (move_operand): Ditto. + * config/xtensa/xtensa.md: Add two new split patterns: + - splits DImode immediate load into two SImode ones + - puts out-of-constraint SImode constants into the constant pool + * config/xtensa/xtensa.opt (-mlra): New target-specific option + for testing purpose. + +2022-10-19 Robin Dapp <rdapp@linux.ibm.com> + + * config/s390/s390.md: Move reload_completed and check operands for REG_P. + +2022-10-19 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/107262 + * expr.cc (convert_mode_scalar): For BFmode -> SFmode conversions + of constants, use simplify_unary_operation if fromi has VOIDmode + instead of recursive convert_mode_scalar. + +2022-10-19 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/106990 + * match.pd ((~X - ~Y) -> Y - X, -x & 1 -> x & 1): Guard with + !TYPE_OVERFLOW_SANITIZED (type). + +2022-10-19 Jakub Jelinek <jakub@redhat.com> + + * config/i386/i386-builtins.cc (ix86_bf16_ptr_type_node): Remove. + (ix86_bf16_type_node): New variable. + (ix86_register_bf16_builtin_type): If bfloat16_type_node is NULL + from generic code, set only ix86_bf16_type_node to a new REAL_TYPE + rather than bfloat16_type_node, otherwise set ix86_bf16_type_node + to bfloat16_type_node. Register __bf16 on ix86_bf16_type_node + rather than bfloat16_type_node. Don't initialize unused + ix86_bf16_ptr_type_node. + * config/i386/i386-builtin-types.def (BFLOAT16): Use + ix86_bf16_type_node rather than bfloat16_type_node. + +2022-10-19 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106781 + * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): Copy + LHS removal from fixup_noreturn_call. + +2022-10-19 liuhongt <hongtao.liu@intel.com> + + PR target/107271 + * config/i386/i386-expand.cc (ix86_vec_perm_index_canon): New. + (expand_vec_perm_shufps_shufps): Call + ix86_vec_perm_index_canon + +2022-10-18 Martin Jambor <mjambor@suse.cz> + + * ipa-prop.h (ipa_agg_value): Remove type. + (ipa_agg_value_set): Likewise. + (ipa_copy_agg_values): Remove function. + (ipa_release_agg_values): Likewise. + (ipa_auto_call_arg_values) Add a forward declaration. + (ipa_call_arg_values): Likewise. + (class ipa_argagg_value_list): New constructors, added member function + value_for_index_p. + (class ipa_auto_call_arg_values): Removed the destructor and member + function safe_aggval_at. Use ipa_argagg_values for m_known_aggs. + (class ipa_call_arg_values): Removed member function safe_aggval_at. + Use ipa_argagg_values for m_known_aggs. + (ipa_get_indirect_edge_target): Removed declaration. + (ipa_find_agg_cst_for_param): Likewise. + (ipa_find_agg_cst_from_init): New declaration. + (ipa_agg_value_from_jfunc): Likewise. + (ipa_agg_value_set_from_jfunc): Removed declaration. + (ipa_push_agg_values_from_jfunc): New declaration. + * ipa-cp.cc (ipa_agg_value_from_node): Renamed to + ipa_agg_value_from_jfunc, made public. + (ipa_agg_value_set_from_jfunc): Removed. + (ipa_push_agg_values_from_jfunc): New function. + (ipa_get_indirect_edge_target_1): Removed known_aggs parameter, use + avs for this purpose too. + (ipa_get_indirect_edge_target): Removed the overload working on + ipa_auto_call_arg_values, use ipa_argagg_value_list in the remaining + one. + (devirtualization_time_bonus): Use ipa_argagg_value_list and + ipa_get_indirect_edge_target_1 instead of + ipa_get_indirect_edge_target. + (context_independent_aggregate_values): Removed function. + (gather_context_independent_values): Work on ipa_argagg_value_list. + (estimate_local_effects): Likewise, define some iterator variables + only in the construct where necessary. + (ipcp_discover_new_direct_edges): Adjust the call to + ipa_get_indirect_edge_target_1. + (push_agg_values_for_index_from_edge): Adjust the call + ipa_agg_value_from_node which has been renamed to + ipa_agg_value_from_jfunc. + * ipa-fnsummary.cc (evaluate_conditions_for_known_args): Work on + ipa_argagg_value_list. + (evaluate_properties_for_edge): Replace manual filling in aggregate + values with call to ipa_push_agg_values_from_jfunc. + (estimate_calls_size_and_time): Work on ipa_argagg_value_list. + (ipa_cached_call_context::duplicate_from): Likewise. + (ipa_cached_call_context::release): Likewise. + (ipa_call_context::equal_to): Likewise. + * ipa-prop.cc (ipa_find_agg_cst_from_init): Make public. + (ipa_find_agg_cst_for_param): Removed function. + (ipa_find_agg_cst_from_jfunc_items): New function. + (try_make_edge_direct_simple_call): Replace calls to + ipa_agg_value_set_from_jfunc and ipa_find_agg_cst_for_param with + ipa_find_agg_cst_from_init and ipa_find_agg_cst_from_jfunc_items. + (try_make_edge_direct_virtual_call): Replace calls to + ipa_agg_value_set_from_jfunc and ipa_find_agg_cst_for_param with + simple query of constant jump function and a call to + ipa_find_agg_cst_from_jfunc_items. + (ipa_auto_call_arg_values::~ipa_auto_call_arg_values): Removed. + +2022-10-18 Martin Jambor <mjambor@suse.cz> + + * ipa-prop.h (IPA_PROP_ARG_INDEX_LIMIT_BITS): New. + (ipcp_transformation): Added forward declaration. + (ipa_argagg_value): New type. + (ipa_argagg_value_list): New type. + (ipa_agg_replacement_value): Removed type. + (ipcp_transformation): Switch from using ipa_agg_replacement_value + to ipa_argagg_value_list. + (ipa_get_agg_replacements_for_node): Removed. + (ipa_dump_agg_replacement_values): Removed declaration. + * ipa-cp.cc: Define INCLUDE_ALGORITHM. + (values_equal_for_ipcp_p): Moved up in the file. + (ipa_argagg_value_list::dump): New function. + (ipa_argagg_value_list::debug): Likewise. + (ipa_argagg_value_list::get_elt): Likewise. + (ipa_argagg_value_list::get_elt_for_index): Likewise. + (ipa_argagg_value_list::get_value): New overloaded functions. + (ipa_argagg_value_list::superset_of_p): New function. + (new ipa_argagg_value_list::push_adjusted_values): Likewise. + (push_agg_values_from_plats): Likewise. + (intersect_argaggs_with): Likewise. + (get_clone_agg_value): Removed. + (ipa_agg_value_from_node): Make last parameter const, use + ipa_argagg_value_list to search values coming from clones. + (ipa_get_indirect_edge_target_1): Use ipa_argagg_value_list to search + values coming from clones. + (ipcp_discover_new_direct_edges): Pass around a vector of + ipa_argagg_values rather than a link list of replacement values. + (cgraph_edge_brings_value_p): Use ipa_argagg_value_list to search + values coming from clones. + (create_specialized_node): Work with a vector of ipa_argagg_values + rather than a link list of replacement values. + (self_recursive_agg_pass_through_p): Make the pointer parameters + const. + (copy_plats_to_inter): Removed. + (intersect_with_plats): Likewise. + (agg_replacements_to_vector): Likewise. + (intersect_with_agg_replacements): Likewise. + (intersect_aggregates_with_edge): Likewise. + (push_agg_values_for_index_from_edge): Likewise. + (push_agg_values_from_edge): Likewise. + (find_aggregate_values_for_callers_subset): Rewrite. + (cgraph_edge_brings_all_agg_vals_for_node): Likewise. + (ipcp_val_agg_replacement_ok_p): Use ipa_argagg_value_list to search + aggregate values. + (decide_about_value): Work with a vector of ipa_argagg_values rather + than a link list of replacement values. + (decide_whether_version_node): Likewise. + (ipa_analyze_node): Check number of parameters, assert that there + are no descriptors when bailing out. + * ipa-prop.cc (ipa_set_node_agg_value_chain): Switch to a vector of + ipa_argagg_value. + (ipa_node_params_t::duplicate): Removed superfluous handling of + ipa_agg_replacement_values. Name of src parameter removed because + it is no longer used. + (ipcp_transformation_t::duplicate): Replaced duplication of + ipa_agg_replacement_values with copying vector m_agg_values. + (ipa_dump_agg_replacement_values): Removed. + (write_ipcp_transformation_info): Stream the new data-structure + instead of the old. + (read_ipcp_transformation_info): Likewise. + (adjust_agg_replacement_values): Work with ipa_argagg_values instead + of linked lists of ipa_agg_replacement_values, copy the items and + truncate the vector as necessary to keep it sorted instead of marking + items as invalid. Return one bool if CFG should be updated. + (ipcp_modif_dom_walker): Store ipcp_transformation instead of + linked list of ipa_agg_replacement_values. + (ipcp_modif_dom_walker::before_dom_children): Use + ipa_argagg_value_list instead of walking a list of + ipa_agg_replacement_values. + (ipcp_transform_function): Switch to the new data structure, adjust + dumping. + +2022-10-18 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107302 + * tree-vect-loop.cc (vectorizable_recurrence): Fix vec_perm + placement for a PHI latch def. + +2022-10-18 Andre Vieira <andre.simoesdiasvieira@arm.com> + + PR tree-optimization/107275 + * tree-if-conv.cc (if_convertible_loop_p_1): Move + find_data_references_in_loop call from here... + (if_convertible_loop_p): And move data-reference vector initialization + from here... + (tree_if_conversion):... to here. + +2022-10-18 Jakub Jelinek <jakub@redhat.com> + + PR c++/106654 + * gimple.def (GIMPLE_ASSUME): New statement kind. + * gimple.h (struct gimple_statement_assume): New type. + (is_a_helper <gimple_statement_assume *>::test, + is_a_helper <const gimple_statement_assume *>::test): New. + (gimple_build_assume): Declare. + (gimple_has_substatements): Return true for GIMPLE_ASSUME. + (gimple_assume_guard, gimple_assume_set_guard, + gimple_assume_guard_ptr, gimple_assume_body_ptr, gimple_assume_body): + New inline functions. + * gsstruct.def (GSS_ASSUME): New. + * gimple.cc (gimple_build_assume): New function. + (gimple_copy): Handle GIMPLE_ASSUME. + * gimple-pretty-print.cc (dump_gimple_assume): New function. + (pp_gimple_stmt_1): Handle GIMPLE_ASSUME. + * gimple-walk.cc (walk_gimple_op): Handle GIMPLE_ASSUME. + * omp-low.cc (WALK_SUBSTMTS): Likewise. + (lower_omp_1): Likewise. + * omp-oacc-kernels-decompose.cc (adjust_region_code_walk_stmt_fn): + Likewise. + * tree-cfg.cc (verify_gimple_stmt, verify_gimple_in_seq_2): Likewise. + * function.h (struct function): Add assume_function bitfield. + * gimplify.cc (gimplify_call_expr): If the assumption isn't + simple enough, expand it into GIMPLE_ASSUME wrapped block or + for -O0 drop it. + * gimple-low.cc: Include attribs.h. + (create_assumption_fn): New function. + (struct lower_assumption_data): New type. + (find_assumption_locals_r, assumption_copy_decl, + adjust_assumption_stmt_r, adjust_assumption_stmt_op, + lower_assumption): New functions. + (lower_stmt): Handle GIMPLE_ASSUME. + * tree-ssa-ccp.cc (pass_fold_builtins::execute): Remove + IFN_ASSUME calls. + * lto-streamer-out.cc (output_struct_function_base): Pack + assume_function bit. + * lto-streamer-in.cc (input_struct_function_base): And unpack it. + * cgraphunit.cc (cgraph_node::expand): Don't verify assume_function + has TREE_ASM_WRITTEN set and don't release its body. + (symbol_table::compile): Allow assume functions not to have released + body. + * internal-fn.cc (expand_ASSUME): Remove gcc_unreachable. + * passes.cc (execute_one_pass): For TODO_discard_function don't + release body of assume functions. + * cgraph.cc (cgraph_node::verify_node): Don't verify cgraph nodes + of PROP_assumptions_done functions. + * tree-pass.h (PROP_assumptions_done): Define. + (TODO_discard_function): Adjust comment. + (make_pass_assumptions): Declare. + * passes.def (pass_assumptions): Add. + * timevar.def (TV_TREE_ASSUMPTIONS): New. + * tree-inline.cc (remap_gimple_stmt): Handle GIMPLE_ASSUME. + * tree-vrp.cc (pass_data_assumptions): New variable. + (pass_assumptions): New class. + (make_pass_assumptions): New function. + +2022-10-18 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107301 + * gimple-ssa-isolate-paths.cc (handle_return_addr_local_phi_arg): + Check whether we can duplicate the block. + (find_implicit_erroneous_behavior): Likewise. + +2022-10-18 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/107273 + * value-relation.cc (equiv_oracle::add_partial_equiv): Merge + instead of copying precison of each member. + +2022-10-17 Jeff Law <jeffreyalaw@gmail.com> + + PR target/101697 + * config/h8300/combiner.md: Replace '<' preincment constraint with + ZA/Z1..ZH/Z7 combinations. + * config/h8300/movepush.md: Similarly + +2022-10-17 Jeff Law <jeffreyalaw@gmail.com> + + * config/h8300/constraints.md (Za..Zh): New constraints for + autoinc addresses using a specific register. + * config/h8300/h8300.cc (pre_incdec_with_reg): New function. + * config/h8300/h8300-protos.h (pre_incdec_with_reg): Add prototype. + +2022-10-17 Jeff Law <jlaw@ventanamicro.com> + + * config/i386/cet.c: Remove accidental commit. + * config/i386/driver-mingw32.c: Likewise. + * config/i386/i386-builtins.c: Likewise. + * config/i386/i386-d.c: Likewise. + * config/i386/i386-expand.c: Likewise. + * config/i386/i386-features.c: Likewise. + * config/i386/i386-options.c: Likewise. + * config/i386/t-cet: Likewise. + * config/i386/x86-tune-sched-atom.c: Likewise. + * config/i386/x86-tune-sched-bd.c: Likewise. + * config/i386/x86-tune-sched-core.c: Likewise. + * config/i386/x86-tune-sched.c: Likewise. + +2022-10-17 Jeff Law <jeffreyalaw@gmail.com> + + * common/config/h8300/h8300-common.cc (h8300_option_optimization_table): + Enable redundant extension elimination at -O2 and above. + * config/i386/cet.c: New file. + * config/i386/driver-mingw32.c: New file. + * config/i386/i386-builtins.c: New file. + * config/i386/i386-d.c: New file. + * config/i386/i386-expand.c: New file. + * config/i386/i386-features.c: New file. + * config/i386/i386-options.c: New file. + * config/i386/t-cet: New file. + * config/i386/x86-tune-sched-atom.c: New file. + * config/i386/x86-tune-sched-bd.c: New file. + * config/i386/x86-tune-sched-core.c: New file. + * config/i386/x86-tune-sched.c: New file. + +2022-10-17 Jeff Law <jeffreyalaw@gmail.com> + + * config/h8300/extensions.md (CCZN setting zero extended load): Add + missing splitter. + +2022-10-17 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/107293 + * tree-ssa-dom.cc + (dom_opt_dom_walker::set_global_ranges_from_unreachable_edges): + Check that condition post-dominates the definition point. + +2022-10-17 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/107286 + * value-range.cc (range_tests_floats): Do not test for -Inf when + flag_finite_math_only. + +2022-10-17 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-fold.cc (fold_using_range::range_of_range_op): + Provide relation_trio class. + * gimple-range-gori.cc (gori_compute::refine_using_relation): + Provide relation_trio class. + (gori_compute::refine_using_relation): Ditto. + (gori_compute::compute_operand1_range): Provide lhs_op2 and + op1_op2 relations via relation_trio class. + (gori_compute::compute_operand2_range): Ditto. + * gimple-range-op.cc (gimple_range_op_handler::calc_op1): Use + relation_trio instead of relation_kind. + (gimple_range_op_handler::calc_op2): Ditto. + (*::fold_range): Ditto. + * gimple-range-op.h (gimple_range_op::calc_op1): Adjust prototypes. + (gimple_range_op::calc_op2): Adjust prototypes. + * range-op-float.cc (*::fold_range): Use relation_trio instead of + relation_kind. + (*::op1_range): Ditto. + (*::op2_range): Ditto. + * range-op.cc (*::fold_range): Use relation_trio instead of + relation_kind. + (*::op1_range): Ditto. + (*::op2_range): Ditto. + * range-op.h (class range_operator): Adjust prototypes. + (class range_operator_float): Ditto. + (class range_op_handler): Adjust prototypes. + (relop_early_resolve): Pickup op1_op2 relation from relation_trio. + * value-relation.cc (VREL_LAST): Adjust use to be one past the end of + the enum. + (relation_oracle::validate_relation): Use relation_trio in call + to fold_range. + * value-relation.h (enum relation_kind_t): Add VREL_LAST as + final element. + (class relation_trio): New. + (TRIO_VARYING, TRIO_SHIFT, TRIO_MASK): New. + +2022-10-17 Andrew MacLeod <amacleod@redhat.com> + + * range-op-float.cc (foperator_not_equal::op1_range): Check for + VREL_EQ after singleton. + (foperator_unordered::op1_range): Set VARYING before calling + clear_nan(). + (foperator_ordered::op1_range): Set rather than clear NAN if both + operands are the same. + +2022-10-17 Andrew MacLeod <amacleod@redhat.com> + + * value-relation.cc (value_relation::dump): Change message. + * value-relation.h (value_relation::set_relation): If op1 is the + same as op2 do not create a relation. + +2022-10-17 Thomas Schwinge <thomas@codesourcery.com> + + * config/gcn/gcn.cc (VnMODE): Use 'case E_QImode:' instead of + 'case QImode:', etc. + +2022-10-17 Thomas Schwinge <thomas@codesourcery.com> + + * gimple-expr.cc (mark_addressable_2): Tag as 'static'. + +2022-10-17 Richard Biener <rguenther@suse.de> + Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + PR tree-optimization/99409 + PR tree-optimization/99394 + * tree-vectorizer.h (vect_def_type::vect_first_order_recurrence): Add. + (stmt_vec_info_type::recurr_info_type): Likewise. + (vectorizable_recurr): New function. + * tree-vect-loop.cc (vect_phi_first_order_recurrence_p): New + function. + (vect_analyze_scalar_cycles_1): Look for first order + recurrences. + (vect_analyze_loop_operations): Handle them. + (vect_transform_loop): Likewise. + (vectorizable_recurr): New function. + (maybe_set_vectorized_backedge_value): Handle the backedge value + setting in the first order recurrence PHI and the permutes. + * tree-vect-stmts.cc (vect_analyze_stmt): Handle first order + recurrences. + (vect_transform_stmt): Likewise. + (vect_is_simple_use): Likewise. + (vect_is_simple_use): Likewise. + * tree-vect-slp.cc (vect_get_and_check_slp_defs): Likewise. + (vect_build_slp_tree_2): Likewise. + (vect_schedule_scc): Handle the backedge value setting in the + first order recurrence PHI and the permutes. + +2022-10-17 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/t-riscv: Change Tab into 2 space. + +2022-10-17 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-vector-builtins.cc (mangle_builtin_type): Move down the function. + +2022-10-17 Arsen Arsenovic <arsen@aarsen.me> + + * config.gcc: --target=*-elf --without-{newlib,headers} should + provide stdint.h. + +2022-10-17 Hu, Lin1 <lin1.hu@intel.com> + + * common/config/i386/cpuinfo.h: + (get_intel_cpu): Handle Meteorlake. + * common/config/i386/i386-common.cc: + (processor_alias_table): Add Meteorlake. + +2022-10-17 Haochen Jiang <haochen.jiang@intel.com> + + * common/config/i386/cpuinfo.h: + (get_intel_cpu): Handle Raptorlake. + * common/config/i386/i386-common.cc: + (processor_alias_table): Add Raptorlake. + +2022-10-16 Jeff Law <jeffreyalaw@gmail.com> + + * config/h8300/constraints.md (Z0..Z7): New register + constraints. + * config/h8300/h8300.h (reg_class): Add new classes. + (REG_CLASS_NAMES): Similarly. + (REG_CLASS_CONTENTS): Similarly. + +2022-10-16 Jeff Law <jeffreyalaw@gmail.com> + + * config/h8300/constraints.md (Zz constraint): Renamed + from "z". + * config/h8300/movepush.md (movqi_h8sx, movhi_h8sx): Adjust + constraint to use Zz instead of Z. + +2022-10-16 Jeff Law <jeffreyalaw@gmail.com> + + * config/h8300/h8300.cc (h8300_register_move_cost): Fix typo. + +2022-10-14 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (frange::set): Implement distinction between + HONOR_SIGNED_ZEROS and MODE_HAS_SIGNED_ZEROS. + +2022-10-14 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-op.cc (class cfn_copysign): New. + (gimple_range_op_handler::maybe_builtin_call): Add + CFN_BUILT_IN_COPYSIGN*. + +2022-10-14 Aldy Hernandez <aldyh@redhat.com> + + * real.h (real_isdenormal): Check rvc_normal. + * value-range.cc (range_tests_floats): New test. + +2022-10-14 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-op.cc + (gimple_range_op_handler::maybe_builtin_call): Replace + CFN_BUILTIN_SIGNBIT* cases with CASE_FLT_FN. + +2022-10-14 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (frange::set): Normalize ranges for both bounds. + +2022-10-14 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (frange::set): Drop -0.0 for !HONOR_SIGNED_ZEROS. + +2022-10-14 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-op.cc + (gimple_range_op_handler::maybe_builtin_call): Add + CFN_BUILT_IN_SIGNBIT[FL]* entries. + +2022-10-14 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107254 + * tree-vect-slp.cc (vect_slp_analyze_node_operations_1): + For permutes also analyze live lanes. + (vect_schedule_slp_node): For permutes also code generate + live lane extracts. + +2022-10-14 Eric Botcazou <ebotcazou@adacore.com> + + PR target/107248 + * config/sparc/sparc.cc (sparc_expand_prologue): Emit a frame + blockage for leaf functions. + (sparc_flat_expand_prologue): Emit frame instead of full blockage. + (sparc_expand_epilogue): Emit a frame blockage for leaf functions. + (sparc_flat_expand_epilogue): Emit frame instead of full blockage. + +2022-10-14 Jakub Jelinek <jakub@redhat.com> + + * tree-core.h (enum tree_index): Add TI_BFLOAT16_TYPE. + * tree.h (bfloat16_type_node): Define. + * tree.cc (excess_precision_type): Promote bfloat16_type_mode + like float16_type_mode. + (build_common_tree_nodes): Initialize bfloat16_type_node if + BFmode is supported. + * expmed.h (maybe_expand_shift): Declare. + * expmed.cc (maybe_expand_shift): No longer static. + * expr.cc (convert_mode_scalar): Don't ICE on BF -> HF or HF -> BF + conversions. If there is no optab, handle BF -> {DF,XF,TF,HF} + conversions as separate BF -> SF -> {DF,XF,TF,HF} conversions, add + -ffast-math generic implementation for BF -> SF and SF -> BF + conversions. + * builtin-types.def (BT_BFLOAT16, BT_FN_BFLOAT16_CONST_STRING): New. + * builtins.def (BUILT_IN_NANSF16B): New builtin. + * fold-const-call.cc (fold_const_call): Handle CFN_BUILT_IN_NANSF16B. + * config/i386/i386.cc (classify_argument): Handle E_BCmode. + (ix86_libgcc_floating_mode_supported_p): Also return true for BFmode + for -msse2. + (ix86_mangle_type): Mangle BFmode as DF16b. + (ix86_invalid_conversion, ix86_invalid_unary_op, + ix86_invalid_binary_op): Remove. + (TARGET_INVALID_CONVERSION, TARGET_INVALID_UNARY_OP, + TARGET_INVALID_BINARY_OP): Don't redefine. + * config/i386/i386-builtins.cc (ix86_bf16_type_node): Remove. + (ix86_register_bf16_builtin_type): Use bfloat16_type_node rather than + ix86_bf16_type_node, only create it if still NULL. + * config/i386/i386-builtin-types.def (BFLOAT16): Likewise. + * config/i386/i386.md (cbranchbf4, cstorebf4): New expanders. + +2022-10-14 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/323 + PR c++/107097 + * doc/invoke.texi (-fexcess-precision=standard): Mention that the + option now also works in C++. + +2022-10-13 Eric Botcazou <ebotcazou@adacore.com> + + * gimple-ssa-warn-access.cc (pass_waccess::check_call): Return + early for calls made from thunks. + +2022-10-13 Eric Botcazou <ebotcazou@adacore.com> + + * expr.cc (emit_group_stote): Fix handling of modes of different + sizes for big-endian targets in latest change and add commentary. + +2022-10-13 Martin Liska <mliska@suse.cz> + + * output.h (assemble_vtv_preinit_initializer): Remove. + * varasm.cc (assemble_vtv_preinit_initializer): Remove. + +2022-10-13 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/102540 + PR tree-optimization/102872 + * gimple-range-cache.cc (ranger_cache::fill_block_cache): + Handle partial equivs. + (ranger_cache::range_from_dom): Cleanup dump output. + +2022-10-13 Andrew MacLeod <amacleod@redhat.com> + + * range-op.cc (operator_cast::lhs_op1_relation): New. + (operator_bitwise_and::lhs_op1_relation): New. + +2022-10-13 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-cache.cc (ranger_cache::fill_block_cache): Use + iterator. + * value-relation.cc + (equiv_relation_iterator::equiv_relation_iterator): New. + (equiv_relation_iterator::next): New. + (equiv_relation_iterator::get_name): New. + * value-relation.h (class relation_oracle): Privatize some methods. + (class equiv_relation_iterator): New. + (FOR_EACH_EQUIVALENCE): New. + (FOR_EACH_PARTIAL_EQUIV): New. + (FOR_EACH_PARTIAL_AND_FULL_EQUIV): New. + +2022-10-13 Andrew MacLeod <amacleod@redhat.com> + + * value-relation.cc (equiv_chain::dump): Don't print empty + equivalences. + (equiv_oracle::equiv_oracle): Allocate a partial equiv table. + (equiv_oracle::~equiv_oracle): Release the partial equiv table. + (equiv_oracle::add_partial_equiv): New. + (equiv_oracle::partial_equiv_set): New. + (equiv_oracle::partial_equiv): New. + (equiv_oracle::query_relation): Check for partial equivs too. + (equiv_oracle::dump): Also dump partial equivs. + (dom_oracle::register_relation): Handle partial equivs. + (dom_oracle::query_relation): Check for partial equivs. + * value-relation.h (enum relation_kind_t): Add partial equivs. + (relation_partial_equiv_p): New. + (relation_equiv_p): New. + (class pe_slice): New. + (class equiv_oracle): Add prototypes. + (pe_to_bits): New. + (bits_to_pe): New. + (pe_min): New. + +2022-10-13 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107247 + * tree-vect-loop.cc (vect_create_epilog_for_reduction): + Reduce multi vector SLP reduction accumulators. Check + the adjusted number of accumulator vectors against + one for the re-use in the epilogue. + +2022-10-13 Jakub Jelinek <jakub@redhat.com> + + * genmodes.cc (emit_mode_wider): Emit previous content of + mode_wider array into mode_next array and for mode_wider + emit always VOIDmode for !CLASS_HAS_WIDER_MODES_P classes, + otherwise skip through modes with the same precision. + * machmode.h (mode_next): Declare. + (GET_MODE_NEXT_MODE): New inline function. + (mode_iterator::get_next, mode_iterator::get_known_next): New + function templates. + (FOR_EACH_MODE_IN_CLASS): Use get_next instead of get_wider. + (FOR_EACH_MODE): Use get_known_next instead of get_known_wider. + (FOR_EACH_MODE_FROM): Use get_next instead of get_wider. + (FOR_EACH_WIDER_MODE_FROM): Define. + (FOR_EACH_NEXT_MODE): Define. + * expmed.cc (emit_store_flag_1): Use FOR_EACH_WIDER_MODE_FROM + instead of FOR_EACH_MODE_FROM. + * optabs.cc (prepare_cmp_insn): Likewise. Remove redundant + !CLASS_HAS_WIDER_MODES_P check. + (prepare_float_lib_cmp): Use FOR_EACH_WIDER_MODE_FROM instead of + FOR_EACH_MODE_FROM. + * config/i386/i386-expand.cc (get_mode_wider_vector): Use + GET_MODE_NEXT_MODE instead of GET_MODE_WIDER_MODE. + +2022-10-13 Wilco Dijkstra <wdijkstr@arm.com> + + PR target/105773 + * config/aarch64/aarch64.cc (aarch64_select_cc_mode): Allow + GT/LE for merging compare with zero into AND. + (aarch64_get_condition_code_1): Add CC_NZVmode support. + * config/aarch64/aarch64-modes.def: Add CC_NZV. + * config/aarch64/aarch64.md: Use CC_NZV in cmp+and patterns. + +2022-10-13 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107160 + * tree-vect-loop.cc (vect_create_epilog_for_reduction): + Do not register accumulator if we failed to reduce it + to a single vector. + +2022-10-13 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (range_operator_float::op1_op2_relation): New. + (class foperator_equal): Add using. + (class foperator_not_equal): Same. + (class foperator_lt): Same. + (class foperator_le): Same. + (class foperator_gt): Same. + (class foperator_ge): Same. + * range-op.cc (range_op_handler::op1_op2_relation): New. + * range-op.h (range_operator_float::op1_op2_relation): New. + +2022-10-13 Richard Biener <rguenther@suse.de> + + * genmatch.cc (parser::parse_c_expr): Diagnose 'return'. + * match.pd: Replace 'return' statements in with expressions + with appropriate variants. + +2022-10-13 Andre Vieira <andre.simoesdiasvieira@arm.com> + + PR tree-optimization/107229 + * tree-if-conv.cc (get_bitfield_rep): Fix bitposition calculation. + +2022-10-13 Andre Vieira <andre.simoesdiasvieira@arm.com> + + PR tree-optimization/107226 + * tree-vect-patterns.cc (vect_recog_bitfield_ref_pattern): Reject + BITFIELD_REF's with non integral typed first operands. + +2022-10-13 Joseph Myers <joseph@codesourcery.com> + + * ginclude/float.h (FLT_IS_IEC_60559, DBL_IS_IEC_60559) + (LDBL_IS_IEC_60559): Update comment. + +2022-10-12 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (class foperator_negate): New. + (floating_op_table::floating_op_table): Add NEGATE_EXPR + (range_op_float_tests): Add negate tests. + +2022-10-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-vector-builtins.h: Remove unused macro. + +2022-10-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-vector-builtins.cc (DEF_RVV_TYPE): Apply + clang-format. + (add_vector_type_attribute): Ditto. + * config/riscv/riscv-vector-builtins.def (DEF_RVV_TYPE): Apply + clang-format. + * config/riscv/riscv-vector-builtins.h (DEF_RVV_TYPE): Apply + clang-format. + +2022-10-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-vector-builtins.cc (builtin_types): Redefine + vector types. + (build_const_pointer): New function. + (register_builtin_type): Ditto. + (DEF_RVV_TYPE): Simplify macro. + (register_vector_type): Refine implementation. + * config/riscv/riscv-vector-builtins.h (rvv_builtin_types_t): New. + +2022-10-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-vector-builtins.h (class rvv_switcher): Move to + this to .... + * config/riscv/riscv-vector-builtins.cc (class rvv_switcher): + here. + +2022-10-12 Cui,Lili <lili.cui@intel.com> + + * config/i386/driver-i386.cc (host_detect_local_cpu): + Move sapphirerapids out of AVX512_VP2INTERSECT. + * config/i386/i386.h: Remove AVX512_VP2INTERSECT from PTA_SAPPHIRERAPIDS + * doc/invoke.texi: Remove AVX512_VP2INTERSECT from SAPPHIRERAPIDS + +2022-10-12 Martin Liska <mliska@suse.cz> + + * gcov-io.cc (gcov_write_summary): Rename to ... + (gcov_write_object_summary): ... this. + * gcov-io.h (GCOV_TAG_OBJECT_SUMMARY_LENGTH): Rename from ... + (GCOV_TAG_SUMMARY_LENGTH): ... this. + +2022-10-12 Martin Liska <mliska@suse.cz> + + * configure: Regenerate. + +2022-10-12 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (frange_float): New. + (range_op_float_tests): New. + * range-op.cc (range_op_tests): Call range_op_float_tests. + +2022-10-12 Aldy Hernandez <aldyh@redhat.com> + + * value-range.h (frange::nan_signbit_p): New. + +2022-10-12 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (frange::set_nonnegative): Pass bool to + update_nan. + * value-range.h: Disallow conversion to bool in update_nan(). + +2022-10-12 Aldy Hernandez <aldyh@redhat.com> + + * value-range.h (frange::frange): Add constructor taking type. + +2022-10-12 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc: Add relation_kind = VREL_VARYING to all + methods. + +2022-10-11 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-gori.cc (gori_compute::logical_combine): Avoid + calling tracer.trailer(). + +2022-10-11 Jakub Jelinek <jakub@redhat.com> + + PR target/107185 + * config/i386/i386.md (*notxor<mode>_1): Use MASK_REG_P (x) instead of + MASK_REGNO_P (REGNO (x)). + +2022-10-11 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (class foperator_abs): New. + (floating_op_table::floating_op_table): Add ABS_EXPR entry. + +2022-10-11 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (foperator_unordered_le::op1_range): New. + (foperator_unordered_le::op2_range): New. + (foperator_unordered_gt::op1_range): New. + (foperator_unordered_gt::op2_range): New. + (foperator_unordered_ge::op1_range): New. + (foperator_unordered_ge::op2_range): New. + (foperator_unordered_equal::op1_range): New. + +2022-10-11 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (class foperator_unordered_lt): New. + (class foperator_relop_unknown): Remove + (class foperator_unordered_le): New. + (class foperator_unordered_gt): New. + (class foperator_unordered_ge): New. + (class foperator_unordered_equal): New. + (floating_op_table::floating_op_table): Replace all UN_EXPR + entries with their appropriate fop_unordered_* counterpart. + +2022-10-11 Aldy Hernandez <aldyh@redhat.com> + + * range-op.cc (operator_equal::op1_range): Move BRS_TRUE case up. + (operator_lt::op2_range): Same. + (operator_le::op2_range): Same. + (operator_gt::op2_range): Same. + (operator_ge::op2_range): Same. + +2022-10-11 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107212 + * tree-vect-loop.cc (vectorizable_reduction): Make sure to + set STMT_VINFO_REDUC_DEF for all live lanes in a SLP + reduction. + (vectorizable_live_operation): Do not pun to the SLP + node representative for reduction epilogue generation. + +2022-10-11 Andrew Stubbs <ams@codesourcery.com> + + * config/gcn/gcn-valu.md (neg<mode>2): New define_expand. + +2022-10-11 Andrew Stubbs <ams@codesourcery.com> + + * config/gcn/gcn-valu.md (vec_init<V_ALL:mode><V_ALL_ALT:mode>): New. + * config/gcn/gcn.cc (GEN_VN): Add andvNsi3, subvNsi3. + (GEN_VNM): Add gathervNm_expr. + (GEN_VN_NOEXEC): Add vec_seriesvNsi. + (gcn_expand_vector_init): Add initialization of vectors from smaller + vectors. + +2022-10-11 Andrew Stubbs <ams@codesourcery.com> + + * config/gcn/gcn-protos.h (get_exec): Add prototypes for two variants. + * config/gcn/gcn-valu.md + (vec_extract<V_ALL:mode><V_ALL_ALT:mode>): New define_expand. + * config/gcn/gcn.cc (get_exec): Export the existing function. Add a + new overload variant. + +2022-10-11 Andrew Stubbs <ams@codesourcery.com> + + * config/gcn/gcn-valu.md + (<cvt_name><VCVT_MODE:mode><VCVT_FMODE:mode>2<exec>): Use MODE_VF. + (<cvt_name><VCVT_FMODE:mode><VCVT_IMODE:mode>2<exec>): Likewise. + * config/gcn/gcn.h (MODE_VF): New macro. + +2022-10-11 Andrew Stubbs <ams@codesourcery.com> + + * config/gcn/gcn-modes.def (VECTOR_MODE): Add new modes + V32QI, V32HI, V32SI, V32DI, V32TI, V32HF, V32SF, V32DF, + V16QI, V16HI, V16SI, V16DI, V16TI, V16HF, V16SF, V16DF, + V8QI, V8HI, V8SI, V8DI, V8TI, V8HF, V8SF, V8DF, + V4QI, V4HI, V4SI, V4DI, V4TI, V4HF, V4SF, V4DF, + V2QI, V2HI, V2SI, V2DI, V2TI, V2HF, V2SF, V2DF. + (ADJUST_ALIGNMENT): Likewise. + * config/gcn/gcn-protos.h (gcn_full_exec): Delete. + (gcn_full_exec_reg): Delete. + (gcn_scalar_exec): Delete. + (gcn_scalar_exec_reg): Delete. + (vgpr_1reg_mode_p): Use inner mode to identify vector registers. + (vgpr_2reg_mode_p): Likewise. + (vgpr_vector_mode_p): Use VECTOR_MODE_P. + * config/gcn/gcn-valu.md (V_QI, V_HI, V_HF, V_SI, V_SF, V_DI, V_DF, + V_QIHI, V_1REG, V_INT_1REG, V_INT_1REG_ALT, V_FP_1REG, V_2REG, V_noQI, + V_noHI, V_INT_noQI, V_INT_noHI, V_ALL, V_ALL_ALT, V_INT, V_FP): + Add additional vector modes. + (V64_SI, V64_DI, V64_ALL, V64_FP): New iterators. + (scalar_mode, SCALAR_MODE, vnsi, VnSI, vndi, VnDI, sdwa): + Add additional vector mode mappings. + (mov<mode>): Implement vector length conversions. + (ldexp<mode>3<exec>): Use VnSI. + (frexp<mode>_exp2<exec>): Likewise. + (VCVT_MODE, VCVT_FMODE, VCVT_IMODE): Add additional vector modes. + (reduc_<reduc_op>_scal_<mode>): Use V64_ALL. + (fold_left_plus_<mode>): Use V64_FP. + (*<reduc_op>_dpp_shr_<mode>): Use V64_1REG. + (*<reduc_op>_dpp_shr_<mode>): Use V64_DI. + (*plus_carry_dpp_shr_<mode>): Use V64_INT_1REG. + (*plus_carry_in_dpp_shr_<mode>): Use V64_SI. + (*plus_carry_dpp_shr_<mode>): Use V64_DI. + (mov_from_lane63_<mode>): Use V64_2REG. + * config/gcn/gcn.cc (VnMODE): New function. + (gcn_can_change_mode_class): Support multiple vector sizes. + (gcn_modes_tieable_p): Likewise. + (gcn_operand_part): Likewise. + (gcn_scalar_exec): Delete function. + (gcn_scalar_exec_reg): Delete function. + (gcn_full_exec): Delete function. + (gcn_full_exec_reg): Delete function. + (gcn_inline_fp_constant_p): Support multiple vector sizes. + (gcn_fp_constant_p): Likewise. + (A): New macro. + (GEN_VN_NOEXEC): New macro. + (GEN_VNM_NOEXEC): New macro. + (GEN_VN): New macro. + (GEN_VNM): New macro. + (GET_VN_FN): New macro. + (CODE_FOR): New macro. + (CODE_FOR_OP): New macro. + (gen_mov_with_exec): Delete function. + (gen_duplicate_load): Delete function. + (gcn_expand_vector_init): Support multiple vector sizes. + (strided_constant): Likewise. + (gcn_addr_space_legitimize_address): Likewise. + (gcn_expand_scalar_to_vector_address): Likewise. + (gcn_expand_scaled_offsets): Likewise. + (gcn_secondary_reload): Likewise. + (gcn_valid_cvt_p): Likewise. + (gcn_expand_builtin_1): Likewise. + (gcn_make_vec_perm_address): Likewise. + (gcn_vectorize_vec_perm_const): Likewise. + (gcn_vector_mode_supported_p): Likewise. + (gcn_autovectorize_vector_modes): New hook. + (gcn_related_vector_mode): Support multiple vector sizes. + (gcn_expand_dpp_shr_insn): Add FIXME comment. + (gcn_md_reorg): Support multiple vector sizes. + (print_reg): Likewise. + (print_operand): Likewise. + (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES): New hook. + +2022-10-11 Andre Vieira <andre.simoesdiasvieira@arm.com> + + * tree-if-conv.cc (if_convertible_loop_p_1): Move ordering of loop bb's from + here... + (tree_if_conversion): ... to here. Also call bitfield lowering when + appropriate. + (version_loop_for_if_conversion): Adapt to enable loop versioning when we only + need to lower bitfields. + (ifcvt_split_critical_edges): Relax condition of expected loop form as this is + checked earlier. + (get_bitfield_rep): New function. + (lower_bitfield): Likewise. + (bitfields_to_lower_p): Likewise. + (need_to_lower_bitfields): New global boolean. + (need_to_ifcvt): Likewise. + * tree-vect-data-refs.cc (vect_find_stmt_data_reference): Improve diagnostic + message. + * tree-vect-patterns.cc (vect_recog_temp_ssa_var): Add default value for last + parameter. + (vect_recog_bitfield_ref_pattern): New. + (vect_recog_bit_insert_pattern): New. + +2022-10-11 liuhongt <hongtao.liu@intel.com> + + PR target/107093 + * config/i386/i386.md (*notxor<mode>_1): New post_reload + define_insn_and_split. + (*notxorqi_1): Ditto. + +2022-10-11 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/107195 + * value-range.cc (irange::set_range_from_nonzero_bits): Set range + to [0,0] when nonzero mask is 0. + +2022-10-11 Olivier Hainque <hainque@adacore.com> + + * configure: Regenerate. + +2022-10-11 Olivier Hainque <hainque@adacore.com> + + * config.gcc (*vxworks*): Add t-slibgcc fragment + if enable_shared. + +2022-10-11 Olivier Hainque <hainque@adacore.com> + + * config/vxworks.h (VX_LGCC_EH_SO0, VX_LGCC_EH_SO1): New + internal macros. + (VXWORKS_LIBGCC_SPEC): Use them and document. + +2022-10-11 Martin Liska <mliska@suse.cz> + + * gimple-range-op.cc: Add override keyword. + +2022-10-11 Eugene Rozenfeld <erozen@microsoft.com> + + PR debug/107193 + * tree-cfg.cc (assign_discriminators): Move declaration of cur_locus_e + out of the loop. + +2022-10-11 Liwei Xu <liwei.xu@intel.com> + liuhongt <hongtao.liu@intel.com> + + PR tree-optimization/54346 + * match.pd: Merge the index of VCST then generates the new vec_perm. + +2022-10-11 Jeff Law <jeffreyalaw@gmail.com> + + PR rtl-optimization/107182 + * cfgrtl.cc (fixup_reorder_chain): When optimizing a jump to a + return, clear EDGE_CROSSING on the appropriate edge. + +2022-10-11 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-vector-builtins.cc (struct vector_type_info): Move + from config/riscv/riscv-vector-builtins.h. + (DEF_RVV_TYPE): Change USER_NAME to NAME. + (register_vector_type): Change user_name to name. + * config/riscv/riscv-vector-builtins.def (DEF_RVV_TYPE): Change + USER_NAME to NAME. + * config/riscv/riscv-vector-builtins.h (struct vector_type_info): Move + to riscv-vector-builtins.cc. + (DEF_RVV_TYPE): Change USER_NAME to NAME. + +2022-10-11 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config/riscv/riscv.md: Add vsetvl instruction type. + +2022-10-10 Nathan Sidwell <nathan@acm.org> + + * common.opt (-fabi-version=): Document 18. + * doc/invoke.texi (-fabi-version): Document 18. + +2022-10-10 Andrea Corallo <andrea.corallo@arm.com> + + PR other/99723 + * toplev.cc (toplev::main): Don't run self tests in case of + previous error. + +2022-10-10 Kito Cheng <kito.cheng@sifive.com> + + * config/riscv/riscv-c.cc: Add newline to the end of file. + +2022-10-10 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (class foperator_identity): Make members public. + (class foperator_equal): Same. + (class foperator_not_equal): Same. + (class foperator_lt): Same. + (class foperator_le): Same. + (class foperator_gt): Same. + (class foperator_ge): Same. + (class foperator_unordered): Same. + (class foperator_ordered): Same. + +2022-10-10 Aldy Hernandez <aldyh@redhat.com> + + * value-range.h (frange::maybe_isnan): New. + +2022-10-10 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (foperator_not_equal::op1_range): Set NAN on + TRUE side for x != x. + +2022-10-10 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (foperator_unordered::op1_range): Set NAN when + operands are equal and result is TRUE. + +2022-10-10 Aldy Hernandez <aldyh@redhat.com> + + * range.h (range_true): Return int_range<2>. + (range_false): Same. + (range_true_and_false): Same. + +2022-10-10 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-op.cc: Add op1_range entry for __builtin_signbit. + +2022-10-10 liuhongt <hongtao.liu@intel.com> + + PR target/107185 + * config/i386/i386.md (lrint<MODEF:mode><SWI48:mode>2): Swap + predicate of operands[0] and operands[1]. + +2022-10-10 Claudiu Zissulescu <claziss@gmail.com> + + * common/config/arc/arc-common.cc (arc_option_optimization_table): + Remove Rcq and Rcw options. + * config/arc/arc.opt (mRcq): Ignore option, preserve it for + backwards compatibility. + (mRcw): Likewise. + * doc/invoke.texi (mRcw, mRcq): Update document. + +2022-10-10 Claudiu Zissulescu <claziss@gmail.com> + + * config/arc/arc.cc (arc_check_short_reg_p): New function. + (arc_address_cost): Replace satisfies_constraint_Rcq with the + above new function. + (arc_output_addsi): Likewise. + (split_addsi): Likewise. + (split_subsi): Likewise. + * config/arc/arc.md (movqi_insn): Remove Rcq constraint. + (movhi_insn): Likewise. + (movsi_insn): Likewise. + (tst_movb): Likewise. + (tst): Likewise. + (tst_bitfield): Likewise. + (abssi2): Likewise. + (addsi3_mixed): Likewise. + (mulhisi3_reg): Likewise. + (umulhisi3_reg): Likewise. + (mulsi_600): Likewise. + (mul64): Likewise. + (subsi3_insn): Likewise. + (bicsi3_insn): Likewise. + (xorsi3): Likewise. + (negsi2): Likewise. + (one_cmplsi2): Likewise. + (lshrsi3_insn): Likewise. + (cmpsi_cc_insn_mixed): Likewise. + (cmpsi_cc_zn_insn): Likewise. + (btst): Likewise. + (cmpsi_cc_z_insn): Likewise. + (cmpsi_cc_c_insn): Likewise. + (indirect_jump): Likewise. + (casesi_jump): Likewise. + (call_i): Likewise. + (call_value_i): Likewise. + (bbit): Likewise. + (abssf2): Likewise. + (ashlsi2_cnt1): Likewise. + (lshrsi3_cnt1): Likewise. + (ashrsi3_cnt1): Likewise. + * config/arc/constraints.md (Rcq): Remove. + +2022-10-10 Claudiu Zissulescu <claziss@gmail.com> + + * config/arc/arc.md (smaxsi3): Remove Rcw. + (sminsi3): Likewise. + (addsi3_mixed): Likewise. + (add_f_2): Likewise. + (subsi3_insn): Likewise. + (sub_f): Likewise. + (sub_n): Likewise. + (bset): Likewise. + (bxor): Likewise. + (bclr): Likewise. + (bset_insn): Likewise. + (bxor_insn): Likewise. + (bclr_insn): Likewise. + (bmsk_insn): Likewise. + (bicsi3_insn): Likewise. + (xorsi3): Likewise. + (negsi2): Likewise. + (lshrsi3_insn): Likewise. + (abssf2): Likewise. + (negsf2): Likewise. + * config/arc/constraints.md(Rcw): Remove it. + +2022-10-10 Claudiu Zissulescu <claziss@gmail.com> + + * config/arc/arc.md(mulsi3_700): Remove Rcr. + (mulsi3_highpart): Likewise. + (umulsi3_highpart_i): Likewise. + (umulsi3_highpart_int): Likewise. + (macd): Likewise. + (macdu): Likewise. + * config/arc/constraints.md (Rcr): Remove it. + +2022-10-10 Claudiu Zissulescu <claziss@gmail.com> + + * config/arc/arc.cc (arc_save_callee_enter): Use negative offsets. + +2022-10-09 Dimitar Dimitrov <dimitar@dinux.eu> + + PR target/106562 + * config/pru/pru-protos.h (pru_noteq_condition): New + function declaration. + * config/pru/pru.cc (pru_noteq_condition): New function. + * config/pru/pru.md (cbranchdi4): Define new pattern. + +2022-10-09 Dimitar Dimitrov <dimitar@dinux.eu> + + * config/pru/pru.md (lshrdi3): New expand pattern. + (ashldi3): Ditto. + +2022-10-09 YunQiang Su <yunqiang.su@cipunited.com> + + * config.gcc: set with_arch to default_mips_arch if no defined. + * config/mips/driver-native.cc (host_detect_local_cpu): + try getauxval(AT_BASE_PLATFORM) and _MIPS_ARCH, too. + pass -mnan=2008 if __mips_nan2008__ is defined. + * config.in: define HAVE_SYS_AUXV_H and HAVE_GETAUXVAL. + * configure.ac: detect sys/auxv.h and getauxval. + * configure: regenerated. + +2022-10-07 Eugene Rozenfeld <erozen@microsoft.com> + + * tree-cfg.cc (assign_discriminators): Set discriminators for call stmts + on the same line within the same basic block. + +2022-10-07 Qing Zhao <qing.zhao@oracle.com> + + PR tree-optimization/101836 + * tree-object-size.cc (addr_object_size): Use array_at_struct_end_p + to determine a flexible array member reference. + +2022-10-07 Qing Zhao <qing.zhao@oracle.com> + + * doc/extend.texi: Document strict_flex_array attribute. + * doc/invoke.texi: Document -fstrict-flex-arrays[=n] option. + * print-tree.cc (print_node): Print new bit decl_not_flexarray. + * tree-core.h (struct tree_decl_common): New bit field + decl_not_flexarray. + * tree-streamer-in.cc (unpack_ts_decl_common_value_fields): Stream + in new bit decl_not_flexarray. + * tree-streamer-out.cc (pack_ts_decl_common_value_fields): Stream + out new bit decl_not_flexarray. + * tree.cc (array_at_struct_end_p): Update it with the new bit field + decl_not_flexarray. + * tree.h (DECL_NOT_FLEXARRAY): New flag. + +2022-10-07 Olivier Hainque <hainque@adacore.com> + + * config/vxworks/_vxworks-versions.h: Use OS specific + paths in #include of version.h. + +2022-10-07 Martin Liska <mliska@suse.cz> + + * opts.cc (finish_options): Print sorry message only + for -flive-patching=inline-only-static. + +2022-10-07 Jason Merrill <jason@redhat.com> + + * gimplify.cc (gimplify_modify_expr_rhs): Don't optimize + x = *(A*)&<expr> to x = <expr> for a TREE_ADDRESSABLE type. + +2022-10-07 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107153 + * tree-cfg.cc (gimple_duplicate_sese_tail): Do not update + SSA form here. + * tree-parloops.cc (gen_parallel_loop): Update SSA form + after to-exit-first transform, no PHI insertion is necessary. + (pass_parallelize_loops::execute): Force re-write of the + virtual operand SSA web. + +2022-10-07 Jonathan Wakely <jwakely@redhat.com> + + * value-range.cc (irange::irange_contains_p): Fix comment typo. + +2022-10-07 Eric Botcazou <ebotcazou@adacore.com> + + * function.cc (thread_prologue_and_epilogue_insns): Update only + entry and exit blocks when not optimizing. Remove dead statement. + +2022-10-07 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (irange::irange_set): Convert nonzero mask to + tree. + (irange::irange_set_anti_range): Same. + (irange::set): Same. + (irange::verify_range): Same. + (irange::contains_p): Same. + (irange::invert): Same. + (irange::set_range_from_nonzero_bits): Same. + (irange::set_nonzero_bits): Same. + (mask_to_wi): Same. + (irange::intersect_nonzero_bits): Same. + (irange::union_nonzero_bits): Same. + * value-range.h (irange::varying_compatible_p): Same. + (gt_ggc_mx): Same. + (gt_pch_nx): Same. + (irange::set_undefined): Same. + (irange::set_varying): Same. + +2022-10-07 Martin Liska <mliska@suse.cz> + + * config/i386/i386-protos.h (ix86_binary_operator_ok): Add array + size to function parameter. + (ix86_unary_operator_ok): Likewise. + +2022-10-07 Martin Liska <mliska@suse.cz> + + * auto-profile.cc (get_inline_stack): Remove unused variable. + +2022-10-07 Jakub Jelinek <jakub@redhat.com> + + * ipa-prop.h (ipa_constant_data): Fix comment typo. + * value-range.cc (irange::irange_contains_p): Likewise. + * value-relation.cc (dom_oracle::set_one_relation): Likewise. + * gimple-predicate-analysis.cc (predicate::simplify_4): Likewise. + * tree-inline.cc (remap_ssa_name): Likewise. + +2022-10-07 Jakub Jelinek <jakub@redhat.com> + + * attribs.h (is_attribute_namespace_p): New inline function. + (lookup_attribute): Document meaning of ATTR_NS equal to "". + * attribs.cc (remove_attribute): Use is_attribute_namespace_p. + (private_lookup_attribute): For ATTR_NS "" match either standard + attribute or "gnu" namespace one. + +2022-10-07 Olivier Hainque <hainque@adacore.com> + + * config/vxworks.h (DWARF_VERSION_DEFAULT): Adjust from + 4 to 3 for VxWorks >= 7. + +2022-10-07 Olivier Hainque <hainque@adacore.com> + + * defaults.h (DWARF_DEFAULT_VERSION): Define if not + defined already. + * common.opt (gdwarf-): Use it. + * doc/tm.texi.in (DWARF_DEFAULT_VERSION): Document. + * doc/tm.texi: Update accordingly. + * config/vxworks.h (DWARF_DEFAULT_VERSION): Redefine. + * config/vxworks.cc: Remove code setting dwarf_version, now + handled by the DWARF_DEFAULT_VERSION redefinition. + +2022-10-07 Olivier Hainque <hainque@adacore.com> + + * ginclude/stddef.h: #undef offsetof before #define. + +2022-10-06 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/107170 + * vr-values.cc (vr_values::range_of_expr): Do not die on + unsupported types. + +2022-10-06 Joseph Myers <joseph@codesourcery.com> + + * doc/invoke.texi (-fno-asm): Update description of effects on + typeof keyword. + +2022-10-06 Eric Botcazou <ebotcazou@adacore.com> + + * gimple-loop-jam.cc (tree_loop_unroll_and_jam): Bail out for a self + dependency that is a write-after-write if the access function is not + affine or constant. + +2022-10-06 Eric Botcazou <ebotcazou@adacore.com> + + * df-scan.cc (df_ref_create_structure): Minor cleanup. + +2022-10-06 Richard Biener <rguenther@suse.de> + + PR middle-end/107115 + * expr.cc (store_expr): Check mems_same_for_tbaa_p before + eliding a seemingly redundant store. + +2022-10-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/atomics.md (*atomic_load<ALLX:mode>_zext<SD_HSDI:mode>): + New pattern. + +2022-10-06 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/aarch64/aarch64-cores.def (AARCH64_CORE): Update + Ampere-1 core entry. + +2022-10-06 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/aarch64/driver-aarch64.cc (readline): Fix off-by-one. + +2022-10-06 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107107 + * tree-ssa-sccvn.cc (visit_reference_op_store): Do not + affect value-numbering when doing the tail merging + MODIFY_EXPR lookup. + +2022-10-06 Claudiu Zissulescu <claziss@synopsys.com> + + * config/arc/linux.h (LINK_SPEC): Remove max-page-size and + common-pave-size. + +2022-10-06 Jakub Jelinek <jakub@redhat.com> + + PR c++/106654 + * internal-fn.def (ASSUME): New internal function. + * internal-fn.h (expand_ASSUME): Declare. + * internal-fn.cc (expand_ASSUME): Define. + * gimplify.cc (gimplify_call_expr): Gimplify IFN_ASSUME. + * fold-const.h (simple_condition_p): Declare. + * fold-const.cc (simple_operand_p_2): Rename to ... + (simple_condition_p): ... this. Remove forward declaration. + No longer static. Adjust function comment and fix a typo in it. + Adjust recursive call. + (simple_operand_p): Adjust function comment. + (fold_truth_andor): Adjust simple_operand_p_2 callers to call + simple_condition_p. + * doc/extend.texi: Document assume attribute. Move fallthrough + attribute example to its section. + +2022-10-06 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> + + PR rtl-optimization/107088 + * cselib.cc (new_cselib_val): Skip BImode while keeping track of + subvalue relations. + +2022-10-06 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (frange::set): Call set_nan unconditionally. + (range_tests_nan): Adjust tests. + (range_tests_signed_zeros): Same. + (range_tests_floats): Same. + * value-range.h (frange::update_nan): Guard with HONOR_NANS. + (frange::set_nan): Set undefined if !HONOR_NANS. + +2022-10-06 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (foperator_lt::fold_range): Remove extra check + to finite_operands_p. + (foperator_le::fold_range): Same. + (foperator_gt::fold_range): Same. + (foperator_ge::fold_range): Same. + +2022-10-06 Aldy Hernandez <aldyh@redhat.com> + + * value-range-pretty-print.cc (vrange_printer::print_real_value): + Avoid printing INF and NAN twice. + +2022-10-05 Segher Boessenkool <segher@kernel.crashing.org> + + * config/rs6000/constraints.md (wD): Delete. + * doc/md.texi (Machine Constraints): Adjust. + +2022-10-05 Segher Boessenkool <segher@kernel.crashing.org> + + * config/rs6000/vsx.md (vsx_extract_<mode>): Replace define_insn by a + define_expand. Split the contents to... + (*vsx_extract_<mode>_0): ... this. Rewrite. + (*vsx_extract_<mode>_1): ... and this. Rewrite. + +2022-10-05 Segher Boessenkool <segher@kernel.crashing.org> + + * config/rs6000/vsx.md (*vsx_extract_<mode>_store): Use "n" instead of + "wD" constraint. + +2022-10-05 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/107060 + * doc/analyzer.texi (__analyzer_get_unknown_ptr): Document. + +2022-10-05 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config.gcc: Add riscv_vector.h. + * config/riscv/riscv-builtins.cc: Add RVV builtin types support. + * config/riscv/riscv-c.cc (riscv_pragma_intrinsic): New function. + (riscv_register_pragmas): Ditto. + * config/riscv/riscv-protos.h (riscv_register_pragmas): Ditto. + (init_builtins): Move declaration from riscv-vector-builtins.h to riscv-protos.h. + (mangle_builtin_type): Ditto. + (verify_type_context): Ditto. + (handle_pragma_vector): New function. + * config/riscv/riscv-vector-builtins.cc (GTY): New variable. + (register_vector_type): New function. + (init_builtins): Add RVV builtin types support. + (handle_pragma_vector): New function. + * config/riscv/riscv-vector-builtins.h (GCC_RISCV_V_BUILTINS_H): Change + name according to file name. + (GCC_RISCV_VECTOR_BUILTINS_H): Ditto. + (init_builtins): Remove declaration in riscv-vector-builtins.h. + (mangle_builtin_type): Ditto. + (verify_type_context): Ditto. + * config/riscv/riscv.cc: Adjust for RVV builtin types support. + * config/riscv/riscv.h (REGISTER_TARGET_PRAGMAS): New macro. + * config/riscv/t-riscv: Remove redundant file including. + * config/riscv/riscv_vector.h: New file. + +2022-10-05 Aldy Hernandez <aldyh@redhat.com> + + * range-op.cc (operator_cast::fold_range): Handle truncating casts + for nonzero masks. + +2022-10-05 Martin Liska <mliska@suse.cz> + + PR c/107156 + * attribs.h (lookup_attribute_by_prefix): Support the attribute + starting with underscore (_Noreturn). + +2022-10-05 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/107052 + * gimple-range-op.cc (cfn_popcount::fold_range): Take into account + nonzero bit mask. + +2022-10-05 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/107052 + * range-op.cc (operator_cast::fold_range): Set nonzero mask. + +2022-10-05 Eric Botcazou <ebotcazou@adacore.com> + + PR tree-optimization/106698 + * pointer-query.cc (handle_array_ref): Fix handling of low bound. + +2022-10-05 Vineet Gupta <vineetg@rivosinc.com> + + * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): + Remove __riscv_cmodel_pic, that deprecated in last version. + +2022-10-05 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/107072 + * Makefile.in (ANALYZER_OBJS): Add analyzer/call-summary.o. + +2022-10-04 Jakub Jelinek <jakub@redhat.com> + + * attribs.h (remove_attribute): Declare overload with additional + attr_ns argument. + (private_lookup_attribute): Declare overload with additional + attr_ns and attr_ns_len arguments. + (lookup_attribute): New overload with additional attr_ns argument. + * attribs.cc (remove_attribute): New overload with additional + attr_ns argument. + (private_lookup_attribute): New overload with additional + attr_ns and attr_ns_len arguments. + +2022-10-04 Jakub Jelinek <jakub@redhat.com> + + * attribs.cc (handle_ignored_attributes_option, decl_attributes, + common_function_versions): Use auto_diagnostic_group. + +2022-10-04 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (irange::set_nonzero_bits): Remove assert. + +2022-10-04 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64.h (AARCH64_ISA_RCPC): New macro. + * config/aarch64/aarch64-arches.def (armv8.3-a): Include RCPC. + * config/aarch64/aarch64-cores.def (thunderx3t110, zeus, neoverse-v1) + (neoverse-512tvb, saphira): Remove RCPC from these Armv8.3-A+ cores. + * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Define + __ARM_FEATURE_RCPC when appropriate. + +2022-10-04 Tobias Burnus <tobias@codesourcery.com> + + * doc/invoke.texi (-fopenmp): Mention C++ attribut syntax. + (-fopenmp-simd): Likewise; update permitted directives. + +2022-10-04 Tobias Burnus <tobias@codesourcery.com> + + * doc/install.texi (Specific): Add missing items to bullet list. + (amdgcn): Update LLVM requirements, use version not date for newlib. + (nvptx): Use version not git hash for newlib. + +2022-10-04 Aldy Hernandez <aldyh@redhat.com> + + * value-range-storage.cc (irange_storage_slot::set_irange): Remove + special case. + * value-range.cc (irange::irange_set): Adjust for nonzero mask + being a wide int. + (irange::irange_set_anti_range): Same. + (irange::set): Same. + (irange::verify_range): Same. + (irange::legacy_equal_p): Same. + (irange::operator==): Same. + (irange::contains_p): Same. + (irange::legacy_intersect): Same. + (irange::legacy_union): Same. + (irange::irange_single_pair_union): Call union_nonzero_bits. + (irange::irange_union): Same. + (irange::irange_intersect): Call intersect_nonzero_bits. + (irange::intersect): Adjust for nonzero mask being a wide int. + (irange::invert): Same. + (irange::set_nonzero_bits): Same. + (irange::get_nonzero_bits_from_range): New. + (irange::set_range_from_nonzero_bits): New. + (irange::get_nonzero_bits): Adjust for nonzero mask being a wide + int. + (irange::intersect_nonzero_bits): Same. + (irange::union_nonzero_bits): Same. + (range_tests_nonzero_bits): Remove test. + * value-range.h (irange::varying_compatible_p): Adjust for nonzero + mask being a wide int. + (gt_ggc_mx): Same. + (gt_pch_nx): Same. + (irange::set_undefined): Same. + (irange::set_varying): Same. + (irange::normalize_kind): Same. + +2022-10-04 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/107130 + * gimple-range-op.cc (class cfn_popcount): Call op_cfn_ffs. + (class cfn_ffs): New. + (gimple_range_op_handler::maybe_builtin_call): Separate out + CASE_CFN_FFS into its own case. + +2022-10-03 Sergei Trofimovich <siarheit@google.com> + + * config/i386/t-i386: Add build-time dependencies against + i386-builtin-types.inc to i386-builtins.o, i386-expand.o, + i386-features.o. + +2022-10-03 Andrew Stubbs <ams@codesourcery.com> + + * config/gcn/gcn-valu.md (while_ultsidi): Limit mask length using + operand 3. + * doc/md.texi (while_ult): Document new operand 3 usage. + * internal-fn.cc (expand_while_optab_fn): Set operand 3 when lhs_type + maps to a non-vector mode. + +2022-10-03 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/107109 + * range-op.cc (adjust_op1_for_overflow): Don't process undefined. + +2022-10-03 Christophe Lyon <christophe.lyon@arm.com> + + * config/arm/mve.md (mve_vrev64q_m_<supf><mode>): Add early + clobber. + (mve_vrev64q_m_f<mode>): Likewise. + +2022-10-03 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (irange::set_nonzero_bits): Do not pessimize range. + (range_tests_nonzero_bits): New test. + +2022-10-03 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (irange::operator==): Early bail on m_num_ranges + equal to 0. + +2022-10-03 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (irange::legacy_equal_p): Remove nonozero mask + check when comparing VR_VARYING ranges. + +2022-10-03 Aldy Hernandez <aldyh@redhat.com> + + * ipa-prop.cc (struct ipa_vr_ggc_hash_traits): Do not compare + incompatible ranges in ipa-prop. + +2022-10-02 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/107121 + * tree-cfg.cc (verify_gimple_call): Fix a typo in diagnostics, + DEFFERED_INIT -> DEFERRED_INIT. + +2022-10-02 Marc Poulhiès <poulhies@adacore.com> + + * config/vxworks-driver.cc: New. + * config.gcc (*vxworks*): Add vxworks-driver.o in extra_gcc_objs. + * config/t-vxworks: Add vxworks-driver.o. + * config/vxworks.h (GCC_DRIVER_HOST_INITIALIZATION): New. + +2022-10-02 Olivier Hainque <hainque@adacore.com> + + * config/vxworks.h (VX_CRTBEGIN_SPEC, VX_CRTEND_SPEC): If + HAVE_INITFINI_ARRAY_SUPPORT, pick crtstuff objects regardless + of ENABLE_SHARED_LIBGCC. + +2022-10-01 Stafford Horne <shorne@gmail.com> + + * config/or1k/or1k.cc (TARGET_HAVE_TLS): Only define if + HAVE_AS_TLS is defined. + +2022-10-01 Julian Brown <julian@codesourcery.com> + + * gimplify.cc (omp_group_base): Fix IF_PRESENT (no_create) + handling. + +2022-10-01 Jeff Law <jeffreyalaw@gmail.com> + + * config/h8300/h8300.md (HSI2): New iterator. + (eqne_invert): Similarly. + * config/h8300/testcompare.md (testhi_upper_z): New pattern. + (cmpqi_z, cmphi_z, cmpsi_z): Likewise. + (store_z_qi, store_z_i_qi, store_z_hi, store_z_hi_sb): New + define_insn_and_splits and/or define_insns. + (store_z_hi_neg, store_z_hi_and, store_z_<mode>): Likewise. + (store_z_<mode>_neg, store_z_<mode>_and, store_z): Likewise. + +2022-10-01 Jeff Law <jeffreyalaw@gmail.com> + + * tree-ssa-dom.cc (record_edge_info): Install correct version of + patch. + +2022-10-01 Eugene Rozenfeld <erozen@microsoft.com> + + * dwarf2out.cc (add_call_src_coords_attributes): Emit discriminators for inlined call sites. + +2022-09-30 Jeff Law <jeffreyalaw@gmail.com> + + * tree-ssa-dom.cc (single_block_loop_p): New function. + (record_edge_info): Also record equivalences for the outgoing + edge of a single block loop where the condition is an invariant. + +2022-09-30 Jeff Law <jeffreyalaw@gmail.com> + + * tree-ssa-dom.cc (free_dom_edge_info): Clear e->aux too. + (free_all_edge_infos): Do not clear e->aux here. + +2022-09-30 H.J. Lu <hjl.tools@gmail.com> + + * target.def (TARGET_C_EXCESS_PRECISION): Document + -fexcess-precision=16. + +2022-09-30 Palmer Dabbelt <palmer@rivosinc.com> + + * doc/tm.texi (TARGET_C_EXCESS_PRECISION): Add 16. + +2022-09-30 Palmer Dabbelt <palmer@rivosinc.com> + + PR target/106815 + * config/riscv/riscv.cc (riscv_excess_precision): Add support + for EXCESS_PRECISION_TYPE_FLOAT16. + +2022-09-30 Jakub Jelinek <jakub@redhat.com> + + PR c++/107080 + * config/arm/arm.cc (arm_mangle_type): Mangle just __fp16 as Dh + and _Float16 as DF16_. + * config/csky/csky.cc (csky_init_builtins): Fix a comment typo. + (csky_mangle_type): Mangle __fp16 as Dh and _Float16 as DF16_ + rather than mangling __fp16 as __fp16. + +2022-09-30 Lewis Hyatt <lhyatt@gmail.com> + + PR preprocessor/69543 + * tree-ssa-uninit.cc (warn_uninit): Stop stripping macro tracking + information away from the diagnostic location. + (maybe_warn_read_write_only): Likewise. + (maybe_warn_operand): Likewise. + +2022-09-30 Jakub Jelinek <jakub@redhat.com> + + PR c++/107080 + * config/aarch64/aarch64.cc (aarch64_mangle_type): Mangle just __fp16 + as Dh and _Float16 as DF16_. + +2022-09-30 Jakub Jelinek <jakub@redhat.com> + + PR c++/107080 + * config/i386/i386.cc (ix86_mangle_type): Always return NULL + for float128_type_node or float64x_type_node, don't check + float128t_type_node later on. + * config/ia64/ia64.cc (ia64_mangle_type): Always return NULL + for float128_type_node or float64x_type_node. + * config/rs6000/rs6000.cc (rs6000_mangle_type): Likewise. + Don't check float128_type_node later on. + * config/s390/s390.cc (s390_mangle_type): Don't use + TYPE_MAIN_VARIANT on type which was set to TYPE_MAIN_VARIANT + a few lines earlier. + +2022-09-30 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com> + Yvan ROUX <yvan.roux@foss.st.com> + + * doc/sourcebuild.texi: Document new vma_equals_lma effective + target check. + +2022-09-30 Jiawei <jiawei@iscas.ac.cn> + + * config/riscv/riscv.cc (riscv_file_start): New .option. + * config/riscv/riscv.opt: New options. + * doc/invoke.texi: New definations. + +2022-09-30 Kewen Lin <linkw@linux.ibm.com> + + PR target/99888 + PR target/105649 + * doc/invoke.texi (option -fpatchable-function-entry): Adjust the + documentation for PowerPC ELFv2 ABI dual entry points. + * config/rs6000/rs6000-internal.h + (rs6000_print_patchable_function_entry): New function declaration. + * config/rs6000/rs6000-logue.cc (rs6000_output_function_prologue): + Support patchable-function-entry by emitting nops before and after + local entry for the function that needs global entry. + * config/rs6000/rs6000.cc (rs6000_print_patchable_function_entry): Skip + the function that needs global entry till global entry has been + emitted. + * config/rs6000/rs6000.h (struct machine_function): New bool member + global_entry_emitted. + +2022-09-30 Richard Biener <rguenther@suse.de> + + PR tree-optimization/107095 + * tree-ssa-dse.cc (initialize_ao_ref_for_dse): Use data arg + for .MASK_STORE size. + +2022-09-29 Andrew MacLeod <amacleod@redhat.com> + + * range-op.cc (plus_minus_ranges): New. + (adjust_op1_for_overflow): New. + (operator_plus::op1_range): Use new adjustment. + (operator_plus::op2_range): Ditto. + (operator_minus::op1_range): Ditto. + * value-relation.h (relation_lt_le_gt_ge_p): New. + +2022-09-29 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-gori.cc (gori_compute::refine_using_relation): New. + (gori_compute::compute_operand1_range): Invoke + refine_using_relation when applicable. + (gori_compute::compute_operand2_range): Ditto. + * gimple-range-gori.h (class gori_compute): Adjust prototypes. + +2022-09-29 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-gori.cc (ori_compute::compute_operand_range): + Create a relation record and pass it along when possible. + (gori_compute::compute_operand1_range): Pass relation along. + (gori_compute::compute_operand2_range): Ditto. + (gori_compute::compute_operand1_and_operand2_range): Ditto. + * gimple-range-gori.h (class gori_compute): Adjust prototypes. + * gimple-range-op.cc (gimple_range_op_handler::calc_op1): Pass + relation to op1_range call. + (gimple_range_op_handler::calc_op2): Pass relation to op2_range call. + * gimple-range-op.h (class gimple_range_op_handler): Adjust + prototypes. + +2022-09-29 Andrew MacLeod <amacleod@redhat.com> + + * value-relation.cc (class value_relation): Move to .h file. + (value_relation::set_relation): Ditto. + (value_relation::value_relation): ditto. + * value-relation.h (class value_relation): Move from .cc file. + (value_relation::set_relation): Ditto + (value_relation::value_relation): Ditto. + +2022-09-29 Andrew MacLeod <amacleod@redhat.com> + + * range-op.cc (operator_minus::op2_range): Check for undefined. + (operator_mult::op1_range): Ditto. + (operator_exact_divide::op1_range): Ditto. + (operator_lshift::op1_range): Ditto. + (operator_rshift::op1_range): Ditto. + (operator_cast::op1_range): Ditto. + (operator_bitwise_and::op1_range): Ditto. + (operator_bitwise_or::op1_range): Ditto. + (operator_trunc_mod::op1_range): Ditto. + (operator_trunc_mod::op2_range): Ditto. + (operator_bitwise_not::op1_range): Ditto. + (pointer_or_operator::op1_range): Ditto. + (range_op_handler::op1_range): Ditto. + (range_op_handler::op2_range): Ditto. + +2022-09-29 Andrew Stubbs <ams@codesourcery.com> + + * config/gcn/gcn.cc (gcn_simd_clone_compute_vecsize_and_simdlen): + Remove unused elt_bits variable. + +2022-09-29 Olivier Hainque <hainque@adacore.com> + + * config/vxworks.h: Add comment on our use of + HAVE_INITFINI_ARRAY_SUPPORT. + +2022-09-29 Olivier Hainque <hainque@adacore.com> + + * config/aarch64/t-aarch64-vxworks: Request multilib + variants for mcmodel=large. + +2022-09-29 Olivier Hainque <hainque@adacore.com> + + * config/rs6000/vxworks.h (TARGET_FLOAT128_ENABLE_TYPE): Remove + resetting to 0. + +2022-09-29 Olivier Hainque <hainque@adacore.com> + + * config/vx-common.h (DWARF2_UNWIND_INFO): #define to 0 + when ARM_UNWIND_INFO is set. + +2022-09-29 Julian Brown <julian@codesourcery.com> + + PR middle-end/107028 + * gimplify.cc (omp_check_mapping_compatibility, + oacc_resolve_clause_dependencies): New functions. + (omp_accumulate_sibling_list): Remove redundant duplicate clause + detection for OpenACC. + (build_struct_sibling_lists): Skip deleted groups. Don't build sibling + list for struct variables that are fully mapped on the same directive + for OpenACC. + (gimplify_scan_omp_clauses): Call oacc_resolve_clause_dependencies. + +2022-09-29 Jose E. Marchesi <jose.marchesi@oracle.com> + + PR middle-end/25521 + * varasm.cc (categorize_decl_for_section): Place `const volatile' + objects in read-only sections. + (default_select_section): Likewise. + +2022-09-29 Richard Sandiford <richard.sandiford@arm.com> + + * tree-data-ref.cc (dr_may_alias_p): Use to_poly_widest instead + of to_widest. + +2022-09-29 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64.h (TARGET_CRYPTO, TARGET_SHA3, TARGET_SM4) + (TARGET_DOTPROD): Don't depend on TARGET_SIMD. + (TARGET_AES, TARGET_SHA2): Likewise. Remove TARGET_CRYPTO test. + (TARGET_FP_F16INST): Don't depend on TARGET_FLOAT. + (TARGET_SVE2, TARGET_SVE_F32MM, TARGET_SVE_F64MM): Don't depend + on TARGET_SVE. + (TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3) + (TARGET_SVE2_SM4): Don't depend on TARGET_SVE2. + (TARGET_F32MM, TARGET_F64MM): Delete. + * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Guard + float macros with just TARGET_FLOAT rather than TARGET_FLOAT + || TARGET_SIMD. + * config/aarch64/aarch64-simd.md (copysign<mode>3): Depend + only on TARGET_SIMD, rather than TARGET_FLOAT && TARGET_SIMD. + (aarch64_crypto_aes<aes_op>v16qi): Depend only on TARGET_AES, + rather than TARGET_SIMD && TARGET_AES. + (aarch64_crypto_aes<aesmc_op>v16qi): Likewise. + (*aarch64_crypto_aese_fused): Likewise. + (*aarch64_crypto_aesd_fused): Likewise. + (aarch64_crypto_pmulldi): Likewise. + (aarch64_crypto_pmullv2di): Likewise. + (aarch64_crypto_sha1hsi): Likewise TARGET_SHA2. + (aarch64_crypto_sha1hv4si): Likewise. + (aarch64_be_crypto_sha1hv4si): Likewise. + (aarch64_crypto_sha1su1v4si): Likewise. + (aarch64_crypto_sha1<sha1_op>v4si): Likewise. + (aarch64_crypto_sha1su0v4si): Likewise. + (aarch64_crypto_sha256h<sha256_op>v4si): Likewise. + (aarch64_crypto_sha256su0v4si): Likewise. + (aarch64_crypto_sha256su1v4si): Likewise. + (aarch64_crypto_sha512h<sha512_op>qv2di): Likewise TARGET_SHA3. + (aarch64_crypto_sha512su0qv2di): Likewise. + (aarch64_crypto_sha512su1qv2di, eor3q<mode>4): Likewise. + (aarch64_rax1qv2di, aarch64_xarqv2di, bcaxq<mode>4): Likewise. + (aarch64_sm3ss1qv4si): Likewise TARGET_SM4. + (aarch64_sm3tt<sm3tt_op>qv4si): Likewise. + (aarch64_sm3partw<sm3part_op>qv4si): Likewise. + (aarch64_sm4eqv4si, aarch64_sm4ekeyqv4si): Likewise. + * config/aarch64/aarch64.md (<FLOATUORS:optab>dihf2) + (copysign<GPF:mode>3, copysign<GPF:mode>3_insn) + (xorsign<mode>3): Remove redundant TARGET_FLOAT condition. + +2022-09-29 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64.opt (aarch64_asm_isa_flags): New variable. + * config/aarch64/aarch64.h (aarch64_asm_isa_flags) + (aarch64_isa_flags): Redefine as read-only macros. + (TARGET_SIMD, TARGET_FLOAT, TARGET_SVE): Don't depend on + !TARGET_GENERAL_REGS_ONLY. + * common/config/aarch64/aarch64-common.cc + (aarch64_set_asm_isa_flags): New function. + (aarch64_handle_option): Call it when updating -mgeneral-regs. + * config/aarch64/aarch64-protos.h (aarch64_simd_switcher): Replace + m_old_isa_flags with m_old_asm_isa_flags. + (aarch64_set_asm_isa_flags): Declare. + * config/aarch64/aarch64-builtins.cc + (aarch64_simd_switcher::aarch64_simd_switcher) + (aarch64_simd_switcher::~aarch64_simd_switcher): Save and restore + aarch64_asm_isa_flags instead of aarch64_isa_flags. + * config/aarch64/aarch64-sve-builtins.cc + (check_required_extensions): Use aarch64_asm_isa_flags instead + of aarch64_isa_flags. + * config/aarch64/aarch64.cc (aarch64_set_asm_isa_flags): New function. + (aarch64_override_options, aarch64_handle_attr_arch) + (aarch64_handle_attr_cpu, aarch64_handle_attr_isa_flags): Use + aarch64_set_asm_isa_flags to set the ISA flags. + (aarch64_option_print, aarch64_declare_function_name) + (aarch64_start_file): Use aarch64_asm_isa_flags instead + of aarch64_isa_flags. + (aarch64_can_inline_p): Check aarch64_asm_isa_flags as well as + aarch64_isa_flags. + +2022-09-29 Richard Sandiford <richard.sandiford@arm.com> + + * common/config/aarch64/aarch64-common.cc (all_extensions): + Include the feature flag in flags_on and flags_off. + (aarch64_parse_extension): Update accordingly. + (aarch64_get_extension_string_for_isa_flags): Likewise. + +2022-09-29 Richard Sandiford <richard.sandiford@arm.com> + + * common/config/aarch64/aarch64-common.cc: Use aarch64_feature_flags + for feature flags throughout. + * config/aarch64/aarch64-protos.h: Likewise. + * config/aarch64/aarch64-sve-builtins.h: Likewise. + * config/aarch64/aarch64-sve-builtins.cc: Likewise. + * config/aarch64/aarch64.cc: Likewise. + * config/aarch64/aarch64.opt: Likewise. + * config/aarch64/driver-aarch64.cc: Likewise. + +2022-09-29 Richard Sandiford <richard.sandiford@arm.com> + + * common/config/aarch64/aarch64-common.cc (aarch64_option_extension) + (processor_name_to_arch, arch_to_arch_name): Remove const from + member variables. + (all_extensions, all_cores, all_architectures): Make a constexpr. + * config/aarch64/aarch64.cc (processor): Remove const from + member variables. + (all_architectures): Make a constexpr. + * config/aarch64/driver-aarch64.cc (aarch64_core_data) + (aarch64_arch_driver_info): Remove const from member variables. + (aarch64_cpu_data, aarch64_arches): Make a constexpr. + (get_arch_from_id): Return a pointer to const. + (host_detect_local_cpu): Update accordingly. + +2022-09-29 Richard Sandiford <richard.sandiford@arm.com> + + * common/config/aarch64/aarch64-common.cc (processor_name_to_arch) + (arch_to_arch_name): Use const char * instead of std::string. + +2022-09-29 Richard Sandiford <richard.sandiford@arm.com> + + * common/config/aarch64/aarch64-common.cc + (TARGET_OPTION_INIT_STRUCT): Delete. + (aarch64_option_extension): Remove is_synthetic_flag. + (all_extensions): Update accordingly. + (all_extensions_by_on, opt_ext, opt_ext_cmp): Delete. + (aarch64_option_init_struct, aarch64_contains_opt): Delete. + (aarch64_get_extension_string_for_isa_flags): Rewrite to use + all_extensions instead of all_extensions_on. + +2022-09-29 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-option-extensions.def: Switch to a new format. + * config/aarch64/aarch64-cores.def: Use the same format to specify + lists of features. + * config/aarch64/aarch64-arches.def: Likewise, moving that information + from aarch64.h. + * config/aarch64/aarch64-opts.h (aarch64_feature_flags): New typedef. + * config/aarch64/aarch64.h (aarch64_feature): New class enum. + Turn AARCH64_FL_* macros into constexprs, getting the definitions + from aarch64-option-extensions.def. Remove AARCH64_FL_FOR_* macros. + * common/config/aarch64/aarch64-common.cc: Include + aarch64-feature-deps.h. + (all_extensions): Update for new .def format. + (all_extensions_by_on, all_cores, all_architectures): Likewise. + * config/aarch64/driver-aarch64.cc: Include aarch64-feature-deps.h. + (aarch64_extensions): Update for new .def format. + (aarch64_cpu_data, aarch64_arches): Likewise. + * config/aarch64/aarch64.cc: Include aarch64-feature-deps.h. + (all_architectures, all_cores): Update for new .def format. + * config/aarch64/aarch64-sve-builtins.cc + (check_required_extensions): Likewise. + * config/aarch64/aarch64-feature-deps.h: New file. + +2022-09-29 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-option-extensions.def: Move crypto + after sha2. + +2022-09-29 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-option-extensions.def (dotprod): Depend + on fp as well as simd. + (sha3): Likewise. + (aes): Likewise. Make +noaes disable crypto. + (sha2): Likewise +nosha2. Also make +nosha2 disable sha3 and + sve2-sha3. + (sve2-sha3): Depend on sha2 as well as sha3. + +2022-09-29 Richard Sandiford <richard.sandiford@arm.com> + + PR target/107025 + * config/aarch64/aarch64.h (oAARCH64_FL_RCPC8_4): Delete. + (AARCH64_FL_FOR_V8_4A): Update accordingly. + (AARCH64_ISA_RCPC8_4): Use AARCH64_FL_V8_4A directly. + * config/aarch64/aarch64-cores.def (thunderx3t110): Remove + AARCH64_FL_RCPC8_4. + +2022-09-29 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-cores.def: Remove AARCH64_FL_FOR_<ARCH> + from the flags field. + * common/config/aarch64/aarch64-common.cc (all_cores): Add it + here instead. + * config/aarch64/aarch64.cc (all_cores): Likewise. + * config/aarch64/driver-aarch64.cc (all_cores): Likewise. + +2022-09-29 Richard Sandiford <richard.sandiford@arm.com> + + * config.gcc: Remove dead aarch64-option-extensions.def code. + * config/aarch64/aarch64-arches.def: Update comment. + +2022-09-29 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-arches.def: Add a leading "V" to the + ARCH_IDENT fields. + * config/aarch64/aarch64-cores.def: Update accordingly. + * common/config/aarch64/aarch64-common.cc (all_cores): Likewise. + * config/aarch64/aarch64.cc (all_cores): Likewise. + * config/aarch64/driver-aarch64.cc (aarch64_arches): Skip the + leading "V". + +2022-09-29 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64.h (AARCH64_FL_FOR_ARCH8): Rename to... + (AARCH64_FL_FOR_V8A): ...this. + (AARCH64_FL_FOR_ARCH8_1): Rename to... + (AARCH64_FL_FOR_V8_1A): ...this. + (AARCH64_FL_FOR_ARCH8_2): Rename to... + (AARCH64_FL_FOR_V8_2A): ...this. + (AARCH64_FL_FOR_ARCH8_3): Rename to... + (AARCH64_FL_FOR_V8_3A): ...this. + (AARCH64_FL_FOR_ARCH8_4): Rename to... + (AARCH64_FL_FOR_V8_4A): ...this. + (AARCH64_FL_FOR_ARCH8_5): Rename to... + (AARCH64_FL_FOR_V8_5A): ...this. + (AARCH64_FL_FOR_ARCH8_6): Rename to... + (AARCH64_FL_FOR_V8_6A): ...this. + (AARCH64_FL_FOR_ARCH8_7): Rename to... + (AARCH64_FL_FOR_V8_7A): ...this. + (AARCH64_FL_FOR_ARCH8_8): Rename to... + (AARCH64_FL_FOR_V8_8A): ...this. + (AARCH64_FL_FOR_ARCH8_R): Rename to... + (AARCH64_FL_FOR_V8R): ...this. + (AARCH64_FL_FOR_ARCH9): Rename to... + (AARCH64_FL_FOR_V9A): ...this. + (AARCH64_FL_FOR_ARCH9_1): Rename to... + (AARCH64_FL_FOR_V9_1A): ...this. + (AARCH64_FL_FOR_ARCH9_2): Rename to... + (AARCH64_FL_FOR_V9_2A): ...this. + (AARCH64_FL_FOR_ARCH9_3): Rename to... + (AARCH64_FL_FOR_V9_3A): ...this. + * common/config/aarch64/aarch64-common.cc (all_cores): Update + accordingly. + * config/aarch64/aarch64-arches.def: Likewise. + * config/aarch64/aarch64-cores.def: Likewise. + * config/aarch64/aarch64.cc (all_cores): Likewise. + +2022-09-29 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64.h (AARCH64_FL_V8_1, AARCH64_FL_V8_2) + (AARCH64_FL_V8_3, AARCH64_FL_V8_4, AARCH64_FL_V8_5, AARCH64_FL_V8_6) + (AARCH64_FL_V9, AARCH64_FL_V8_7, AARCH64_FL_V8_8, AARCH64_FL_V9_1) + (AARCH64_FL_V9_2, AARCH64_FL_V9_3): Add "A" to the end of the name. + (AARCH64_FL_V8_R): Rename to AARCH64_FL_V8R. + (AARCH64_FL_FOR_ARCH8_1, AARCH64_FL_FOR_ARCH8_2): Update accordingly. + (AARCH64_FL_FOR_ARCH8_3, AARCH64_FL_FOR_ARCH8_4): Likewise. + (AARCH64_FL_FOR_ARCH8_5, AARCH64_FL_FOR_ARCH8_6): Likewise. + (AARCH64_FL_FOR_ARCH8_7, AARCH64_FL_FOR_ARCH8_8): Likewise. + (AARCH64_FL_FOR_ARCH8_R, AARCH64_FL_FOR_ARCH9): Likewise. + (AARCH64_FL_FOR_ARCH9_1, AARCH64_FL_FOR_ARCH9_2): Likewise. + (AARCH64_FL_FOR_ARCH9_3, AARCH64_ISA_V8_2A, AARCH64_ISA_V8_3A) + (AARCH64_ISA_V8_4A, AARCH64_ISA_V8_5A, AARCH64_ISA_V8_6A): Likewise. + (AARCH64_ISA_V8R, AARCH64_ISA_V9A, AARCH64_ISA_V9_1A): Likewise. + (AARCH64_ISA_V9_2A, AARCH64_ISA_V9_3A): Likewise. + +2022-09-29 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64.h (AARCH64_ISA_V8_2, AARCH64_ISA_V8_3) + (AARCH64_ISA_V8_4, AARCH64_ISA_V8_5, AARCH64_ISA_V8_6) + (AARCH64_ISA_V9, AARCH64_ISA_V9_1, AARCH64_ISA_V9_2) + (AARCH64_ISA_V9_3): Add "A" to the end of the name. + (AARCH64_ISA_V8_R): Rename to AARCH64_ISA_V8R. + (TARGET_ARMV8_3, TARGET_JSCVT, TARGET_FRINT, TARGET_MEMTAG): Update + accordingly. + * common/config/aarch64/aarch64-common.cc + (aarch64_get_extension_string_for_isa_flags): Likewise. + * config/aarch64/aarch64-c.cc + (aarch64_define_unconditional_macros): Likewise. + +2022-09-29 Richard Sandiford <richard.sandiford@arm.com> + + * Makefile.in (GTFILES): Add OPTIONS_H_EXTRA. + +2022-09-29 Jakub Jelinek <jakub@redhat.com> + + PR bootstrap/107059 + * cppdefault.cc (cpp_include_defaults): If SYSROOT_HEADERS_SUFFIX_SPEC + isn't defined, add FIXED_INCLUDE_DIR entry with multilib flag 2 + before FIXED_INCLUDE_DIR entry with multilib flag 0. + * gcc.cc (do_spec_1): If multiarch_dir, add + include-fixed/multiarch_dir paths before include-fixed paths. + +2022-09-29 Martin Liska <mliska@suse.cz> + + PR driver/106897 + * common.opt: Add -gz=zstd value. + * configure.ac: Detect --compress-debug-sections=zstd + for both linker and assembler. + * configure: Regenerate. + * gcc.cc (LINK_COMPRESS_DEBUG_SPEC): Handle -gz=zstd. + (ASM_COMPRESS_DEBUG_SPEC): Likewise. + +2022-09-29 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105646 + * tree-ssa-uninit.cc (warn_uninitialized_vars): Pre-compute + the set of fallthru reachable blocks from function entry + and use that to determine wlims.always_executed. + +2022-09-29 liuhongt <hongtao.liu@intel.com> + + PR tree-optimization/107055 + * tree-vect-loop-manip.cc (vect_can_advance_ivs_p): Check for + nonlinear induction variables. + * tree-vect-loop.cc (vect_can_peel_nonlinear_iv_p): New + functions. + (vectorizable_nonlinear_induction): Put part codes into + vect_can_peel_nonlinear_iv_p. + * tree-vectorizer.h (vect_can_peel_nonlinear_iv_p): Declare. + +2022-09-28 Eugene Rozenfeld <erozen@microsoft.com> + + * basic-block.h: Remove discriminator from basic blocks. + * cfghooks.cc (split_block_1): Remove discriminator from basic blocks. + * final.cc (final_start_function_1): Switch from per-bb to per statement + discriminator. + (final_scan_insn_1): Don't keep track of basic block discriminators. + (compute_discriminator): Switch from basic block discriminators to + instruction discriminators. + (insn_discriminator): New function to return instruction discriminator. + (notice_source_line): Use insn_discriminator. + * gimple-pretty-print.cc (dump_gimple_bb_header): Remove dumping of + basic block discriminators. + * gimple-streamer-in.cc (input_bb): Remove reading of basic block + discriminators. + * gimple-streamer-out.cc (output_bb): Remove writing of basic block + discriminators. + * input.cc (make_location): Pass 0 discriminator to COMBINE_LOCATION_DATA. + (location_with_discriminator): New function to combine locus with + a discriminator. + (has_discriminator): New function to check if a location has a discriminator. + (get_discriminator_from_loc): New function to get the discriminator + from a location. + * input.h: Declarations of new functions. + * lto-streamer-in.cc (cmp_loc): Use discriminators in location comparison. + (apply_location_cache): Keep track of current discriminator. + (input_location_and_block): Read discriminator from stream. + * lto-streamer-out.cc (clear_line_info): Set current discriminator to + UINT_MAX. + (lto_output_location_1): Write discriminator to stream. + * lto-streamer.h: Add discriminator to cached_location. + Add current_discr to lto_location_cache. + Add current_discr to output_block. + * print-rtl.cc (print_rtx_operand_code_i): Print discriminator. + * rtl.h: Add extern declaration of insn_discriminator. + * tree-cfg.cc (assign_discriminator): New function to assign a unique + discriminator value to all statements in a basic block that have the given + line number. + (assign_discriminators): Assign discriminators to statement locations. + * tree-pretty-print.cc (dump_location): Dump discriminators. + * tree.cc (set_block): Preserve discriminator when setting block. + (set_source_range): Preserve discriminator when setting source range. + +2022-09-28 H.J. Lu <hjl.tools@gmail.com> + + PR target/107061 + * config/i386/predicates.md (encodekey128_operation): Check + XMM4-XMM6 as clobbered. + (encodekey256_operation): Likewise. + * config/i386/sse.md (encodekey128u32): Clobber XMM4-XMM6. + (encodekey256u32): Likewise. + +2022-09-28 Ju-Zhe Zhong <juzhe.zhong@rivai.ai> + + * config.gcc: Add riscv-vector-builtins.o. + * config/riscv/riscv-builtins.cc (riscv_init_builtins): Add RVV builtin function. + * config/riscv/riscv-protos.h (riscv_v_ext_enabled_vector_mode_p): New function. + * config/riscv/riscv.cc (ENTRY): New macro. + (riscv_v_ext_enabled_vector_mode_p): New function. + (riscv_mangle_type): Add RVV mangle. + (riscv_vector_mode_supported_p): Adjust RVV machine mode. + (riscv_verify_type_context): Add context check for RVV. + (riscv_vector_alignment): Add RVV alignment target hook support. + (TARGET_VECTOR_MODE_SUPPORTED_P): New target hook support. + (TARGET_VERIFY_TYPE_CONTEXT): Ditto. + (TARGET_VECTOR_ALIGNMENT): Ditto. + * config/riscv/t-riscv: Add riscv-vector-builtins.o + * config/riscv/riscv-vector-builtins.cc: New file. + * config/riscv/riscv-vector-builtins.def: New file. + * config/riscv/riscv-vector-builtins.h: New file. + * config/riscv/riscv-vector-switch.def: New file. + +2022-09-28 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> + + * var-tracking.cc (vt_add_function_parameter): Add entry values + up to maximal register mode. + +2022-09-28 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> + + * cselib.cc (new_cselib_val): Keep track of further subvalue + relations. + +2022-09-28 Andrea Corallo <andrea.corallo@arm.com> + + * config/arm/arm-c.cc (arm_cpu_builtins): Define + __ARM_FEATURE_AES and __ARM_FEATURE_SHA2. + +2022-09-28 Xi Ruoyao <xry111@xry111.site> + + PR tree-optimization/105414 + * config/loongarch/loongarch.md (UNSPEC_FMAX): New unspec. + (UNSPEC_FMIN): Likewise. + (fmax<mode>3): Use UNSPEC_FMAX instead of smax. + (fmin<mode>3): Use UNSPEC_FMIN instead of smin. + +2022-09-28 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/loongarch.cc (loongarch_asan_shadow_offset): + Fixed typo in "asan_mapping.h". + +2022-09-28 H.J. Lu <hjl.tools@gmail.com> + + PR middle-end/58245 + * calls.cc: Include "tree-eh.h". + (expand_call): Check stack canary before throwing exception. + +2022-09-27 Eugene Rozenfeld <erozen@microsoft.com> + + * ipa-cp.cc (good_cloning_opportunity_p): Fix profile count comparison. + +2022-09-27 Kim Kuparinen <kim.kuparinen@rightware.com> + + * doc/invoke.texi: Update ABI version info. + +2022-09-27 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-op.cc (cfn_popcount): Calculate the popcount of a + singleton. + +2022-09-27 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (irange::set_nonzero_bits): Set range when known. + +2022-09-27 Aldy Hernandez <aldyh@redhat.com> + + * value-range.h (irange::set): New version taking wide_int_ref. + +2022-09-27 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/107029 + * tree-ssa-reassoc.cc (optimize_range_tests_cmp_bitwise): Treat + OFFSET_TYPE like POINTER_TYPE, except that OFFSET_TYPE may be + signed and so can trigger even the (b % 4) == 3 case. + +2022-09-27 Jeff Law <jeffreyalaw@gmail.com> + + * cfgrtl.cc (fixup_reorder_chain): Verify that simple_return + and return are available before trying to use them. + +2022-09-27 Jakub Jelinek <jakub@redhat.com> + + PR c++/106652 + PR c++/85518 + * tree-core.h (enum tree_index): Add TI_FLOAT128T_TYPE + enumerator. + * tree.h (float128t_type_node): Define. + * tree.cc (build_common_tree_nodes): Initialize float128t_type_node. + * builtins.def (DEF_FLOATN_BUILTIN): Adjust comment now that + _Float<N> is supported in C++ too. + * config/i386/i386.cc (ix86_mangle_type): Only mangle as "g" + float128t_type_node. + * config/i386/i386-builtins.cc (ix86_init_builtin_types): Use + float128t_type_node for __float128 instead of float128_type_node + and create it if NULL. + * config/i386/avx512fp16intrin.h (_mm_setzero_ph, _mm256_setzero_ph, + _mm512_setzero_ph, _mm_set_sh, _mm_load_sh): Use 0.0f16 instead of + 0.0f. + * config/ia64/ia64.cc (ia64_init_builtins): Use + float128t_type_node for __float128 instead of float128_type_node + and create it if NULL. + * config/rs6000/rs6000-c.cc (is_float128_p): Also return true + for float128t_type_node if non-NULL. + * config/rs6000/rs6000.cc (rs6000_mangle_type): Don't mangle + float128_type_node as "u9__ieee128". + * config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Use + float128t_type_node for __float128 instead of float128_type_node + and create it if NULL. + +2022-09-26 Martin Liska <mliska@suse.cz> + + * doc/invoke.texi: Add missing dash for + Wanalyzer-exposure-through-uninit-copy. + +2022-09-26 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/107009 + * range-op.cc (operator_bitwise_and::op1_range): Optimize 0 = x & MASK. + (range_op_bitwise_and_tests): New test. + +2022-09-26 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/107009 + * tree-ssa-dom.cc + (dom_opt_dom_walker::set_global_ranges_from_unreachable_edges): + Iterate over exports. + +2022-09-26 Thomas Schwinge <thomas@codesourcery.com> + + * config.gcc (with_arch) [nvptx]: Allow '--with-arch' to override + the default. + * config/nvptx/gen-multilib-matches.sh: New. + * config/nvptx/t-nvptx (MULTILIB_OPTIONS, MULTILIB_MATCHES) + (MULTILIB_EXCEPTIONS): Handle this. + * doc/install.texi (Specific) <nvptx-*-none>: Document this. + * doc/invoke.texi (Nvidia PTX Options): Likewise. + +2022-09-26 Thomas Schwinge <thomas@codesourcery.com> + + * config.gcc (TM_MULTILIB_CONFIG) [nvptx]: Set to '$with_arch'. + * config/nvptx/t-nvptx (MULTILIB_OPTIONS, MULTILIB_MATCHES) + (MULTILIB_EXCEPTIONS): Handle it. + +2022-09-26 Thomas Schwinge <thomas@codesourcery.com> + + * config.gcc (with_arch) [nvptx]: Set to 'sm_30'. + * config/nvptx/nvptx.cc (nvptx_option_override): Assert that + '-misa' appeared. + * config/nvptx/nvptx.h (OPTION_DEFAULT_SPECS): Define. + * config/nvptx/nvptx.opt (misa=): Remove 'Init'. + +2022-09-26 Thomas Schwinge <thomas@codesourcery.com> + + * config/nvptx/nvptx.h (ASM_SPEC): Define. + +2022-09-26 Jeff Law <jeffreyalaw@gmail.com> + + * cfgcleanup.cc (bb_is_just_return): No longer static. + * cfgcleanup.h (bb_is_just_return): Add prototype. + * cfgrtl.cc (fixup_reorder_chain): Do not create an + unconditional jump to a return block. Conditionally + remove unreachable blocks. + +2022-09-26 Tobias Burnus <tobias@codesourcery.com> + + PR middle-end/106982 + * omp-low.cc (lower_oacc_reductions): Add some unshare_expr. + +2022-09-26 Martin Liska <mliska@suse.cz> + + * config/s390/s390.cc (s390_rtx_costs): Remove dest variable + and use only dst. + +2022-09-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/aarch64-arches.def (armv9.1-a): Define. + (armv9.2-a): Likewise. + (armv9.3-a): Likewise. + * config/aarch64/aarch64.h (AARCH64_FL_V9_1): Likewise. + (AARCH64_FL_V9_2): Likewise. + (AARCH64_FL_V9_3): Likewise. + (AARCH64_FL_FOR_ARCH9_1): Likewise. + (AARCH64_FL_FOR_ARCH9_2): Likewise. + (AARCH64_FL_FOR_ARCH9_3): Likewise. + (AARCH64_ISA_V9_1): Likewise. + (AARCH64_ISA_V9_2): Likewise. + (AARCH64_ISA_V9_3): Likewise. + * doc/invoke.texi (AArch64 Options): Document armv9.1-a, armv9.2-a, + armv9.3-a values to -march. + +2022-09-26 Martin Liska <mliska@suse.cz> + + * value-range.cc (tree_compare): Remove unused function. + +2022-09-26 Kewen Lin <linkw@linux.ibm.com> + + PR target/96072 + * config/rs6000/rs6000-logue.cc (rs6000_emit_epilogue): Update the + condition for adding REG_CFA_DEF_CFA reg note with + frame_pointer_needed_indeed. + +2022-09-26 Kewen Lin <linkw@linux.ibm.com> + + PR target/100645 + * config/rs6000/vector.md (vec_shr_<mode>): Replace condition + TARGET_ALTIVEC with VECTOR_UNIT_ALTIVEC_OR_VSX_P. + +2022-09-26 Hongtao Liu <hongtao.liu@intel.com> + Liwei Xu <liwei.xu@intel.com> + + PR target/53346 + * config/i386/i386-expand.cc (expand_vec_perm_shufps_shufps): + New function. + (ix86_expand_vec_perm_const_1): Insert + expand_vec_perm_shufps_shufps at the end of 2-instruction + expand sequence. + +2022-09-25 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com> + + * doc/sourcebuild.texi: Fix chapter level. + +2022-09-24 Jakub Jelinek <jakub@redhat.com> + + PR c/107001 + * omp-low.cc (lower_omp_taskgroup): Don't add GOMP_RETURN statement + at the end. + * omp-expand.cc (build_omp_regions_1): Clarify GF_OMP_TARGET_KIND_DATA + is not stand-alone directive. For GIMPLE_OMP_TASKGROUP, also don't + update parent. + (omp_make_gimple_edges) <case GIMPLE_OMP_TASKGROUP>: Reset + cur_region back after new_omp_region. + +2022-09-23 Vineet Gupta <vineetg@rivosinc.com> + + * config/riscv/riscv.h (LOCAL_SYM_P): New. + (USE_LOAD_ADDRESS_MACRO): Simplify by calling LOCAL_SYM_P. + +2022-09-23 zhongjuzhe <juzhe.zhong@rivai.ai> + + * config/riscv/riscv-modes.def (VECTOR_BOOL_MODE): Add RVV mask modes. + (ADJUST_NUNITS): Adjust nunits using riscv_vector_chunks. + (ADJUST_ALIGNMENT): Adjust alignment. + (ADJUST_BYTESIZE): Adjust bytesize using riscv_vector_chunks. + (RVV_MODES): New macro. + (VECTOR_MODE_WITH_PREFIX): Add RVV vector modes. + (VECTOR_MODES_WITH_PREFIX): Add RVV vector modes. + +2022-09-23 zhongjuzhe <juzhe.zhong@rivai.ai> + + * common/config/riscv/riscv-common.cc: Change "static void" to "void". + * config.gcc: Add riscv-selftests.o + * config/riscv/predicates.md: Allow const_poly_int. + * config/riscv/riscv-protos.h (riscv_reinit): New function. + (riscv_parse_arch_string): change as exten function. + (riscv_run_selftests): New function. + * config/riscv/riscv.cc (riscv_cannot_force_const_mem): Don't allow poly + into const pool. + (riscv_report_v_required): New function. + (riscv_expand_op): New function. + (riscv_expand_mult_with_const_int): New function. + (riscv_legitimize_poly_move): Ditto. + (riscv_legitimize_move): New function. + (riscv_hard_regno_mode_ok): Add VL/VTYPE register allocation and fix + vector RA. + (riscv_convert_vector_bits): Fix riscv_vector_chunks configuration for + -marh no 'v'. + (riscv_reinit): New function. + (TARGET_RUN_TARGET_SELFTESTS): New target hook support. + * config/riscv/t-riscv: Add riscv-selftests.o. + * config/riscv/riscv-selftests.cc: New file. + +2022-09-23 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106922 + * tree-ssa-sccvn.cc (vn_reference_lookup_3): Allow + an arbitrary number of same valued skipped stores. + +2022-09-23 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (frange::set): Swap setters such that the one + accepting REAL_VALUE_TYPE does all the work. + +2022-09-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/aarch64-cores.def (neoverse-v2): New entry. + (demeter): Update tunings to neoversev2. + * config/aarch64/aarch64-tune.md: Regenerate. + * config/aarch64/aarch64.cc (demeter_addrcost_table): Rename to + neoversev2_addrcost_table. + (demeter_regmove_cost): Rename to neoversev2_addrcost_table. + (demeter_advsimd_vector_cost): Rename to neoversev2_advsimd_vector_cost. + (demeter_sve_vector_cost): Rename to neoversev2_sve_vector_cost. + (demeter_scalar_issue_info): Rename to neoversev2_scalar_issue_info. + (demeter_advsimd_issue_info): Rename to neoversev2_advsimd_issue_info. + (demeter_sve_issue_info): Rename to neoversev2_sve_issue_info. + (demeter_vec_issue_info): Rename to neoversev2_vec_issue_info. + Update references to above. + (demeter_vector_cost): Rename to neoversev2_vector_cost. + (demeter_tunings): Rename to neoversev2_tunings. + (aarch64_vec_op_count::rename_cycles_per_iter): Use + neoversev2_sve_issue_info instead of demeter_sve_issue_info. + * doc/invoke.texi (AArch64 Options): Document neoverse-v2. + +2022-09-23 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (build_le): Use vrp_val_*. + (build_lt): Same. + (build_ge): Same. + (build_gt): Same. + * value-range.cc (frange::set): Chop ranges outside of the + representable numbers for -ffinite-math-only. + (frange::normalize_kind): Use vrp_val*. + (frange::verify_range): Same. + (frange::set_nonnegative): Same. + (range_tests_floats): Remove tests that depend on -INF and +INF. + * value-range.h (real_max_representable): Add prototype. + (real_min_representable): Same. + (vrp_val_max): Set max representable number for + -ffinite-math-only. + (vrp_val_min): Same but for min. + (frange::set_varying): Use vrp_val*. + +2022-09-23 Aldy Hernandez <aldyh@redhat.com> + + * real.cc (debug): New. + +2022-09-23 Aldy Hernandez <aldyh@redhat.com> + + * value-range-pretty-print.cc (vrange_printer::print_real_value): New. + (vrange_printer::visit): Call print_real_value. + * value-range-pretty-print.h: New print_real_value. + +2022-09-23 Martin Liska <mliska@suse.cz> + + * common.opt: Update -flto-compression-level documentation. + * opts.cc (print_filtered_help): Do not append range to an + option that uses \t syntax. + +2022-09-23 Jakub Jelinek <jakub@redhat.com> + + * attribs.cc (decl_attributes): Improve diagnostics, instead of + saying expected between 1 and 1, found 2 just say expected 1, found 2. + +2022-09-23 Hu, Lin1 <lin1.hu@intel.com> + + PR target/94962 + * config/i386/constraints.md (BH): New define_constraint. + * config/i386/i386.cc (standard_sse_constant_p): Add return + 3/4 when operand matches new predicate. + (standard_sse_constant_opcode): Add new alternative branch to + return "vpcmpeqd". + * config/i386/predicates.md + (vector_all_ones_zero_extend_half_operand): New define_predicate. + (vector_all_ones_zero_extend_quarter_operand): Ditto. + * config/i386/sse.md: Add constraint to insn "mov<mode>_internal". + +2022-09-22 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-fold.cc (range_of_range_op): Handle no operands. + (range_of_call): Do not check for builtins. + (fold_using_range::range_of_builtin_call): Delete. + (fold_using_range::range_of_builtin_int_call): Delete. + * gimple-range-fold.h: Adjust prototypes. + * gimple-range-op.cc (class cfn_parity): New. + (gimple_range_op_handler::maybe_builtin_call): Set arguments. + +2022-09-22 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-fold.cc (range_of_builtin_int_call): Remove case + for CFN_GOACC_DIM_*. + * gimple-range-op.cc (class cfn_goacc_dim): New. + (gimple_range_op_handler::maybe_builtin_call): Set arguments. + +2022-09-22 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-fold.cc (range_of_builtin_int_call): Remove case + for CFN_BUILT_IN_STRLEN. + * gimple-range-op.cc (class cfn_strlen): New. + (gimple_range_op_handler::maybe_builtin_call): Set arguments. + +2022-09-22 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-fold.cc (range_of_builtin_ubsan_call): Delete. + (range_of_builtin_int_call): Remove cases for + CFN_BUILT_IN_UBSAN_CHECK. + * gimple-range-op.cc (class cfn_ubsan): New. + (gimple_range_op_handler::maybe_builtin_call): Set arguments. + +2022-09-22 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-fold.cc (range_of_builtin_int_call): Remove case + for CFN_BUILT_IN_CLRSB. + * gimple-range-op.cc (class cfn_clrsb): New. + (gimple_range_op_handler::maybe_builtin_call): Set arguments. + +2022-09-22 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-fold.cc (range_of_builtin_int_call): Remove case + for CFN_CTZ. + * gimple-range-op.cc (class cfn_ctz): New. + (gimple_range_op_handler::maybe_builtin_call): Set arguments. + +2022-09-22 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-fold.cc (range_of_builtin_int_call): Remove case + for CFN_CLZ. + * gimple-range-op.cc (class cfn_clz): New. + (gimple_range_op_handler::maybe_builtin_call): Set arguments. + +2022-09-22 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-fold.cc (range_of_builtin_int_call): Remove case + for CFN_FFS and CFN_POPCOUNT. + * gimple-range-op.cc (class cfn_pocount): New. + (gimple_range_op_handler::maybe_builtin_call): Set arguments. + +2022-09-22 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-fold.cc (get_letter_range): Move to new class. + (range_of_builtin_int_call): Remove case for CFN_BUILT_IN_TOUPPER + and CFN_BUILT_IN_TOLOWER. + * gimple-range-op.cc (class cfn_toupper_tolower): New. + (gimple_range_op_handler::maybe_builtin_call): Set arguments. + +2022-09-22 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-fold.cc (range_of_builtin_int_call): Remove case + for CFN_BUILT_IN_SIGNBIT. + * gimple-range-op.cc (class cfn_signbit): New. + (gimple_range_op_handler::maybe_builtin_call): Set arguments. + +2022-09-22 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-fold.cc + (fold_using_range::range_of_builtin_int_call): Remove case for + CFN_BUILT_IN_CONSTANT_P. + * gimple-range-op.cc (gimple_range_op_handler::supported_p): + Check if a call also creates a range-op object. + (gimple_range_op_handler): Also check builtin calls. + (class cfn_constant_float_p): New. Float CFN_BUILT_IN_CONSTANT_P. + (class cfn_constant_p): New. Integral CFN_BUILT_IN_CONSTANT_P. + (gimple_range_op_handler::maybe_builtin_call): Set arguments and + handler for supported built-in calls. + * gimple-range-op.h (maybe_builtin_call): New prototype. + +2022-09-22 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-fold.cc (range_of_range_op): Set result to + VARYING if the call to fold_range fails. + * tree-data-ref.cc (compute_distributive_range): Ditto. + * tree-vrp.cc (range_fold_binary_expr): Ditto. + (range_fold_unary_expr): Ditto. + * value-query.cc (range_query::get_tree_range): Ditto. + +2022-09-22 Andrew MacLeod <amacleod@redhat.com> + + * range-op-float.cc (range_operator_float::fold_range): New base + method for "int = float op int". + * range-op.cc (range_op_handler::fold_range): New case. + * range-op.h: Update prototypes. + +2022-09-22 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-op.cc (gimple_range_op_handler::calc_op1): Use + operand 1 for second range if there is no operand 2. + +2022-09-22 Andrew MacLeod <amacleod@redhat.com> + + * Makefile.in (OBJS): Add gimple-range-op.o. + * gimple-range-edge.cc (gimple_outgoing_range_stmt_p): Use + gimple_range_op_handler. + * gimple-range-fold.cc (gimple_range_base_of_assignment): Move + to a method in gimple_range_op_handler. + (gimple_range_operand1): Ditto. + (gimple_range_operand2): Ditto. + (fold_using_range::fold_stmt): Use gimple_range_op_handler. + (fold_using_range::range_of_range_op): Ditto. + (fold_using_range::relation_fold_and_or): Ditto. + (fur_source::register_outgoing_edges): Ditto. + (gimple_range_ssa_names): Relocate to gimple-range-op.cc. + * gimple-range-fold.h: Adjust prototypes. + * gimple-range-gori.cc (gimple_range_calc_op1): Move + to a method in gimple_range_op_handler. + (gimple_range_calc_op2): Ditto. + (gori_compute::compute_operand_range): Use + gimple_range_op_handler. + (gori_compute::compute_logical_operands): Ditto. + (compute_operand1_range): Ditto. + (gori_compute::compute_operand2_range): Ditto. + (gori_compute::compute_operand1_and_operand2_range): Ditto. + * gimple-range-gori.h: Adjust protoypes. + * gimple-range-op.cc: New. Supply gimple_range_op_handler methods. + * gimple-range-op.h: New. Supply gimple_range_op_handler class. + * gimple-range.cc (gimple_ranger::prefill_name): Use + gimple_range_op_handler. + (gimple_ranger::prefill_stmt_dependencies): Ditto. + * gimple-range.h: Include gimple-range-op.h. + * range-op.cc (range_op_handler::range_op_handler): Adjust and + remove gimple * parameter option. + * range-op.h: Adjust prototypes. + +2022-09-22 Andrew MacLeod <amacleod@redhat.com> + + * range-op.cc (range_op_handler::set_op_handler): Set new fields. + (ange_op_handler::range_op_handler): Likewise. + (range_op_handler::operator bool): Remove. + (range_op_handler::fold_range): Use appropriate handler. + (range_op_handler::op1_range): Likewise. + (range_op_handler::op2_range): Likewise. + (range_op_handler::lhs_op1_relation): Likewise. + (range_op_handler::lhs_op2_relation): Likewise. + (range_op_handler::op1_op2_relation): Likewise. + * range-op.h (class range_op_handler): Store handler pointers. + (range_op_handler:: operator bool): Inline. + +2022-09-22 Andrew MacLeod <amacleod@redhat.com> + + * tree-ssa-threadbackward.cc + (back_threader::find_paths_to_names): Replace sequence with + a call to gimple_range_ssa_names. + +2022-09-22 Martin Liska <mliska@suse.cz> + Fangrui Song <i@maskray.me> + + * configure: Regenerate. + * configure.ac: Simplify to gcc_cv_ld_compress_debug={0,1} + and gcc_cv_as_compress_debug={0,1}. + * doc/invoke.texi: Document the removal. + * gcc.cc (LINK_COMPRESS_DEBUG_SPEC): Simplify and ignore + zlib-gnu. + (ASM_COMPRESS_DEBUG_SPEC): Likewise. + +2022-09-22 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106922 + * tree-ssa-sccvn.cc (vn_walk_cb_data::same_val): New member. + (vn_walk_cb_data::finish): Perform delayed verification of + a skipped may-alias. + (vn_reference_lookup_pieces): Likewise. + (vn_reference_lookup): Likewise. + (vn_reference_lookup_3): When skipping stores of the same + value also handle constant stores that are more than a + single VDEF away by delaying the verification. + +2022-09-22 Max Filippov <jcmvbkbc@gmail.com> + + * config/xtensa/xtensa.cc (TARGET_MAX_ANCHOR_OFFSET): New + definition. + +2022-09-22 Max Filippov <jcmvbkbc@gmail.com> + + * config/xtensa/xtensa.cc (xtensa_can_output_mi_thunk) + (xtensa_output_mi_thunk): New functions. + (TARGET_ASM_CAN_OUTPUT_MI_THUNK) + (TARGET_ASM_OUTPUT_MI_THUNK): New macro definitions. + (xtensa_prepare_expand_call): Use fixed register a8 as temporary + when called with reload_completed set to 1. + +2022-09-22 Richard Biener <rguenther@suse.de> + + PR tree-optimization/99407 + * tree-ssa-dse.cc (dse_stmt_to_dr_map): New global. + (dse_classify_store): Use data-ref analysis to disambiguate more uses. + (pass_dse::use_dr_analysis_p): New pass parameter. + (pass_dse::set_pass_param): Implement. + (pass_dse::execute): Allocate and deallocate dse_stmt_to_dr_map. + * passes.def: Allow DR analysis for the DSE pass before loop. + +2022-09-22 Richard Biener <rguenther@suse.de> + + * tree-ssa-sccvn.cc (can_track_predicate_on_edge): New + function split out from ... + (vn_nary_op_insert_pieces_predicated): ... here. + +2022-09-22 liuhongt <hongtao.liu@intel.com> + + PR target/106994 + * config/i386/mmx.md (floorv2sf2): Fix typo, use + register_operand instead of vector_operand for operands[1]. + +2022-09-21 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/106967 + * value-range.cc (frange::set): Set known NANs to undefined for + flag_finite_math_only. + +2022-09-21 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (frange::combine_zeros): Call set_undefined. + (frange::intersect_nans): Same. + (frange::intersect): Same. + (frange::verify_range): Undefined ranges do not have a type. + * value-range.h (frange::set_undefined): Clear NAN flags and type. + +2022-09-21 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106984 + * tsan.cc (instrument_builtin_call): Build the COND_EXPR condition in + a separate statement. + +2022-09-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/aarch64.h (HAVE_LOCAL_CPU_DETECT, + EXTRA_SPEC_FUNCTIONS, MCPU_MTUNE_NATIVE_SPECS): Move definitions up before + OPTION_DEFAULT_SPECS. + (MCPU_MTUNE_NATIVE_SPECS): Pass "cpu" to + local_cpu_detect when rewriting -march=native and no -mcpu or -mtune + is given. + (CONFIG_TUNE_SPEC): Define. + (OPTION_DEFAULT_SPECS): Use CONFIG_TUNE_SPEC for "tune". + +2022-09-21 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/106967 + * range-op-float.cc (foperator_equal::fold_range): Adjust for NAN. + (foperator_equal::op1_range): Same. + (foperator_not_equal::fold_range): Same. + (foperator_not_equal::op1_range): Same. + (foperator_lt::fold_range): Same. + (foperator_lt::op1_range): Same. + (foperator_lt::op2_range): Same. + (foperator_le::fold_range): Same. + (foperator_le::op1_range): Same. + (foperator_le::op2_range): Same. + (foperator_gt::fold_range): Same. + (foperator_gt::op1_range): Same. + (foperator_gt::op2_range): Same. + (foperator_ge::fold_range): Same. + (foperator_ge::op1_range): Same. + (foperator_ge::op2_range): Same. + (foperator_unordered::op1_range): Same. + (foperator_ordered::fold_range): Same. + (foperator_ordered::op1_range): Same. + (build_le): Assert that we don't have a NAN. + (build_lt): Same. + (build_gt): Same. + (build_ge): Same. + +2022-09-21 liuhongt <hongtao.liu@intel.com> + + PR tree-optimization/106963 + * tree-vect-loop.cc (vect_create_nonlinear_iv_init): Use + vec_gen_perm_mask_any instead of vec_gen_perm_mask_check. + +2022-09-20 Aldy Hernandez <aldyh@redhat.com> + + * value-range.h (frange::maybe_isnan): Return false for + undefined ranges. + +2022-09-20 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (frange::set_nonnegative): Set +NAN. + (range_tests_signed_zeros): New test. + * value-range.h (frange::update_nan): New overload to set NAN sign. + +2022-09-20 Richard Sandiford <richard.sandiford@arm.com> + + PR target/106491 + * config/aarch64/aarch64-sve-builtins.cc (scalar_types) + (acle_vector_types, acle_svpattern, acle_svprfop): Add GTY + markup to (new) extern declarations instead of to the main + definition. + +2022-09-20 Richard Sandiford <richard.sandiford@arm.com> + + PR tree-optimization/106794 + PR tree-optimization/106914 + * tree-vect-slp.cc (vect_optimize_slp_pass::internal_node_cost): + Only consider loads that already have a permutation. + (vect_optimize_slp_pass::start_choosing_layouts): Assert that + loads with permutations are leaf nodes. Prevent any kind of grouped + access from changing layout if it doesn't have a load permutation. + +2022-09-20 Richard Sandiford <richard.sandiford@arm.com> + + * tree-vect-data-refs.cc (vect_check_gather_scatter): Restrict + early-out optimisation to SSA_NAMEs. + +2022-09-20 Martin Liska <mliska@suse.cz> + + * ctfc.cc (ctf_add_string): Replace "the the" with "the". + * doc/md.texi: Likewise. + * gimple-range-infer.cc (non_null_loadstore): Likewise. + +2022-09-20 liuhongt <hongtao.liu@intel.com> + + PR target/106910 + * config/i386/mmx.md (nearbyintv2sf2): New expander. + (rintv2sf2): Ditto. + (ceilv2sf2): Ditto. + (lceilv2sfv2si2): Ditto. + (floorv2sf2): Ditto. + (lfloorv2sfv2si2): Ditto. + (btruncv2sf2): Ditto. + (lrintv2sfv2si2): Ditto. + (roundv2sf2): Ditto. + (lroundv2sfv2si2): Ditto. + (*mmx_roundv2sf2): New define_insn. + +2022-09-20 konglin1 <lingling.kong@intel.com> + + PR middle-end/105735 + * tree-scalar-evolution.cc + (analyze_and_compute_bitop_with_inv_effect): New function. + (final_value_replacement_loop): Enhanced to handle bitop + with inv induction. + +2022-09-20 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/gnu-user.h (GNU_USER_TARGET_LINK_SPEC): For + -static-pie, pass -static -pie --no-dynamic-linker -z text to + the linker, and do not pass --dynamic-linker. + +2022-09-20 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (frange::flush_denormals_to_zero): New. + (frange::set): Call flush_denormals_to_zero. + * value-range.h (class frange): Add flush_denormals_to_zero. + +2022-09-20 liuhongt <hongtao.liu@intel.com> + + * config/i386/x86-tune-sched.cc (ix86_issue_rate): Adjust for + latest Intel processors. + +2022-09-20 konglin1 <lingling.kong@intel.com> + + PR target/106887 + * config/i386/i386-expand.cc (ix86_expand_vector_init_duplicate): + Fixed V16BF mode case. + +2022-09-19 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com> + + * targhooks.cc (default_zero_call_used_regs): Improve sorry + message. + +2022-09-18 Julian Brown <julian@codesourcery.com> + + * gimplify.cc (omp_segregate_mapping_groups): Update comment. + (gimplify_adjust_omp_clauses): Move ATTACH and + ATTACH_ZERO_LENGTH_ARRAY_SECTION nodes to the end of the clause list + for offloaded OpenMP regions. + +2022-09-18 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/106831 + * value-range.cc (frange::singleton_p): Avoid propagating long + doubles that may have multiple representations. + +2022-09-18 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (frange_add_zeros): Replace set_signbit with + union of zero. + * value-query.cc (range_query::get_tree_range): Remove set_signbit + use. + * value-range-pretty-print.cc (vrange_printer::print_frange_prop): + Remove. + (vrange_printer::print_frange_nan): New. + * value-range-pretty-print.h (print_frange_prop): Remove. + (print_frange_nan): New. + * value-range-storage.cc (frange_storage_slot::set_frange): Set + kind and NAN fields. + (frange_storage_slot::get_frange): Restore kind and NAN fields. + * value-range-storage.h (class frange_storage_slot): Add kind and + NAN fields. + * value-range.cc (frange::update_nan): Remove. + (frange::set_signbit): Remove. + (frange::set): Adjust for NAN fields. + (frange::normalize_kind): Remove m_props. + (frange::combine_zeros): New. + (frange::union_nans): New. + (frange::union_): Handle new NAN fields. + (frange::intersect_nans): New. + (frange::intersect): Handle new NAN fields. + (frange::operator=): Same. + (frange::operator==): Same. + (frange::contains_p): Same. + (frange::singleton_p): Remove special case for signed zeros. + (frange::verify_range): Adjust for new NAN fields. + (frange::set_zero): Handle signed zeros. + (frange::set_nonnegative): Same. + (range_tests_nan): Adjust tests. + (range_tests_signed_zeros): Same. + (range_tests_signbit): Same. + (range_tests_floats): Same. + * value-range.h (class fp_prop): Remove. + (FP_PROP_ACCESSOR): Remove. + (class frange_props): Remove + (frange::lower_bound): NANs don't have endpoints. + (frange::upper_bound): Same. + (frange_props::operator==): Remove. + (frange_props::union_): Remove. + (frange_props::intersect): Remove. + (frange::update_nan): New. + (frange::clear_nan): New. + (frange::undefined_p): New. + (frange::set_nan): New. + (frange::known_finite): Adjust for new NAN representation. + (frange::maybe_isnan): Same. + (frange::known_isnan): Same. + (frange::signbit_p): Same. + * gimple-range-fold.cc (range_of_builtin_int_call): Rename + known_signbit_p into signbit_p. + +2022-09-17 Jan-Benedict Glaw <jbglaw@lug-owl.de> + + * config/csky/csky.h (FUNCTION_ARG_REGNO_P): Cast REGNO to (int) + to prevent warning. + +2022-09-17 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/106958 + * tree-ssa-reassoc.cc (optimize_range_tests_cmp_bitwise): If + id >= l, cast op to type1, otherwise to pointer_sized_int_node. + If type has pointer type, cast exp to pointer_sized_int_node + even when id < l. + +2022-09-16 liuhongt <hongtao.liu@intel.com> + + PR target/106910 + * config/i386/i386-builtins.cc + (ix86_builtin_vectorized_function): Modernized with + corresponding expanders. + * config/i386/sse.md (lrint<mode><sseintvecmodelower>2): New + expander. + (floor<mode>2): Ditto. + (lfloor<mode><sseintvecmodelower>2): Ditto. + (ceil<mode>2): Ditto. + (lceil<mode><sseintvecmodelower>2): Ditto. + (btrunc<mode>2): Ditto. + (lround<mode><sseintvecmodelower>2): Ditto. + (exp2<mode>2): Ditto. + +2022-09-15 Joseph Myers <joseph@codesourcery.com> + + * ginclude/float.h (INFINITY): Define only if + [__FLT_HAS_INFINITY__]. + +2022-09-15 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106922 + * tree-ssa-pre.cc (translate_vuse_through_block): Only + keep the VUSE if its def dominates PHIBLOCK. + (prune_clobbered_mems): Rewrite logic so we check whether + a value dies in a block when the VUSE def doesn't dominate it. + +2022-09-15 Richard Biener <rguenther@suse.de> + + * tree.cc (build_common_tree_nodes): Initialize void_list_node + here. + +2022-09-15 Jiufu Guo <guojiufu@linux.ibm.com> + + PR target/106550 + * config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Use pli. + +2022-09-14 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (frange_add_zeros): New. + (build_le): Call frange_add_zeros. + (build_ge): Same. + (foperator_equal::op1_range): Same. + (foperator_not_equal::op1_range): Same. + +2022-09-14 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (build_le): Accept frange instead of number. + (build_lt): Same. + (build_ge): Same. + (build_gt): Same. + (foperator_lt::op1_range): Pass full range to build_*. + (foperator_lt::op2_range): Same. + (foperator_le::op1_range): Same. + (foperator_le::op2_range): Same. + (foperator_gt::op1_range): Same. + (foperator_gt::op2_range): Same. + (foperator_ge::op1_range): Same. + (foperator_ge::op2_range): Same. + +2022-09-14 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (frange::set): Use set_nan. + * value-range.h (frange::set_nan): Inline code originally in + set(). + +2022-09-14 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (frange_set_nan): Remove. + (build_lt): Use set_nan, update_nan, clear_nan. + (build_gt): Same. + (foperator_equal::op1_range): Same. + (foperator_not_equal::op1_range): Same. + (foperator_lt::op1_range): Same. + (foperator_lt::op2_range): Same. + (foperator_le::op1_range): Same. + (foperator_le::op2_range): Same. + (foperator_gt::op1_range): Same. + (foperator_gt::op2_range): Same. + (foperator_ge::op1_range): Same. + (foperator_ge::op2_range): Same. + (foperator_unordered::op1_range): Same. + (foperator_ordered::op1_range): Same. + * value-query.cc (range_query::get_tree_range): Same. + * value-range.cc (frange::set_nan): Same. + (frange::update_nan): Same. + (frange::union_): Same. + (frange::intersect): Same. + (range_tests_nan): Same. + (range_tests_signed_zeros): Same. + (range_tests_signbit): Same. + (range_tests_floats): Same. + * value-range.h (class frange): Add update_nan and clear_nan. + (frange::set_nan): New. + +2022-09-14 Aldy Hernandez <aldyh@redhat.com> + + * value-query.cc (range_query::get_tree_range): Remove check for overflow. + * value-range-pretty-print.cc (vrange_printer::visit): Move read + of type until after undefined_p is checked. + * value-range.cc (frange::set): Remove asserts for REAL_CST. + (frange::contains_p): Tidy up. + (range_tests_nan): Add comment. + * value-range.h (frange::type): Check for undefined_p. + (frange::set_undefined): Remove set of endpoints. + +2022-09-14 Julian Brown <julian@codesourcery.com> + + * gimplify.cc (omp_group_last): Allow GOMP_MAP_ATTACH_DETACH after + GOMP_MAP_STRUCT (for reindexing). + (omp_gather_mapping_groups): Reimplement using... + (omp_gather_mapping_groups_1): This new function. Stop processing at + GATHER_SENTINEL. + (omp_group_base): Allow GOMP_MAP_TO_PSET without any following node. + (omp_index_mapping_groups): Reimplement using... + (omp_index_mapping_groups_1): This new function. Handle + REINDEX_SENTINEL. + (omp_reindex_mapping_groups, omp_mapped_by_containing_struct): New + functions. + (omp_tsort_mapping_groups_1): Adjust handling of base group being the + same as current group. Use omp_mapped_by_containing_struct. + (omp_build_struct_sibling_lists): Use omp_mapped_by_containing_struct + and omp_reindex_mapping_groups. Robustify group deletion for reordered + lists. + (gimplify_scan_omp_clauses): Update calls to + omp_build_struct_sibling_lists. + +2022-09-14 Julian Brown <julian@codesourcery.com> + + * gimplify.cc (gimplify_omp_var_data): Remove GOVD_MAP_HAS_ATTACHMENTS. + (GOMP_FIRSTPRIVATE_IMPLICIT): Renumber. + (insert_struct_comp_map): Refactor function into... + (build_omp_struct_comp_nodes): This new function. Remove list handling + and improve self-documentation. + (extract_base_bit_offset): Remove BASE_REF, OFFSETP parameters. Move + code to strip outer parts of address out of function, but strip no-op + conversions. + (omp_mapping_group): Add DELETED field for use during reindexing. + (omp_strip_components_and_deref, omp_strip_indirections): New functions. + (omp_group_last, omp_group_base): Add GOMP_MAP_STRUCT handling. + (omp_gather_mapping_groups): Initialise DELETED field for new groups. + (omp_index_mapping_groups): Notice DELETED groups when (re)indexing. + (omp_siblist_insert_node_after, omp_siblist_move_node_after, + omp_siblist_move_nodes_after, omp_siblist_move_concat_nodes_after): New + helper functions. + (omp_accumulate_sibling_list): New function to build up GOMP_MAP_STRUCT + node groups for sibling lists. Outlined from gimplify_scan_omp_clauses. + (omp_build_struct_sibling_lists): New function. + (gimplify_scan_omp_clauses): Remove struct_map_to_clause, + struct_seen_clause, struct_deref_set. Call + omp_build_struct_sibling_lists as pre-pass instead of handling sibling + lists in the function's main processing loop. + (gimplify_adjust_omp_clauses_1): Remove GOVD_MAP_HAS_ATTACHMENTS + handling, unused now. + * omp-low.cc (scan_sharing_clauses): Handle pointer-type indirect + struct references, and references to pointers to structs also. + +2022-09-14 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106938 + * tree-cfg.cc (execute_fixup_cfg): Purge dead abnormal + edges for all last stmts in a block. Do EH cleanup + only on the last stmt in a block. + +2022-09-14 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/106936 + * value-query.cc (range_query::get_value_range): Remove assert. + +2022-09-14 Jan-Benedict Glaw <jbglaw@lug-owl.de> + + * config/mips/mips.cc (mips_option_override): Drop unused variable. + +2022-09-14 Julian Brown <julian@codesourcery.com> + + * gimplify.cc (is_or_contains_p, omp_target_reorder_clauses): Delete + functions. + (omp_tsort_mark): Add enum. + (omp_mapping_group): Add struct. + (debug_mapping_group, omp_get_base_pointer, omp_get_attachment, + omp_group_last, omp_gather_mapping_groups, omp_group_base, + omp_index_mapping_groups, omp_containing_struct, + omp_tsort_mapping_groups_1, omp_tsort_mapping_groups, + omp_segregate_mapping_groups, omp_reorder_mapping_groups): New + functions. + (gimplify_scan_omp_clauses): Call above functions instead of + omp_target_reorder_clauses, unless we've seen an error. + * omp-low.cc (scan_sharing_clauses): Avoid strict test if we haven't + sorted mapping groups. + +2022-09-14 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/106878 + * tree-cfg.cc (verify_gimple_assign_binary): Disallow pointer, + reference or OFFSET_TYPE BIT_IOR_EXPR, BIT_XOR_EXPR or, unless + the second argument is INTEGER_CST, BIT_AND_EXPR. + * match.pd ((type) X op CST -> (type) (X op ((type-x) CST)), + (type) (((type2) X) op Y) -> (X op (type) Y)): Punt for + POINTER_TYPE_P or OFFSET_TYPE. + * tree-ssa-reassoc.cc (optimize_range_tests_cmp_bitwise): For + pointers cast them to pointer sized integers first. + +2022-09-14 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106934 + * tree-ssa.cc (non_rewritable_mem_ref_base): Avoid BIT_FIELD_REFs + of bitfields. + (maybe_rewrite_mem_ref_base): Likewise. + +2022-09-14 liuhongt <hongtao.liu@intel.com> + + PR tree-optimization/106905 + * tree-vect-loop.cc (vectorizable_nonlinear_induction): Return + false when !vect_use_loop_mask_for_alignment_p (loop_vinfo) && + LOOP_VINFO_PEELING_FOR_ALIGNMENT (loop_vinfo) < 0. + +2022-09-13 Roger Sayle <roger@nextmovesoftware.com> + + PR target/106877 + * reg-stack.cc (move_for_stack_reg): Check for any_malformed_asm + in gcc_assert. + +2022-09-13 Max Filippov <jcmvbkbc@gmail.com> + + Revert: + 2022-09-12 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.cc (TARGET_CONSTANT_OK_FOR_CPROP_P): + New macro definition. + (xtensa_constant_ok_for_cprop_p): + Implement the hook as mentioned above. + +2022-09-13 Kewen Lin <linkw@linux.ibm.com> + + PR target/104482 + * config/rs6000/rs6000-c.cc (altivec_resolve_overloaded_builtin): Fix + the equality check for argument number, and move this hunk ahead. + +2022-09-13 Kewen.Lin <linkw@gcc.gnu.org> + + PR target/105485 + * config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_builtin): Add + the handling for unresolved overloaded builtin function. + (rs6000_expand_builtin): Likewise. + +2022-09-13 Kewen Lin <linkw@linux.ibm.com> + + * config/rs6000/rs6000.cc (class rs6000_cost_data): Add new members + m_nstores, m_reduc_factor, m_gather_load and member function + determine_suggested_unroll_factor. + (rs6000_cost_data::update_target_cost_per_stmt): Update for m_nstores, + m_reduc_factor and m_gather_load. + (rs6000_cost_data::determine_suggested_unroll_factor): New function. + (rs6000_cost_data::finish_cost): Use determine_suggested_unroll_factor. + * config/rs6000/rs6000.opt (rs6000-vect-unroll-limit): New parameter. + (rs6000-vect-unroll-issue): Likewise. + (rs6000-vect-unroll-reduc-threshold): Likewise. + * doc/invoke.texi (rs6000-vect-unroll-limit): Document new parameter. + +2022-09-13 Richard Biener <rguenther@suse.de> + + PR middle-end/106909 + * gimple-fold.cc (gimple_fold_call): Clear the ctrl-altering + flag of a unreachable call. + +2022-09-13 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106913 + * tree-ssa-uninit.cc (warn_uninitialized_vars): Do not set + ft_reachable on EXIT_BLOCK. + +2022-09-13 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64.cc (aarch64_classify_vector_mode): Use + TARGET_FLOAT instead of TARGET_SIMD. + (aarch64_vectorize_related_mode): Restrict ADVSIMD handling to + TARGET_SIMD. + (aarch64_hard_regno_mode_ok): Don't allow tuples of 2 64-bit vectors + in GPRs. + (aarch64_classify_address): Treat little-endian structure moves + like big-endian for TARGET_FLOAT && !TARGET_SIMD. + (aarch64_secondary_memory_needed): New function. + (aarch64_secondary_reload): Handle 128-bit Advanced SIMD vectors + in the same way as TF, TI and TD. + (aarch64_rtx_mult_cost): Restrict ADVSIMD handling to TARGET_SIMD. + (aarch64_rtx_costs): Likewise. + (aarch64_register_move_cost): Treat a pair of 64-bit vectors + separately from a single 128-bit vector. Handle the cost implied + by aarch64_secondary_memory_needed. + (aarch64_simd_valid_immediate): Restrict ADVSIMD handling to + TARGET_SIMD. + (aarch64_expand_vec_perm_const_1): Likewise. + (TARGET_SECONDARY_MEMORY_NEEDED): New macro. + * config/aarch64/iterators.md (VTX): New iterator. + * config/aarch64/aarch64.md (arches): Add fp_q as a synonym of simd. + (arch_enabled): Adjust accordingly. + (@aarch64_reload_mov<TX:mode>): Extend to... + (@aarch64_reload_mov<VTX:mode>): ...this. + * config/aarch64/aarch64-simd.md (mov<mode>): Require TARGET_FLOAT + rather than TARGET_SIMD. + (movmisalign<mode>): Likewise. + (load_pair<DREG:mode><DREG2:mode>): Likewise. + (vec_store_pair<DREG:mode><DREG2:mode>): Likewise. + (load_pair<VQ:mode><VQ2:mode>): Likewise. + (vec_store_pair<VQ:mode><VQ2:mode>): Likewise. + (@aarch64_split_simd_mov<mode>): Likewise. + (aarch64_get_low<mode>): Likewise. + (aarch64_get_high<mode>): Likewise. + (aarch64_get_half<mode>): Likewise. Canonicalize to a move for + lowpart extracts. + (*aarch64_simd_mov<VDMOV:mode>): Require TARGET_FLOAT rather than + TARGET_SIMD. Use different w<-w and r<-w instructions for + !TARGET_SIMD. Disable immediate moves for !TARGET_SIMD but + add an alternative specifically for w<-Z. + (*aarch64_simd_mov<VQMOV:mode>): Require TARGET_FLOAT rather than + TARGET_SIMD. Likewise for the associated define_splits. Disable + FPR moves and immediate moves for !TARGET_SIMD but add an alternative + specifically for w<-Z. + (aarch64_simd_mov_from_<mode>high): Require TARGET_FLOAT rather than + TARGET_SIMD. Restrict the existing alternatives to TARGET_SIMD + but add a new r<-w one for !TARGET_SIMD. + (*aarch64_get_high<mode>): New pattern. + (load_pair_lanes<mode>): Require TARGET_FLOAT rather than TARGET_SIMD. + (store_pair_lanes<mode>): Likewise. + (*aarch64_combine_internal<mode>): Likewise. Restrict existing + w<-w, w<-r and w<-m alternatives to TARGET_SIMD but add a new w<-r + alternative for !TARGET_SIMD. + (*aarch64_combine_internal_be<mode>): Likewise. + (aarch64_combinez<mode>): Require TARGET_FLOAT rather than TARGET_SIMD. + Remove bogus arch attribute. + (*aarch64_combinez_be<mode>): Likewise. + (@aarch64_vec_concat<mode>): Require TARGET_FLOAT rather than + TARGET_SIMD. + (aarch64_combine<mode>): Likewise. + (aarch64_rev_reglist<mode>): Likewise. + (mov<mode>): Likewise. + (*aarch64_be_mov<VSTRUCT_2D:mode>): Extend to TARGET_FLOAT && + !TARGET_SIMD, regardless of endianness. Extend associated + define_splits in the same way, both for this pattern and the + ones below. + (*aarch64_be_mov<VSTRUCT_2Qmode>): Likewise. Restrict w<-w + alternative to TARGET_SIMD. + (*aarch64_be_movoi): Likewise. + (*aarch64_be_movci): Likewise. + (*aarch64_be_movxi): Likewise. + (*aarch64_be_mov<VSTRUCT_4QD:mode>): Extend to TARGET_FLOAT + && !TARGET_SIMD, regardless of endianness. Restrict w<-w alternative + to TARGET_SIMD for tuples of 128-bit vectors. + (*aarch64_be_mov<VSTRUCT_4QD:mode>): Likewise. + * config/aarch64/aarch64-ldpstp.md: Remove TARGET_SIMD condition + from DREG STP peephole. Change TARGET_SIMD to TARGET_FLOAT in + the VQ and VP_2E LDP and STP peepholes. + +2022-09-13 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-simd.md (movv8di): Remove TARGET_SIMD + condition. Likewise for the related define_split. Tweak formatting. + +2022-09-12 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.cc (TARGET_CONSTANT_OK_FOR_CPROP_P): + New macro definition. + (xtensa_constant_ok_for_cprop_p): + Implement the hook as mentioned above. + +2022-09-12 Joseph Myers <joseph@codesourcery.com> + + * ginclude/stdatomic.h [defined __STDC_VERSION__ && + __STDC_VERSION__ > 201710L] (ATOMIC_VAR_INIT): Do not define. + +2022-09-12 Tobias Burnus <tobias@codesourcery.com> + + * config/nvptx/mkoffload.cc (process): Replace a fatal_error by + a warning + not enabling offloading if -misa=sm_30 prevents + reverse offload. + (main): Use tool_name as progname for diagnostic. + * config/gcn/mkoffload.cc (main): Likewise. + +2022-09-12 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (frange::set_signbit): Avoid changing sign when + already in the correct sign. + +2022-09-12 Max Filippov <jcmvbkbc@gmail.com> + + * config/xtensa/xtensa.cc (xtensa_function_value_regno_p): + Recognize all 4 return registers. + * config/xtensa/xtensa.h (GP_RETURN_REG_COUNT): New definition. + * config/xtensa/xtensa.md (untyped_call): New pattern. + +2022-09-12 Jonathan Wakely <jwakely@redhat.com> + + * doc/extend.texi (Floating Types): Fix "_float128" typo. + +2022-09-10 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.cc (xtensa_constantsynth): + Add new pattern for the abovementioned case. + +2022-09-10 Akari Takahashi <akaritakahashioss@gmail.com> + Segher Boessenkool <segher@kernel.crashing.org> + + * config/rs6000/rs6000.cc (get_memref_parts): Regularize some code. + +2022-09-09 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md: Rewrite the split pattern that performs + the abovementioned process so that insns that overwrite clobbered + register no longer need to be contiguous. + (DSC): Remove as no longer needed. + +2022-09-09 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.cc (machine_function): New boolean member as + a flag that controls whether to emit the insns for stack pointer + adjustment inside of the pro/epilogue. + (xtensa_emit_adjust_stack_ptr): New function to share the common + codes and to emit insns if not inhibited. + (xtensa_expand_epilogue): Change to use the function mentioned + above when using the CALL0 ABI. + (xtensa_expand_prologue): Ditto. + And also change to set the inhibit flag used by + xtensa_emit_adjust_stack_ptr() to true if the stack pointer is only + used for its own adjustment. + +2022-09-09 David Malcolm <dmalcolm@redhat.com> + + * doc/invoke.texi (Static Analyzer Options): Add + -Wanalyzer-exposure-through-uninit-copy. + +2022-09-09 David Malcolm <dmalcolm@redhat.com> + + * Makefile.in (ANALYZER_OBJS): Add + analyzer/known-function-manager.o. + +2022-09-09 Tobias Burnus <tobias@codesourcery.com> + + * config/nvptx/mkoffload.cc (struct id_map): Add 'dim' member. + (record_id): Store func name without quotes, store dim separately. + (process): For GOMP_REQUIRES_REVERSE_OFFLOAD, check that -march is + at least sm_35, create '$offload_func_table' global array and init + with reverse-offload function addresses. + * config/nvptx/nvptx.cc (write_fn_proto_1, write_fn_proto): New + force_public attribute to force .visible. + (nvptx_declare_function_name): For "omp target + device_ancestor_nohost" attribut, force .visible/TREE_PUBLIC. + +2022-09-09 Tobias Burnus <tobias@codesourcery.com> + + * config/gcn/mkoffload.cc (process_asm): Create .offload_func_table, + similar to pre-existing .offload_var_table. + +2022-09-09 Joseph Myers <joseph@codesourcery.com> + + * ginclude/stddef.h [__STDC_VERSION__ > 201710L] (unreachable): + New macro. + +2022-09-09 Kewen Lin <linkw@linux.ibm.com> + + PR middle-end/106833 + * tree.cc (verify_opaque_type): New function. + (verify_type): Call verify_opaque_type for OPAQUE_TYPE. + +2022-09-09 Kwok Cheung Yeung <kcy@codesourcery.com> + + * config/gcn/gcn-builtins.def (FABSVF, LDEXPVF, LDEXPV, FREXPVF_EXP, + FREXPVF_MANT, FREXPV_EXP, FREXPV_MANT): Add new builtins. + * config/gcn/gcn-protos.h (gcn_dconst1over2pi): New prototype. + * config/gcn/gcn-valu.md (MATH_UNOP_1OR2REG, MATH_UNOP_1REG, + MATH_UNOP_TRIG): New iterators. + (math_unop): New attributes. + (<math_unop><mode>2, <math_unop><mode>2<exec>, + <math_unop><mode>2, <math_unop><mode>2<exec>, + *<math_unop><mode>2_insn, *<math_unop><mode>2<exec>_insn, + ldexp<mode>3, ldexp<mode>3<exec>, + frexp<mode>_exp2, frexp<mode>_mant2, + frexp<mode>_exp2<exec>, frexp<mode>_mant2<exec>): New instructions. + (<math_unop><mode>2, <math_unop><mode>2<exec>): New expanders. + * config/gcn/gcn.cc (init_ext_gcn_constants): Update definition of + dconst1over2pi. + (gcn_dconst1over2pi): New. + (gcn_builtin_type_index): Add entry for v64df type. + (v64df_type_node): New. + (gcn_init_builtin_types): Initialize v64df_type_node. + (gcn_expand_builtin_1): Expand new builtins to instructions. + (print_operand): Fix assembler output for 1/(2*PI) constant. + * config/gcn/gcn.md (unspec): Add new entries. + +2022-09-09 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106722 + * tree-predcom.cc (ref_at_iteration): Do not associate the + constant part of the offset into the MEM_REF offset + operand, across a non-zero offset. + +2022-09-09 Kito Cheng <kito.cheng@sifive.com> + + * common/config/riscv/riscv-common.cc (RISCV_USE_CUSTOMISED_MULTI_LIB): + Move forward for cover all all necessary functions for suppress + unused function warnings. + (riscv_multi_lib_check): Move forward, and tweak message to suppress + -Werror=format-diag warning. + +2022-09-09 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106881 + * gimple-predicate-analysis.cc (simple_control_dep_chain): + Add only non-fallthru edges and avoid the same set of edges + as compute_control_dep_chain_pdom does. + +2022-09-09 Jan-Benedict Glaw <jbglaw@lug-owl.de> + + * doc/tm.texi.in (TARGET_OVERRIDES_FORMAT_ATTRIBUTES): Document requirement + of TARGET_OVERRIDES_FORMAT_ATTRIBUTES_COUNT being defined as well. + * doc/tm.texi: Regenerate. + +2022-09-09 Martin Liska <mliska@suse.cz> + + * optc-save-gen.awk: Always compare array option values with memcmp. + +2022-09-08 Jonathan Wakely <jwakely@redhat.com> + + PR c++/106838 + * doc/extend.texi (Type Traits): Fix requirements. Document + __is_aggregate and __is_final. + +2022-09-08 Tim Lange <mail@tim-lange.me> + + PR analyzer/106625 + * doc/invoke.texi: + State that the checker also reasons about symbolic values. + +2022-09-08 Richard Sandiford <richard.sandiford@arm.com> + + PR tree-optimization/106886 + * tree-vect-slp.cc (vect_optimize_slp_pass::get_result_with_layout): + Fix copying of scalar stmts. + +2022-09-08 Chung-Lin Tang <cltang@codesourcery.com> + + * config/nios2/linux.h (MUSL_DYNAMIC_LINKER): Add #undef before #define. + +2022-09-08 Richard Biener <rguenther@suse.de> + + PR middle-end/106870 + * gimple-harden-conditionals.cc (insert_check_and_trap): + Set the control-altering flag on the built IFN_TRAP. + * gimple.cc (gimple_build_builtin_unreachable): Likewise. + * tree-cfg.cc (handle_abnormal_edges): Set the control-altering + flag on the .ABNORMAL_DISPATCHER call. + * tree-cfgcleanup.cc (cleanup_call_ctrl_altering_flag): Avoid + resetting the control altering flag for ECF_NORETURN calls. + (cleanup_control_flow_bb): Set the control altering flag on + discovered noreturn calls. + * symtab-thunks.cc (expand_thunk): Set the control altering + flag for the noreturn tailcall case. + * tree-eh.cc (lower_resx): Likewisw for trap and unwind_resume + calls. + +2022-09-08 Jakub Jelinek <jakub@redhat.com> + + * omp-expand.cc (expand_omp_ordered_sink): Add CONT_BB argument. + Add doacross(sink:omp_cur_iteration-1) support. + (expand_omp_ordered_source_sink): Clear counts[fd->ordered + 1]. + Adjust expand_omp_ordered_sink caller. + (expand_omp_for_ordered_loops): If counts[fd->ordered + 1] is + non-NULL, set that variable to true at the start of outermost + non-collapsed loop and set it to false at the end of innermost + ordered loop. + (expand_omp_for_generic): If fd->ordered, allocate + 1 + (fd->ordered - fd->collapse) further elements in counts array. + Copy to counts + 2 + fd->ordered the counts of fd->collapse .. + fd->ordered - 1 loop if any. + +2022-09-08 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106881 + * gimple-predicate-analysis.cc (compute_control_dep_chain_pdom): + Add only non-fallthru edges and avoid the same set of edges + as the caller does. + +2022-09-08 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-fold.cc + (fold_using_range::range_of_builtin_int_call): Use fpclassify like API. + * range-op-float.cc (finite_operand_p): Same. + (finite_operands_p): Same. + (foperator_lt::fold_range): Same. + (foperator_le::fold_range): Same. + (foperator_gt::fold_range): Same. + (foperator_ge::fold_range): Same. + (foperator_unordered::fold_range): Same. + (foperator_unordered::op1_range): Same. + (foperator_ordered::fold_range): Same. + * value-range.cc (frange::set_nan): Same. + (frange::set_signbit): Same. + (frange::union_): Same. + (frange::intersect): Same. + (frange::operator==): Same. + (frange::singleton_p): Same. + (frange::verify_range): Same. + (range_tests_nan): Same. + (range_tests_floats): Same. + * value-range.h(frange::known_finite): New. + (frange::maybe_inf): New. + (frange::known_inf): New. + (frange::maybe_nan): New. + (frange::known_nan): New. + (frange::known_signbit): New. + +2022-09-08 Iain Buclaw <ibuclaw@gdcproject.org> + + * config/darwin-d.cc: Include tm.h. + * config/dragonfly-d.cc: Likewise. + * config/freebsd-d.cc: Remove memmodel.h. + * config/glibc-d.cc: Likewise. + * config/netbsd-d.cc: Include tm.h. + * config/openbsd-d.cc: Likewise. + * config/sol2-d.cc: Likewise. + +2022-09-08 Christophe Lyon <christophe.lyon@arm.com> + + * config/arm/mve.md (mve_vqshluq_n_s<mode>): Use + MVE_pred/MVE_constraint instead of mve_imm_7/Ra. + (mve_vqshluq_m_n_s<mode>): Likewise. + (mve_vqrshrnbq_n_<supf><mode>): Use MVE_pred3/MVE_constraint3 + instead of mve_imm_8/Rb. + (mve_vqrshrunbq_n_s<mode>): Likewise. + (mve_vqrshrntq_n_<supf><mode>): Likewise. + (mve_vqrshruntq_n_s<mode>): Likewise. + (mve_vrshrnbq_n_<supf><mode>): Likewise. + (mve_vrshrntq_n_<supf><mode>): Likewise. + (mve_vqrshrnbq_m_n_<supf><mode>): Likewise. + (mve_vqrshrntq_m_n_<supf><mode>): Likewise. + (mve_vrshrnbq_m_n_<supf><mode>): Likewise. + (mve_vrshrntq_m_n_<supf><mode>): Likewise. + (mve_vqrshrunbq_m_n_s<mode>): Likewise. + (mve_vsriq_n_<supf><mode): Use MVE_pred2/MVE_constraint2 instead + of mve_imm_selective_upto_8/Rg. + (mve_vsriq_m_n_<supf><mode>): Likewise. + +2022-09-08 Jiufu Guo <guojiufu@linux.ibm.com> + + * config/rs6000/rs6000.md (splitter for set to and_mask constants): + Use int_reg_operand (instead of int_reg_operand_not_pseudo). + (splitter for multi-insn constant loads): Ditto. + +2022-09-08 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * config/rs6000/rtems.h (CPP_OS_DEFAULT_SPEC): Define __PPC_VRSAVE__ if + -mvrsave is present. + * config/rs6000/t-rtems: Add -mvrsave multilib variants for + -mcpu=e6500. + +2022-09-07 Martin Liska <mliska@suse.cz> + + * configure.ac: Restore detection of HAVE_XCOFF_DWARF_EXTRAS. + * config/rs6000/rs6000.cc (HAVE_XCOFF_DWARF_EXTRAS): Reset it. + * configure: Regenerate. + * config.in: Regenerate. + +2022-09-07 Surya Kumari Jangala <jskumari@linux.ibm.com> + + PR rtl-optimization/105586 + * sched-rgn.cc (save_state_for_fallthru_edge): New function. + (schedule_region): Use it for all blocks. + +2022-09-07 Joseph Myers <joseph@codesourcery.com> + + * ginclude/stdalign.h [defined __STDC_VERSION__ && + __STDC_VERSION__ > 201710L]: Disable all content. + * ginclude/stdbool.h [defined __STDC_VERSION__ && __STDC_VERSION__ + > 201710L] (bool, true, false): Do not define. + +2022-09-07 Martin Liska <mliska@suse.cz> + + PR bootstrap/106855 + * collect2.cc (scan_prog_file): Restore if XCOFF_DEBUGGING_INFO. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): + Restore usage of XCOFF_DEBUGGING_INFO. + * config/rs6000/xcoff.h (XCOFF_DEBUGGING_INFO): Restore. + * dwarf2asm.cc (XCOFF_DEBUGGING_INFO): Restore support for + XCOFF_DEBUGGING_INFO. + (dw2_asm_output_nstring): Likewise. + (USE_LINKONCE_INDIRECT): Likewise. + * dwarf2out.cc (XCOFF_DEBUGGING_INFO): Likewise. + (HAVE_XCOFF_DWARF_EXTRAS): Likewise. + (output_fde): Likewise. + (output_call_frame_info): Likewise. + (have_macinfo): Likewise. + (add_AT_loc_list): Likewise. + (add_AT_view_list): Likewise. + (output_compilation_unit_header): Likewise. + (output_pubnames): Likewise. + (output_aranges): Likewise. + (output_line_info): Likewise. + (output_macinfo): Likewise. + (dwarf2out_finish): Likewise. + (dwarf2out_early_finish): Likewise. + +2022-09-07 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106866 + * tree-ssa-dce.cc (eliminate_unnecessary_stmts): When + we changed cfun->calls_setjmp make sure to purge all + abnormal call edges. + +2022-09-07 Xianmiao Qu <cooper.qu@linux.alibaba.com> + + * config/csky/csky.cc (csky_emit_compare_float): Fix the expanding of + float LE comparing with zero for fpuv3. + * config/csky/csky.h (TARGET_SUPPORT_FPV2): New, true if any fpuv2 + features are enabled. + +2022-09-07 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106860 + * tree-ssa-loop-split.cc (split_loop): Find the exit to + latch edge from the loop exit edge instead of from the + latch. Verify we're going to find it. + +2022-09-07 Richard Biener <rguenther@suse.de> + + * gimple-predicate-analysis.cc (dfs_mark_dominating_region): + Adjust to take the region exit source as argument. + (uninit_analysis::init_from_phi_def): Adjust. + (uninit_analysis::init_use_preds): Mark the dominating region + before computing control dependences. + +2022-09-07 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64.md (*mov<SHORT:mode>_aarch64): Extend + w<-w, r<-w and w<-r alternatives to !simd, using 32-bit moves + in that case. Extend w<-r to w<-Z. + (*mov<HFBF:mode>_aarch64): Likewise, but with Y instead of Z. + (*movti_aarch64): Use an FMOV from XZR for w<-Z if MOVI is not + available. + (define_split): Do not apply the floating-point immediate-to-register + split to zeros, even if MOVI is not available. + +2022-09-07 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64.cc (aarch64_conditional_register_usage): + Disallow use of FPRs in register asms for !TARGET_FLOAT. + +2022-09-07 Lulu Cheng <chenglulu@loongson.cn> + + PR target/106828 + * config/loongarch/loongarch.cc (loongarch_asan_shadow_offset): New. + (TARGET_ASAN_SHADOW_OFFSET): New. + +2022-09-07 Jakub Jelinek <jakub@redhat.com> + + * doc/invoke.texi (-Wno-unicode): Document. + +2022-09-07 Jiufu Guo <guojiufu@linux.ibm.com> + + * config/rs6000/rs6000.md (const_scalar_int splitter): Remove. + +2022-09-07 Jiufu Guo <guojiufu@linux.ibm.com> + + * config/rs6000/rs6000.md: (constant splitters): Use "(pc)" as the + replacements. + +2022-09-07 liuhongt <hongtao.liu@intel.com> + + PR tree-optimization/103144 + * tree-vect-loop.cc (vect_is_nonlinear_iv_evolution): New function. + (vect_analyze_scalar_cycles_1): Detect nonlinear iv by upper function. + (vect_create_nonlinear_iv_init): New function. + (vect_peel_nonlinear_iv_init): Ditto. + (vect_create_nonlinear_iv_step): Ditto + (vect_create_nonlinear_iv_vec_step): Ditto + (vect_update_nonlinear_iv): Ditto + (vectorizable_nonlinear_induction): Ditto. + (vectorizable_induction): Call + vectorizable_nonlinear_induction when induction_type is not + vect_step_op_add. + * tree-vect-loop-manip.cc (vect_update_ivs_after_vectorizer): + Update nonlinear iv for epilogue loop. + * tree-vectorizer.h (enum vect_induction_op_type): New enum. + (STMT_VINFO_LOOP_PHI_EVOLUTION_TYPE): New Macro. + +2022-09-06 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106754 + * gimple-predicate-analysis.cc (compute_control_dep_chain_pdom): + New function, split out from compute_control_dep_chain. Handle + loop-exit like conditions here by pushing to the control vector. + (compute_control_dep_chain): Adjust and streamline dumping. + In the wrapper perform a post-dominator walk as well. + (uninit_analysis::init_use_preds): Remove premature early exit. + +2022-09-06 Max Filippov <jcmvbkbc@gmail.com> + + * config/xtensa/linux.h (LINK_SPEC): Add static-pie. + +2022-09-06 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (build_le): Handle NANs and going past infinity. + (build_lt): Same. + (build_ge): Same. + (build_gt): Same. + (foperator_lt::op1_range): Avoid adjustments to range if build_* + returned false. + (foperator_lt::op2_range): Same. + (foperator_le::op1_range): Same. + (foperator_le::op2_range): Same. + (foperator_gt::op1_range): Same. + (foperator_gt::op2_range): Same. + +2022-09-06 Richard Biener <rguenther@suse.de> + + * gimple-predicate-analysis.cc (compute_control_dep_chain): + Add output flag to indicate whether we possibly have dropped + any chains. Return whether the info is complete from the + wrapping overload. + (uninit_analysis::init_use_preds): Adjust accordingly, with + a workaround for PR106754. + (uninit_analysis::init_from_phi_def): Properly guard the + case where we complete an empty chain. + +2022-09-06 Jan-Benedict Glaw <jbglaw@lug-owl.de> + + * config/msp430/msp430.cc (msp430_single_op_cost): Document unused argument. + +2022-09-06 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> + + * tree-ssa-forwprop.cc (simplify_permutation): Set res_type to a vector + type with same element type as arg0, and length as op2. + +2022-09-06 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106844 + * gimple-predicate-analysis.cc (compute_control_dep_chain): + Return whether we found a chain. + +2022-09-06 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106841 + * tree-vect-slp.cc (vect_detect_hybrid_slp): Also process + scatter/gather offset. + +2022-09-06 Jan-Benedict Glaw <jbglaw@lug-owl.de> + + * config/bpf/bpf.h (REGNO_REG_CLASS): Reference arguments as (void). + +2022-09-06 Jakub Jelinek <jakub@redhat.com> + + * gimple.h (enum gf_mask): Add GF_OMP_ORDERED_STANDALONE enumerator. + (gimple_omp_subcode): Use GIMPLE_OMP_ORDERED instead of + GIMPLE_OMP_TEAMS as upper bound. + (gimple_omp_ordered_standalone_p, gimple_omp_ordered_standalone): New + inline functions. + * gimplify.cc (find_standalone_omp_ordered): Look for OMP_ORDERED with + NULL OMP_ORDERED_BODY rather than with OMP_DOACROSS clause. + (gimplify_expr): Call gimple_omp_ordered_standalone for OMP_ORDERED + with NULL OMP_ORDERED_BODY. + * omp-low.cc (check_omp_nesting_restrictions): Use + gimple_omp_ordered_standalone_p test instead of + omp_find_clause (..., OMP_CLAUSE_DOACROSS). + (lower_omp_ordered): Likewise. + * omp-expand.cc (expand_omp, build_omp_regions_1, + omp_make_gimple_edges): Likewise. + +2022-09-06 Xianmiao Qu <cooper.qu@linux.alibaba.com> + + * config/csky/csky.md (cskyv2_addcc): Fix missing operand. + (cskyv2_addcc_invert): Likewise. + +2022-09-06 Jose E. Marchesi <jose.marchesi@oracle.com> + + * config/bpf/bpf.cc (bpf_expand_prologue): Remove unused automatic + `insn'. + (bpf_expand_epilogue): Likewise. + +2022-09-06 liuhongt <hongtao.liu@intel.com> + + * config/i386/i386-builtin.def (IX86_BUILTIN_CVTPS2PH512): + Map to CODE_FOR_avx512f_vcvtps2ph512_mask_sae. + * config/i386/sse.md (<mask_codefor>avx512f_vcvtps2ph512<mask_name>): Extend to .. + (<mask_codefor>avx512f_vcvtps2ph512<mask_name><round_saeonly_name>): .. this. + (avx512f_vcvtps2ph512_mask_sae): New expander + +2022-09-05 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-fold.cc + (fold_using_range::range_of_builtin_int_call): Ignore sign bit + when there's the possibility of a NAN. + +2022-09-05 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-fold.cc + (fold_using_range::range_of_builtin_int_call): Fold a set signbit + in __builtin_signbit to nonzero. + +2022-09-05 Alexander Monakov <amonakov@ispras.ru> + + PR target/106453 + * config/i386/i386.md (sse4_2_crc32di): Model that only low 32 + bits of operand 0 are consumed, and the result is zero-extended + to 64 bits. + +2022-09-05 Aldy Hernandez <aldyh@redhat.com> + + PR middle-end/106831 + * value-range.h (frange::supports_p): Disable decimal floats. + * range-op-float.cc (frange_drop_inf): Remove DECIMAL_FLOAT_MODE_P + check. + (frange_drop_ninf): Same. + +2022-09-05 Aldy Hernandez <aldyh@redhat.com> + + PR middle-end/106824 + * value-range.cc (frange::set_nan): Set undefined when updating a + NAN to a non-NAN. + +2022-09-05 Kito Cheng <kito.cheng@sifive.com> + + * config/riscv/riscv.cc (riscv_option_override): Fix wrong + condition for MASK_DIV and simplify incompatible checking. + * config/riscv/riscv.md (muldi3): Adding parentheses. + +2022-09-05 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/aarch64/aarch64.cc (aarch64_validate_march): Check if invalid arch + string is a valid -mcpu string and emit hint. + +2022-09-05 LiaoShihua <shihua@iscas.ac.cn> + + * common/config/riscv/riscv-common.cc: Add Zmmul. + * config/riscv/riscv-opts.h (MASK_ZMMUL): New. + (TARGET_ZMMUL): Ditto. + * config/riscv/riscv.cc (riscv_option_override):Ditto. + * config/riscv/riscv.md: Add Zmmul + * config/riscv/riscv.opt: Ditto. + +2022-09-05 Richard Biener <rguenther@suse.de> + + * tree-cfg.h (get_cases_for_edge): Declare. + * tree-cfg.cc (get_cases_for_edge): Export. + * tree-ssa-uninit.cc (execute_late_warn_uninitialized): + Start and end recording case labels. + * gimple-predicate-analysis.cc (MAX_SWITCH_CASES): Remove. + (predicate::init_from_control_deps): Use get_cases_for_edge. + +2022-09-05 Richard Biener <rguenther@suse.de> + + * gimple-predicate-analysis.cc (MAX_POSTDOM_CHECK): Remove. + (compute_control_dep_chain): Move uninit-control-dep-attempts + checking where it also counts the post-dominator check + invocations. + +2022-09-05 Richard Biener <rguenther@suse.de> + + * gimple-predicate-analysis.h (predicate::debug): New. + (predicate::dump): Add FILE * argument, add base overload. + * gimple-predicate-analysis.cc (debug): New. + (dump_pred_info): Add FILE * argument. + (dump_pred_chain): Likewise. + (predicate::dump): Split out preamble into overload. Add + FILE * argument. + (predicate::debug): New. + (predicate::simplify): Adjust. + (predicate::normalize): Likewise. + (predicate::init_from_control_deps): Likewise. + +2022-09-05 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-protos.h + (aarch64_init_simd_builtins): Remove prototype. + * config/aarch64/aarch64-builtins.cc + (aarch64_simd_builtins_initialized_p): Delete. + (aarch64_init_simd_builtins): Make static. Remove protection + against multiple calls. + * config/aarch64/aarch64-c.cc (aarch64_pragma_target_parse): Remove + lazy SIMD builtin initialization. + * config/aarch64/aarch64.cc + (aarch64_option_valid_attribute_p): Likewise. + +2022-09-05 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/genopts/loongarch.opt.in: Add + -mdirect-extern-access option. + * config/loongarch/loongarch.opt: Regenerate. + * config/loongarch/loongarch.cc + (loongarch_symbol_binds_local_p): Return true if + TARGET_DIRECT_EXTERN_ACCESS. + (loongarch_option_override_internal): Complain if + -mdirect-extern-access is used with -fPIC or -fpic. + * doc/invoke.texi: Document -mdirect-extern-access for + LoongArch. + +2022-09-05 Martin Liska <mliska@suse.cz> + + * doc/tm.texi.in: Rename DEBUGGER_REGISTER_NUMBER to + DEBUGGER_REGNO. + * doc/tm.texi: Regenerate. + +2022-09-05 Martin Liska <mliska@suse.cz> + + * config/aarch64/aarch64-protos.h (aarch64_dbx_regno): + Rename DBX_REGISTER_NUMBER to DEBUGGER_REGNO. + (aarch64_debugger_regno): Likewise. + * config/aarch64/aarch64.cc (aarch64_dbx_regno): Likewise. + (aarch64_debugger_regno): Likewise. + * config/aarch64/aarch64.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + (DWARF_FRAME_REGNUM): Likewise. + * config/alpha/alpha.h (DWARF_FRAME_REGNUM): Likewise. + * config/arc/arc.cc (arc_init_reg_tables): Likewise. + * config/arc/arc.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/arm/arm-protos.h (arm_dbx_regno): Likewise. + (arm_debugger_regno): Likewise. + * config/arm/arm.cc (arm_dbx_regno): Likewise. + (arm_debugger_regno): Likewise. + * config/arm/arm.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/bfin/bfin.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/c6x/c6x.cc: Likewise. + * config/c6x/c6x.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/cris/cris.h (enum reg_class): Likewise. + (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/csky/csky.cc (enum reg_class): Likewise. + * config/csky/csky.h (DWARF_FRAME_REGNUM): Likewise. + (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/frv/frv.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/gcn/gcn-hsa.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/gcn/gcn.cc (print_operand): Likewise. + * config/i386/bsd.h (ASM_QUAD): Likewise. + * config/i386/cygming.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + (DWARF_FRAME_REGNUM): Likewise. + * config/i386/darwin.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/i386/djgpp.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/i386/dragonfly.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/i386/freebsd.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/i386/gas.h: Likewise. + * config/i386/gnu-user.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/i386/i386.cc (enum reg_class): Likewise. + * config/i386/i386.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/i386/i386elf.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/i386/iamcu.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/i386/lynx.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/i386/netbsd-elf.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/i386/nto.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/i386/openbsdelf.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/i386/sysv4.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/i386/vxworks.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/i386/x86-64.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/ia64/ia64-protos.h (ia64_dbx_regno): Likewise. + (ia64_debugger_regno): Likewise. + * config/ia64/ia64.cc (ia64_output_function_prologue): Likewise. + (ia64_dbx_regno): Likewise. + (ia64_debugger_regno): Likewise. + (process_cfa_adjust_cfa): Likewise. + (process_cfa_register): Likewise. + (ia64_asm_unwind_emit): Likewise. + * config/ia64/ia64.h: Likewise. + * config/ia64/sysv4.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/lm32/lm32.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/m32c/m32c.cc (m32c_eh_return_stackadj_rtx): Likewise. + * config/m32c/m32c.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/m68k/linux.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/m68k/m68k.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + (__transfer_from_trampoline): Likewise. + * config/m68k/m68kelf.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/m68k/netbsd-elf.h (M68K_STATIC_CHAIN_REG_NAME): Likewise. + (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/microblaze/microblaze.cc (microblaze_option_override): Likewise. + * config/microblaze/microblaze.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + (GP_DBX_FIRST): Likewise. + (GP_DEBUGGER_FIRST): Likewise. + * config/mips/vxworks.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/mmix/mmix-protos.h (mmix_dbx_regno): Likewise. + (mmix_debugger_regno): Likewise. + * config/mmix/mmix.cc (mmix_dbx_regno): Likewise. + (mmix_debugger_regno): Likewise. + * config/mmix/mmix.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/nds32/nds32-protos.h (nds32_dbx_regno): Likewise. + (nds32_debugger_regno): Likewise. + * config/nds32/nds32.cc (nds32_dbx_regno): Likewise. + (nds32_debugger_regno): Likewise. + (nds32_use_blocks_for_constant_p): Likewise. + * config/nds32/nds32.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/nvptx/nvptx.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/or1k/or1k.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/pa/pa32-regs.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/pa/pa64-regs.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/rs6000/rs6000-protos.h (rs6000_dbx_regno): Likewise. + (rs6000_debugger_regno): Likewise. + * config/rs6000/rs6000.cc (rs6000_dbx_regno): Likewise. + (rs6000_debugger_regno): Likewise. + * config/rs6000/rs6000.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + (DWARF2_FRAME_REG_OUT): Likewise. + * config/s390/s390.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/sh/elf.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/sh/linux.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/sh/sh.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + (SH_DBX_REGISTER_NUMBER): Likewise. + (SH_DEBUGGER_REGNO): Likewise. + * config/visium/visium.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/xtensa/elf.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/xtensa/linux.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/xtensa/uclinux.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * config/xtensa/xtensa-protos.h (xtensa_dbx_regno): Likewise. + (xtensa_debugger_regno): Likewise. + * config/xtensa/xtensa.cc (xtensa_dbx_regno): Likewise. + (xtensa_debugger_regno): Likewise. + * config/xtensa/xtensa.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + * defaults.h (DBX_REGISTER_NUMBER): Likewise. + (DEBUGGER_REGNO): Likewise. + (DWARF_FRAME_REGNUM): Likewise. + * doc/tm.texi: Likewise. + * doc/tm.texi.in: Likewise. + * dwarf2out.cc (dbx_reg_number): Likewise. + (debugger_reg_number): Likewise. + (reg_loc_descriptor): Likewise. + (multiple_reg_loc_descriptor): Likewise. + (mem_loc_descriptor): Likewise. + * except.cc: Likewise. + +2022-09-05 konglin1 <lingling.kong@intel.com> + + PR target/106742 + * config/i386/i386-expand.cc (ix86_expand_vector_init_duplicate): + Handle V8BF mode. + (expand_vec_perm_broadcast_1): Ditto. + * config/i386/sse.md (avx512fmaskhalfmode): Add BF vector mode. + (vec_set<mode>_0): Add @ to it. + (@vec_set<mode>_0): Ditto. + (vec_interleave_high<mode><mask_name>): Ditto. + (@vec_interleave_high<mode><mask_name>): Ditto. + (vec_interleave_low<mode><mask_name>): Ditto. + (@vec_interleave_low<mode><mask_name>): Ditto. + * config/i386/subst.md (SUBST_V): Add BF vector mode. + +2022-09-05 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (early_nan_resolve): Remove. + (frange::intersect): Handle NANs. + +2022-09-04 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (frange::union_): Do not drop properties when + unioning a NAN with something else. + (range_tests_signed_zeros): Add tests. + +2022-09-04 Aldy Hernandez <aldyh@redhat.com> + + * real.cc (encode_ieee_single): Use real_isdenormal. + (encode_ieee_double): Same. + (encode_ieee_extended): Same. + (encode_ieee_quad): Same. + (encode_ieee_half): Same. + (encode_arm_bfloat_half): Same. + * real.h (real_isdenormal): New. + +2022-09-03 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (frange::singleton_p): Move NAN check to the top. + +2022-09-03 Jan-Benedict Glaw <jbglaw@lug-owl.de> + + * config/nvptx/nvptx.h (ASM_OUTPUT_DEF): Reference macro arguments. + +2022-09-03 Jakub Jelinek <jakub@redhat.com> + + * tree-core.h (enum omp_clause_code): Add OMP_CLAUSE_DOACROSS. + (enum omp_clause_depend_kind): Remove OMP_CLAUSE_DEPEND_SOURCE + and OMP_CLAUSE_DEPEND_SINK, add OMP_CLAUSE_DEPEND_INVALID. + (enum omp_clause_doacross_kind): New type. + (struct tree_omp_clause): Add subcode.doacross_kind member. + * tree.h (OMP_CLAUSE_DEPEND_SINK_NEGATIVE): Remove. + (OMP_CLAUSE_DOACROSS_KIND): Define. + (OMP_CLAUSE_DOACROSS_SINK_NEGATIVE): Define. + (OMP_CLAUSE_DOACROSS_DEPEND): Define. + (OMP_CLAUSE_ORDERED_DOACROSS): Define. + * tree.cc (omp_clause_num_ops, omp_clause_code_name): Add + OMP_CLAUSE_DOACROSS entries. + * tree-nested.cc (convert_nonlocal_omp_clauses, + convert_local_omp_clauses): Handle OMP_CLAUSE_DOACROSS. + * tree-pretty-print.cc (dump_omp_clause): Don't handle + OMP_CLAUSE_DEPEND_SOURCE and OMP_CLAUSE_DEPEND_SINK. Handle + OMP_CLAUSE_DOACROSS. + * gimplify.cc (gimplify_omp_depend): Don't handle + OMP_CLAUSE_DEPEND_SOURCE and OMP_CLAUSE_DEPEND_SINK. + (gimplify_scan_omp_clauses): Likewise. Handle OMP_CLAUSE_DOACROSS. + (gimplify_adjust_omp_clauses): Handle OMP_CLAUSE_DOACROSS. + (find_standalone_omp_ordered): New function. + (gimplify_omp_for): When OMP_CLAUSE_ORDERED is present, search + body for OMP_ORDERED with OMP_CLAUSE_DOACROSS and if found, + set OMP_CLAUSE_ORDERED_DOACROSS. + (gimplify_omp_ordered): Don't handle OMP_CLAUSE_DEPEND_SINK or + OMP_CLAUSE_DEPEND_SOURCE, instead check OMP_CLAUSE_DOACROSS, adjust + diagnostics that presence or absence of ordered clause parameter + is irrelevant. Handle doacross(sink:omp_cur_iteration-1). Use + actual user name of the clause - doacross or depend - in diagnostics. + * omp-general.cc (omp_extract_for_data): Don't set fd->ordered + if !OMP_CLAUSE_ORDERED_DOACROSS (t). If + OMP_CLAUSE_ORDERED_DOACROSS (t) but !OMP_CLAUSE_ORDERED_EXPR (t), + set fd->ordered to -1 and set it after the loop in that case to + fd->collapse. + * omp-low.cc (check_omp_nesting_restrictions): Don't handle + OMP_CLAUSE_DEPEND_SOURCE nor OMP_CLAUSE_DEPEND_SINK, instead check + OMP_CLAUSE_DOACROSS. Use actual user name of the clause - doacross + or depend - in diagnostics. Diagnose mixing of stand-alone and + block associated ordered constructs binding to the same loop. + (lower_omp_ordered_clauses): Don't handle OMP_CLAUSE_DEPEND_SINK, + instead handle OMP_CLAUSE_DOACROSS. + (lower_omp_ordered): Look for OMP_CLAUSE_DOACROSS instead of + OMP_CLAUSE_DEPEND. + (lower_depend_clauses): Don't handle OMP_CLAUSE_DEPEND_SOURCE and + OMP_CLAUSE_DEPEND_SINK. + * omp-expand.cc (expand_omp_ordered_sink): Emit a sorry for + doacross(sink:omp_cur_iteration-1). + (expand_omp_ordered_source_sink): Use + OMP_CLAUSE_DOACROSS_SINK_NEGATIVE instead of + OMP_CLAUSE_DEPEND_SINK_NEGATIVE. Use actual user name of the clause + - doacross or depend - in diagnostics. + (expand_omp): Look for OMP_CLAUSE_DOACROSS clause instead of + OMP_CLAUSE_DEPEND. + (build_omp_regions_1): Likewise. + (omp_make_gimple_edges): Likewise. + * lto-streamer-out.cc (hash_tree): Handle OMP_CLAUSE_DOACROSS. + * tree-streamer-in.cc (unpack_ts_omp_clause_value_fields): Likewise. + * tree-streamer-out.cc (pack_ts_omp_clause_value_fields): Likewise. + +2022-09-02 David Malcolm <dmalcolm@redhat.com> + + PR c/90885 + * doc/invoke.texi (Warning Options): Add -Wxor-used-as-pow. + +2022-09-02 Iain Buclaw <ibuclaw@gdcproject.org> + + PR d/105659 + * config.gcc: Set tm_d_file to ${cpu_type}/${cpu_type}-d.h. + * config/aarch64/aarch64-d.cc: Include tm_d.h. + * config/aarch64/aarch64-protos.h (aarch64_d_target_versions): Move to + config/aarch64/aarch64-d.h. + (aarch64_d_register_target_info): Likewise. + * config/aarch64/aarch64.h (TARGET_D_CPU_VERSIONS): Likewise. + (TARGET_D_REGISTER_CPU_TARGET_INFO): Likewise. + * config/arm/arm-d.cc: Include tm_d.h and arm-protos.h instead of + tm_p.h. + * config/arm/arm-protos.h (arm_d_target_versions): Move to + config/arm/arm-d.h. + (arm_d_register_target_info): Likewise. + * config/arm/arm.h (TARGET_D_CPU_VERSIONS): Likewise. + (TARGET_D_REGISTER_CPU_TARGET_INFO): Likewise. + * config/default-d.cc: Remove memmodel.h include. + * config/freebsd-d.cc: Include tm_d.h instead of tm_p.h. + * config/glibc-d.cc: Likewise. + * config/i386/i386-d.cc: Include tm_d.h. + * config/i386/i386-protos.h (ix86_d_target_versions): Move to + config/i386/i386-d.h. + (ix86_d_register_target_info): Likewise. + (ix86_d_has_stdcall_convention): Likewise. + * config/i386/i386.h (TARGET_D_CPU_VERSIONS): Likewise. + (TARGET_D_REGISTER_CPU_TARGET_INFO): Likewise. + (TARGET_D_HAS_STDCALL_CONVENTION): Likewise. + * config/i386/winnt-d.cc: Include tm_d.h instead of tm_p.h. + * config/mips/mips-d.cc: Include tm_d.h. + * config/mips/mips-protos.h (mips_d_target_versions): Move to + config/mips/mips-d.h. + (mips_d_register_target_info): Likewise. + * config/mips/mips.h (TARGET_D_CPU_VERSIONS): Likewise. + (TARGET_D_REGISTER_CPU_TARGET_INFO): Likewise. + * config/netbsd-d.cc: Include tm_d.h instead of tm.h and memmodel.h. + * config/openbsd-d.cc: Likewise. + * config/pa/pa-d.cc: Include tm_d.h. + * config/pa/pa-protos.h (pa_d_target_versions): Move to + config/pa/pa-d.h. + (pa_d_register_target_info): Likewise. + * config/pa/pa.h (TARGET_D_CPU_VERSIONS): Likewise. + (TARGET_D_REGISTER_CPU_TARGET_INFO): Likewise. + * config/riscv/riscv-d.cc: Include tm_d.h. + * config/riscv/riscv-protos.h (riscv_d_target_versions): Move to + config/riscv/riscv-d.h. + (riscv_d_register_target_info): Likewise. + * config/riscv/riscv.h (TARGET_D_CPU_VERSIONS): Likewise. + (TARGET_D_REGISTER_CPU_TARGET_INFO): Likewise. + * config/rs6000/rs6000-d.cc: Include tm_d.h. + * config/rs6000/rs6000-protos.h (rs6000_d_target_versions): Move to + config/rs6000/rs6000-d.h. + (rs6000_d_register_target_info): Likewise. + * config/rs6000/rs6000.h (TARGET_D_CPU_VERSIONS) Likewise.: + (TARGET_D_REGISTER_CPU_TARGET_INFO) Likewise.: + * config/s390/s390-d.cc: Include tm_d.h. + * config/s390/s390-protos.h (s390_d_target_versions): Move to + config/s390/s390-d.h. + (s390_d_register_target_info): Likewise. + * config/s390/s390.h (TARGET_D_CPU_VERSIONS): Likewise. + (TARGET_D_REGISTER_CPU_TARGET_INFO): Likewise. + * config/sol2-d.cc: Include tm_d.h instead of tm.h and memmodel.h. + * config/sparc/sparc-d.cc: Include tm_d.h. + * config/sparc/sparc-protos.h (sparc_d_target_versions): Move to + config/sparc/sparc-d.h. + (sparc_d_register_target_info): Likewise. + * config/sparc/sparc.h (TARGET_D_CPU_VERSIONS): Likewise. + (TARGET_D_REGISTER_CPU_TARGET_INFO): Likewise. + * configure: Regenerate. + * configure.ac (tm_d_file): Remove defaults.h. + (tm_d_include_list): Remove options.h and insn-constants.h. + * config/aarch64/aarch64-d.h: New file. + * config/arm/arm-d.h: New file. + * config/i386/i386-d.h: New file. + * config/mips/mips-d.h: New file. + * config/pa/pa-d.h: New file. + * config/riscv/riscv-d.h: New file. + * config/rs6000/rs6000-d.h: New file. + * config/s390/s390-d.h: New file. + * config/sparc/sparc-d.h: New file. + +2022-09-02 Aldy Hernandez <aldyh@redhat.com> + + * builtins.cc (fold_builtin_inf): Convert use of real_info to dconstinf. + (fold_builtin_fpclassify): Same. + * fold-const-call.cc (fold_const_call_cc): Same. + * match.pd: Same. + * omp-low.cc (omp_reduction_init_op): Same. + * realmpfr.cc (real_from_mpfr): Same. + * tree.cc (build_complex_inf): Same. + +2022-09-02 Peter Bergner <bergner@linux.ibm.com> + + * config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_mma_builtin): Use + NOP_EXPR for MMA pointer casting. + +2022-09-02 Richard Sandiford <richard.sandiford@arm.com> + + * tree-vect-slp.cc (vect_optimize_slp_pass::internal_node_cost): + Reduce the fallback cost to 1. Only use it if the number of + input lanes is equal to the number of output lanes. + +2022-09-02 Richard Sandiford <richard.sandiford@arm.com> + + PR tree-optimization/106787 + * tree-vect-slp.cc (vect_map_to_instance): New function, split out + from... + (vect_bb_partition_graph_r): ...here. Replace the visited set + with a map from nodes to instances. Ensure that a node only + appears in one partition. + (vect_bb_partition_graph): Update accordingly. + +2022-09-02 Richard Biener <rguenther@suse.de> + + * timevar.def (TV_TREE_RPO_VN): New. + * tree-ssa-sccvn.h (do_rpo_vn): Remove one overload. + * tree-ssa-sccvn.cc (do_rpo_vn_1): Rename the worker. + (do_rpo_vn): Unify the public API, track with TV_TREE_RPO_VN. + (pass_fre::execute): Adjust. + * tree-ssa-uninit.cc (execute_early_warn_uninitialized): Adjust. + +2022-09-02 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106809 + * tree-ssa-sccvn.cc (dominaged_by_p_w_unex): Check we have + more than one successor before doing extra work. + +2022-09-02 Kito Cheng <kito.cheng@sifive.com> + + * common/config/riscv/riscv-common.cc: Include <vector>. + (struct riscv_multi_lib_info_t): New. + (riscv_subset_list::match_score): Ditto. + (find_last_appear_switch): Ditto. + (prefixed_with): Ditto. + (struct multi_lib_info_t): Ditto. + (riscv_current_arch_str): Ditto. + (riscv_current_abi_str): Ditto. + (riscv_multi_lib_info_t::parse): Ditto. + (riscv_check_cond): Ditto. + (riscv_check_conds): Ditto. + (riscv_compute_multilib): Ditto. + (TARGET_COMPUTE_MULTILIB): Defined. + * config/riscv/elf.h (LIB_SPEC): Call riscv_multi_lib_check if + doing link. + (RISCV_USE_CUSTOMISED_MULTI_LIB): New. + * config/riscv/riscv.h (riscv_multi_lib_check): New. + (EXTRA_SPEC_FUNCTIONS): Add riscv_multi_lib_check. + * config/riscv/riscv-subset.h (riscv_subset_list::match_score): New. + +2022-09-02 Kito Cheng <kito.cheng@sifive.com> + + * common/common-target.def (compute_multilib): New. + * common/common-targhooks.h (default_compute_multilib): New. + * common/common-targhooks.cc (default_compute_multilib): New. + * doc/tm.texi.in (TARGET_COMPUTE_MULTILIB): New. + * doc/tm.texi: Regen. + * gcc.cc: Include common/common-target.h. + (set_multilib_dir) Call targetm_common.compute_multilib. + (SWITCH_LIVE): Move to opts.h. + (SWITCH_FALSE): Ditto. + (SWITCH_IGNORE): Ditto. + (SWITCH_IGNORE_PERMANENTLY): Ditto. + (SWITCH_KEEP_FOR_GCC): Ditto. + (struct switchstr): Ditto. + * opts.h (SWITCH_LIVE): Move from gcc.c. + (SWITCH_FALSE): Ditto. + (SWITCH_IGNORE): Ditto. + (SWITCH_IGNORE_PERMANENTLY): Ditto. + (SWITCH_KEEP_FOR_GCC): Ditto. + (struct switchstr): Ditto. + +2022-09-02 Martin Liska <mliska@suse.cz> + + * config/pdp11/pdp11.h (PREFERRED_DEBUGGING_TYPE): Disable + debugging format. + +2022-09-02 Martin Liska <mliska@suse.cz> + + * Makefile.in: Remove -gstabs option support, DBX-related + macros and DBX debugging info support. + * collect2.cc (scan_prog_file): Likewise. + * common.opt: Likewise. + * config.gcc: Likewise. + * config.in: Likewise. + * config/aarch64/aarch64-elf.h (DBX_DEBUGGING_INFO): Likewise. + * config/alpha/alpha.cc: Likewise. + * config/alpha/elf.h (ASM_SPEC): Likewise. + * config/arc/arc.h (DBX_DEBUGGING_INFO): Likewise. + (DBX_CONTIN_LENGTH): Likewise. + * config/arm/aout.h (DBX_DEBUGGING_INFO): Likewise. + (DBX_CONTIN_LENGTH): Likewise. + * config/arm/netbsd-elf.h (DBX_CONTIN_LENGTH): Likewise. + * config/darwin.h (DSYMUTIL_SPEC): Likewise. + (ASM_DEBUG_SPEC): Likewise. + (DBX_DEBUGGING_INFO): Likewise. + (DBX_USE_BINCL): Likewise. + (DBX_CONTIN_LENGTH): Likewise. + (DBX_OUTPUT_NULL_N_SO_AT_MAIN_SOURCE_FILE_END): Likewise. + * config/epiphany/epiphany.h (DBX_DEBUGGING_INFO): Likewise. + (DBX_CONTIN_LENGTH): Likewise. + * config/i386/bsd.h (DBX_NO_XREFS): Likewise. + (DBX_CONTIN_LENGTH): Likewise. + * config/i386/gas.h (DBX_NO_XREFS): Likewise. + (DBX_CONTIN_LENGTH): Likewise. + * config/ia64/ia64.h: Likewise. + * config/ia64/sysv4.h (DBX_DEBUGGING_INFO): Likewise. + * config/m68k/linux.h (DBX_CONTIN_LENGTH): Likewise. + * config/m68k/openbsd.h (DBX_DEBUGGING_INFO): Likewise. + (DBX_CONTIN_LENGTH): Likewise. + (DBX_CONTIN_CHAR): Likewise. + * config/mips/mips.cc (mips_output_filename): Likewise. + (mips_option_override): Likewise. + * config/mips/mips.h (SUBTARGET_ASM_DEBUGGING_SPEC): Likewise. + (DBX_DEBUGGING_INFO): Likewise. + (DBX_CONTIN_LENGTH): Likewise. + (DBX_REGISTER_NUMBER): Likewise. + (GP_DBX_FIRST): Likewise. + (FP_DBX_FIRST): Likewise. + (MD_DBX_FIRST): Likewise. + * config/nvptx/nvptx.cc: Likewise. + * config/openbsd.h (DBX_NO_XREFS): Likewise. + * config/pa/pa-64.h (DBX_DEBUGGING_INFO): Likewise. + * config/pa/pa.h (ASSEMBLER_DIALECT): Likewise. + (DBX_CONTIN_LENGTH): Likewise. + * config/pa/som.h (PREFERRED_DEBUGGING_TYPE): Likewise. + (DBX_USE_BINCL): Likewise. + (DBX_LINES_FUNCTION_RELATIVE): Likewise. + (DBX_OUTPUT_NULL_N_SO_AT_MAIN_SOURCE_FILE_END): Likewise. + * config/pdp11/pdp11.cc: Likewise. + * config/pdp11/pdp11.h (DBX_DEBUGGING_INFO): Likewise. + (PREFERRED_DEBUGGING_TYPE): Likewise. + (DBX_CONTIN_LENGTH): Likewise. + * config/rs6000/rs6000-builtin.cc: Likewise. + * config/rs6000/rs6000-call.cc: Likewise. + * config/rs6000/rs6000-logue.cc (defined): Likewise. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Likewise. + (HAVE_XCOFF_DWARF_EXTRAS): Likewise. + (rs6000_xcoff_declare_function_name): Likewise. + * config/rs6000/sysv4.h (DBX_DEBUGGING_INFO): Likewise. + (DBX_FUNCTION_FIRST): Likewise. + * config/rs6000/xcoff.h (XCOFF_DEBUGGING_INFO): Likewise. + * config/rx/rx.h (DBX_DEBUGGING_INFO): Likewise. + * config/sh/elf.h (DBX_LINES_FUNCTION_RELATIVE): Likewise. + (DBX_OUTPUT_NULL_N_SO_AT_MAIN_SOURCE_FILE_END): Likewise. + * config/sol2.h (NO_DBX_BNSYM_ENSYM): Likewise. + * config/sparc/freebsd.h (DBX_CONTIN_CHAR): Likewise. + * config/sparc/netbsd-elf.h (DBX_CONTIN_CHAR): Likewise. + * config/sparc/sparc.h (DBX_CONTIN_LENGTH): Likewise. + * config/vax/vax.cc (vax_file_start): Likewise. + * config/vax/vax.h (DBX_DEBUGGING_INFO): Likewise. + (DBX_CONTIN_LENGTH): Likewise. + (DBX_CONTIN_CHAR): Likewise. + (DBX_NO_XREFS): Likewise. + (DBX_STATIC_STAB_DATA_SECTION): Likewise. + * config/vx-common.h (DBX_DEBUGGING_INFO): Likewise. + (XCOFF_DEBUGGING_INFO): Likewise. + * configure: Regenerate. Likewise. + * configure.ac: Likewise. + * debug.h: Likewise. + * doc/install.texi: Likewise. + * doc/invoke.texi: Likewise. + * doc/passes.texi: Likewise. + * doc/tm.texi: Likewise. + * doc/tm.texi.in: Likewise. + * dwarf2asm.cc (XCOFF_DEBUGGING_INFO): Likewise. + (dw2_asm_output_nstring): Likewise. + (USE_LINKONCE_INDIRECT): Likewise. + * dwarf2out.cc (XCOFF_DEBUGGING_INFO): Likewise. + (HAVE_XCOFF_DWARF_EXTRAS): Likewise. + (output_fde): Likewise. + (output_call_frame_info): Likewise. + (have_macinfo): Likewise. + (add_AT_loc_list): Likewise. + (add_AT_view_list): Likewise. + (output_compilation_unit_header): Likewise. + (output_pubnames): Likewise. + (output_aranges): Likewise. + (output_line_info): Likewise. + (output_macinfo): Likewise. + (dwarf2out_finish): Likewise. + (dwarf2out_early_finish): Likewise. + * final.cc (final_scan_insn_1): Likewise. + (rest_of_handle_final): Likewise. + * flag-types.h (enum debug_info_type): Likewise. + (DBX_DEBUG): Likewise. + (XCOFF_DEBUG): Likewise. + * function.cc (defined): Likewise. + * gcc.cc (defined): Likewise. + (ASM_DEBUG_SPEC): Likewise. + (ASM_DEBUG_OPTION_SPEC): Likewise. + * opts.cc (common_handle_option): Likewise. + (set_debug_level): Likewise. + * system.h (fancy_abort): Likewise. + * target-def.h (TARGET_ASM_CONSTRUCTOR): Likewise. + (TARGET_ASM_DESTRUCTOR): Likewise. + * toplev.cc (defined): Likewise. + * varasm.cc: Likewise. + * config/dbxcoff.h: Removed. + * config/dbxelf.h: Removed. + * dbxout.cc: Removed. + * dbxout.h: Removed. + * gstab.h: Removed. + * stab.def: Removed. + * xcoffout.cc: Removed. + * xcoffout.h: Removed. + +2022-09-02 Simon Rainer <gcc.gnu@vvalter.com> + + PR ipa/106627 + * config/i386/i386-features.cc (ix86_get_function_versions_dispatcher): + Set TREE_NOTHROW correctly for dispatcher declaration. + * config/rs6000/rs6000.cc (rs6000_get_function_versions_dispatcher): + Likewise. + +2022-09-01 Tamar Christina <tamar.christina@arm.com> + + PR other/106782 + * config/aarch64/aarch64.cc + (aarch64_vector_costs::prefer_unrolled_loop): Replace %u with + HOST_WIDE_INT_PRINT_UNSIGNED. + +2022-09-01 Richard Sandiford <richard.sandiford@arm.com> + + * tree-vect-slp.cc (vect_build_slp_tree_2): When building a + VEC_PERM_EXPR of an existing vector, set the SLP_TREE_LANES + to the number of vector elements, if that's a known constant. + (vect_optimize_slp_pass::is_compatible_layout): Remove associated + comment about zero SLP_TREE_LANES. + (vect_optimize_slp_pass::start_choosing_layouts): Iterate over + all partition members when looking for potential layouts. + Handle existing permutes of fixed-length vectors. + +2022-09-01 Uroš Bizjak <ubizjak@gmail.com> + + PR target/106707 + * config/i386/i386.md (moves to/from AX_REG into xchg peephole2): + Do not convert a move pattern where both operands are AX_REG. + +2022-09-01 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (build_le): Convert to dconst*inf. + (build_ge): Same. + * value-range.cc (frange::set_signbit): Same. + (frange::normalize_kind): Same. + (range_tests_floats): Same. + * value-range.h (vrp_val_max): Same. + (vrp_val_min): Same. + (frange::set_varying): Same. + +2022-09-01 Aldy Hernandez <aldyh@redhat.com> + + * emit-rtl.cc (init_emit_once): Initialize dconstinf and + dconstninf. + * real.h: Add dconstinf and dconstninf. + +2022-09-01 Richard Biener <rguenther@suse.de> + + * gimple-predicate-analysis.cc (compute_control_dep_chain): + Remove cycle detection, instead avoid walking backedges. + +2022-09-01 Richard Biener <rguenther@suse.de> + + * gimple-predicate-analysis.cc (compute_control_dep_chain): + New wrapping overload. + (uninit_analysis::init_use_preds): Simplify. + (uninit_analysis::init_from_phi_def): Likewise. + +2022-09-01 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-fold.cc + (fold_using_range::range_of_builtin_int_call): Add case for + CFN_BUILT_IN_SIGNBIT. + +2022-09-01 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (foperator_equal::op1_range): Do not copy sign + bit. + (foperator_not_equal::op1_range): Same. + * value-query.cc (range_query::get_tree_range): Set sign bit. + * value-range-pretty-print.cc (vrange_printer::visit): Dump sign bit. + * value-range.cc (frange::set_signbit): New. + (frange::set): Adjust for sign bit. + (frange::normalize_kind): Same. + (frange::union_): Remove useless comment. + (frange::intersect): Same. + (frange::contains_p): Adjust for sign bit. + (frange::singleton_p): Same. + (frange::verify_range): Same. + (range_tests_signbit): New tests. + (range_tests_floats): Call range_tests_signbit. + * value-range.h (class frange_props): Add signbit + (class frange): Same. + +2022-09-01 Jakub Jelinek <jakub@redhat.com> + + PR other/106782 + * dumpfile.h (dump_printf_loc): Use ATTRIBUTE_GCC_DUMP_PRINTF (3, 4) + instead of ATTRIBUTE_GCC_DUMP_PRINTF (3, 0). + * tree-parloops.cc (parloops_is_slp_reduction): Cast pointers to + derived types of gimple to gimple * to avoid -Wformat warnings. + * tree-vect-loop-manip.cc (vect_set_loop_condition, + vect_update_ivs_after_vectorizer): Likewise. + * tree-vect-stmts.cc (vectorizable_load): Likewise. + * tree-vect-patterns.cc (vect_split_statement, + vect_recog_mulhs_pattern, vect_recog_average_pattern, + vect_determine_precisions_from_range, + vect_determine_precisions_from_users): Likewise. + * gimple-loop-versioning.cc + (loop_versioning::analyze_term_using_scevs): Likewise. + * tree-vect-slp.cc (vect_build_slp_tree_1): Likewise. + (vect_build_slp_tree): Cast slp_tree to void * to avoid + -Wformat warnings. + (optimize_load_redistribution_1, vect_match_slp_patterns, + vect_build_slp_instance, vect_optimize_slp_pass::materialize, + vect_optimize_slp_pass::dump, vect_slp_convert_to_external, + vect_slp_analyze_node_operations, vect_bb_partition_graph): Likewise. + (vect_print_slp_tree): Likewise. Also use + HOST_WIDE_INT_PRINT_UNSIGNED instead of %u. + * tree-vect-loop.cc (vect_determine_vectorization_factor, + vect_analyze_scalar_cycles_1, vect_analyze_loop_operations, + vectorizable_induction, vect_transform_loop): Cast pointers to derived + types of gimple to gimple * to avoid -Wformat warnings. + (vect_analyze_loop_2): Cast slp_tree to void * to avoid + -Wformat warnings. + (vect_estimate_min_profitable_iters): Use HOST_WIDE_INT_PRINT_UNSIGNED + instead of %d. + * tree-vect-slp-patterns.cc (vect_pattern_validate_optab): Use %G + instead of %T and STMT_VINFO_STMT (SLP_TREE_REPRESENTATIVE (node)) + instead of SLP_TREE_DEF_TYPE (node). + +2022-09-01 Jakub Jelinek <jakub@redhat.com> + + PR c++/106655 + * doc/invoke.texi (-Winvalid-utf8): Document it. + +2022-09-01 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/106785 + * value-range.cc (range_tests_nan): Adjust tests for !HONOR_NANS. + (range_tests_floats): Same. + +2022-09-01 konglin1 <lingling.kong@intel.com> + + * tree-if-conv.cc (is_cond_scalar_reduction): Add MULT_EXPR + recognition. + +2022-09-01 Peter Bergner <bergner@linux.ibm.com> + + PR target/101322 + * config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_mma_builtin): + Enforce the use of a valid MMA pointer type. + +2022-09-01 zhongjuzhe <juzhe.zhong@rivai.ai> + + * config/riscv/riscv.cc (riscv_conditional_register_usage): Add vector + registers. + +2022-09-01 zhongjuzhe <juzhe.zhong@rivai.ai> + + * config/riscv/riscv.cc (riscv_const_insns): Add cost of poly_int. + (riscv_output_move): Add csrr vlenb assembly. + * config/riscv/riscv.md (move_type): Add csrr vlenb type. + (ext): New attribute. + (ext_enabled): Ditto. + (enabled): Ditto. + +2022-09-01 zhongjuzhe <juzhe.zhong@rivai.ai> + + * config/riscv/constraints.md (TARGET_VECTOR ? V_REGS : NO_REGS): Add + "vr" constraint. + (TARGET_VECTOR ? VD_REGS : NO_REGS): Add "vd" constraint. + (TARGET_VECTOR ? VM_REGS : NO_REGS): Add "vm" constraint. + (vp): Add poly constraint. + +2022-09-01 zhongjuzhe <juzhe.zhong@rivai.ai> + + * config/riscv/riscv.h (enum reg_class): Change vype to vtype. + +2022-09-01 zhongjuzhe <juzhe.zhong@rivai.ai> + + * config/riscv/riscv.cc (riscv_convert_vector_bits): Change + configuration according to TARGET_MIN_VLEN. + * config/riscv/riscv.h (UNITS_PER_FP_REG): Fix comment. + +2022-08-31 Martin Liska <mliska@suse.cz> + + * config.build: Remove deprecated ports. + * config.gcc: Likewise. + * config.host: Likewise. + * configure.ac: Likewise. + * configure: Regenerate. + * config/pa/pa-hpux10.h: Removed. + * config/pa/pa-hpux10.opt: Removed. + * config/pa/t-dce-thr: Removed. + +2022-08-31 Martin Liska <mliska@suse.cz> + + * Makefile.in: Always install limits.h and syslimits.h to + include folder. + * configure.ac: Assign STMP_FIXINC blank if + --disable-fixincludes is used. + * configure: Regenerate. + +2022-08-31 Richard Biener <rguenther@suse.de> + + * gimple-predicate-analysis.cc (predicate::init_from_control_deps): + Assert the guard_bb isn't empty and has more than one successor. + Drop appropriate parts of the predicate when an edge fails to + register a predicate. + (predicate::dump): Dump empty predicate as TRUE. + +2022-08-31 Richard Biener <rguenther@suse.de> + + PR tree-optimization/90994 + * gimple-predicate-analysis.cc (predicate::init_from_control_deps): + Ignore exceptional control flow and skip the edge for the purpose of + predicate generation also for non-calls. + +2022-08-31 Aldy Hernandez <aldyh@redhat.com> + + * value-range-storage.cc (frange_storage_slot::set_frange): Save + endpoints. + (frange_storage_slot::get_frange): Restore endpoints. + * value-range-storage.h (class frange_storage_slot): Add endpoint + fields. + +2022-08-31 Martin Liska <mliska@suse.cz> + + PR tree-optimization/106789 + * range-op-float.cc (default_frelop_fold_range): Remove the + function. + +2022-08-31 Martin Liska <mliska@suse.cz> + + * value-range.h: Add more override keywords. + +2022-08-31 Martin Liska <mliska@suse.cz> + + * value-range.h: Add override. + +2022-08-31 Richard Biener <rguenther@suse.de> + + PR tree-optimization/65244 + * gimple-predicate-analysis.h (predicate::init_from_control_deps): + Add argument to specify whether the predicate is for the USE. + * gimple-predicate-analysis.cc (predicate::init_from_control_deps): + Also include predicates effective fallthru control edges when + the predicate is for the USE. + +2022-08-31 Richard Biener <rguenther@suse.de> + + PR tree-optimization/73550 + * gimple-predicate-analysis.cc (predicate::init_from_control_deps): + Sanitize debug dumping. Handle case labels with a CASE_HIGH. + (predicate::dump): Adjust for better readability. + +2022-08-31 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + Jakub Jelinek <jakub@redhat.com> + + * omp-simd-clone.cc (simd_clone_adjust_return_type, + simd_clone_adjust_argument_types): Use known_eq (veclen, 0U) + instead of known_eq (veclen, 0) to avoid -Wsign-compare warnings. + +2022-08-31 Richard Sandiford <richard.sandiford@arm.com> + + * tree-vect-slp.cc (vect_optimize_slp_pass::dump): Remove bogus + argument. + +2022-08-31 zhongjuzhe <juzhe.zhong@rivai.ai> + + * tree-vect-loop-manip.cc (vect_gen_vector_loop_niters): Simply + initialize const_vf to 0. + +2022-08-31 Martin Liska <mliska@suse.cz> + + * config.gcc: Remove cr16. + +2022-08-30 Martin Jambor <mjambor@suse.cz> + + * vec.h (array_slice): Add constructors for non-const reference to + heap vector and pointers to heap vectors. + +2022-08-30 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (early_nan_resolve): Change comment. + (frange::union_): Handle union when one side is a NAN. + (range_tests_nan): Add tests for NAN union. + +2022-08-30 Andrew Stubbs <ams@codesourcery.com> + + * config/gcn/gcn.cc (gcn_simd_clone_compute_vecsize_and_simdlen): New. + (gcn_simd_clone_adjust): New. + (gcn_simd_clone_usable): New. + (TARGET_SIMD_CLONE_ADJUST): New. + (TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN): New. + (TARGET_SIMD_CLONE_USABLE): New. + +2022-08-30 Andrew Stubbs <ams@codesourcery.com> + + * doc/tm.texi: Regenerate. + * omp-simd-clone.cc (simd_clone_adjust_return_type): Allow zero + vecsize. + (simd_clone_adjust_argument_types): Likewise. + * target.def (compute_vecsize_and_simdlen): Document the new + vecsize_int and vecsize_float semantics. + +2022-08-30 Richard Sandiford <richard.sandiford@arm.com> + + * expmed.cc (store_bit_field_1): Fix byte offset calculation + for undefined structures. + +2022-08-30 Richard Sandiford <richard.sandiford@arm.com> + + * params.opt (-param=vect-max-layout-candidates=): New parameter. + * doc/invoke.texi (vect-max-layout-candidates): Document it. + * tree-vectorizer.h (auto_lane_permutation_t): New typedef. + (auto_load_permutation_t): Likewise. + * tree-vect-slp.cc (vect_slp_node_weight): New function. + (slpg_layout_cost): New class. + (slpg_vertex): Replace perm_in and perm_out with partition, + out_degree, weight and out_weight. + (slpg_partition_info, slpg_partition_layout_costs): New classes. + (vect_optimize_slp_pass): Likewise, cannibalizing some part of + the previous vect_optimize_slp. + (vect_optimize_slp): Use it. + +2022-08-30 Richard Sandiford <richard.sandiford@arm.com> + + * hash-traits.h (vec_hash_base): New class. + (vec_free_hash_base): Likewise. + +2022-08-30 Richard Sandiford <richard.sandiford@arm.com> + + * hash-traits.h (int_hash_base): New struct, split out from... + (int_hash): ...this class, which now inherits from int_hash_base. + * hash-map-traits.h (unbounded_hashmap_traits): Take a template + parameter for the key that provides hash and equality functions. + (unbounded_int_hashmap_traits): Turn into a type alias of + unbounded_hashmap_traits. + +2022-08-30 Richard Sandiford <richard.sandiford@arm.com> + + * graphds.cc (graphds_scc): Add a pass-back parameter for the + final node order. + * graphds.h (graphds_scc): Update prototype accordingly. + +2022-08-30 Richard Sandiford <richard.sandiford@arm.com> + + * tree-vect-slp.cc (vect_transform_slp_perm_load_1): Split out from... + (vect_transform_slp_perm_load): ...here. Use SLP_TREE_VECTYPE instead + of STMT_VINFO_VECTYPE. + +2022-08-30 Richard Sandiford <richard.sandiford@arm.com> + + * tree-vect-slp.cc (vectorizable_slp_permutation_1): Split out from... + (vectorizable_slp_permutation): ...here. + +2022-08-30 Richard Sandiford <richard.sandiford@arm.com> + + * tree-vect-stmts.cc (get_related_vectype_for_scalar_type): Check + that the requested number of units is interoperable with the requested + prevailing mode. + +2022-08-30 Martin Liska <mliska@suse.cz> + + * config.gcc: Remove the port. + * config/m32c/rtems.h: Removed. + +2022-08-30 Richard Biener <rguenther@suse.de> + + PR tree-optimization/73550 + * gimple-predicate-analysis.cc (predicate::init_from_control_deps): + Do not apply MAX_NUM_CHAINS again. + +2022-08-30 Richard Biener <rguenther@suse.de> + + * gimple-predicate-analysis.cc (format_edge_vec): Dump + both source and destination. + (dump_dep_chains): Remove. + (uninit_analysis::init_use_preds): Remove redundant + dumping of chains. + +2022-08-30 Aldy Hernandez <aldyh@redhat.com> + + * value-range-storage.cc (frange_storage_slot::get_frange): Use + frange_nan. + * value-range.cc (frange::set_nan): New. + (frange_nan): Move to header file. + (range_tests_nan): Adjust frange_nan callers to pass type. + New test. + * value-range.h (FRANGE_PROP_ACCESSOR): Remove. + (frange_nan): New. + +2022-08-30 Richard Biener <rguenther@suse.de> + + PR tree-optimization/67196 + * gimple-predicate-analysis.cc (uninit_analysis::is_use_guarded): + Simplify and normalize use prediates before first use. + +2022-08-30 Richard Biener <rguenther@suse.de> + + * gimple-predicate-analysis.cc (dump_pred_chain): Fix + parentizing and AND prepending. + (predicate::dump): Do not dump the GENERIC expanded + predicate, properly parentize and prepend ORs to the + piecewise predicate dump. + (build_pred_expr): Remove. + +2022-08-30 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (finite_operand_p): New. + (build_le): New. + (build_lt): New. + (build_ge): New. + (build_gt): New. + (foperator_equal::fold_range): New implementation with endpoints. + (foperator_equal::op1_range): Same. + (foperator_not_equal::fold_range): Same. + (foperator_not_equal::op1_range): Same. + (foperator_lt::fold_range): Same. + (foperator_lt::op1_range): Same. + (foperator_lt::op2_range): Same. + (foperator_le::fold_range): Same. + (foperator_le::op1_range): Same. + (foperator_le::op2_range): Same. + (foperator_gt::fold_range): Same. + (foperator_gt::op1_range): Same. + (foperator_gt::op2_range): Same. + (foperator_ge::fold_range): Same. + (foperator_ge::op1_range): Same. + (foperator_ge::op2_range): Same. + +2022-08-30 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (frange_set_nan): New. + (frange_drop_inf): New. + (frange_drop_ninf): New. + (foperator_equal::op1_range): Adjust for endpoints. + (foperator_lt::op1_range): Same. + (foperator_lt::op2_range): Same. + (foperator_gt::op1_range): Same. + (foperator_gt::op2_range): Same. + (foperator_unordered::op1_range): Same. + * value-query.cc (range_query::get_tree_range): Same. + * value-range-pretty-print.cc (vrange_printer::visit): Same. + * value-range-storage.cc (frange_storage_slot::get_frange): Same. + * value-range.cc (frange::set): Same. + (frange::normalize_kind): Same. + (frange::union_): Same. + (frange::intersect): Same. + (frange::operator=): Same. + (early_nan_resolve): New. + (frange::contains_p): New. + (frange::singleton_p): New. + (frange::set_nonzero): New. + (frange::nonzero_p): New. + (frange::set_zero): New. + (frange::zero_p): New. + (frange::set_nonnegative): New. + (frange_float): New. + (frange_nan): New. + (range_tests_nan): New. + (range_tests_signed_zeros): New. + (range_tests_floats): New. + (range_tests): New. + * value-range.h (frange::lower_bound): New. + (frange::upper_bound): New. + (vrp_val_min): Use real_inf with a sign instead of negating inf. + (frange::frange): New. + (frange::set_varying): Adjust for endpoints. + (real_max_representable): New. + (real_min_representable): New. + +2022-08-30 Aldy Hernandez <aldyh@redhat.com> + + * match.pd ((cmp @0 zerop) real_zerop (negate@1 @0)): Add variant + for real zero. + +2022-08-30 Martin Liska <mliska@suse.cz> + + * config/s390/s390.cc (s390_rtx_costs): Use proper type as + argument. + +2022-08-30 Richard Biener <rguenther@suse.de> + + * tree-ssa-uninit.cc (warn_uninitialized_vars): Pre-compute + the set of fallthru reachable blocks from function entry + and use that to determine wlims.always_executed. + +2022-08-30 Richard Biener <rguenther@suse.de> + + PR tree-optimization/56654 + * tree-ssa-uninit.cc (cand_cmp): New. + (find_uninit_use): First process all PHIs and collect candidate + stmts, then sort those after RPO. + (warn_uninitialized_phi): Pass on bb_to_rpo. + (execute_late_warn_uninitialized): Compute and pass on + reverse lookup of RPO number from basic block index. + +2022-08-30 Richard Biener <rguenther@suse.de> + + * gimple-predicate-analysis.h (uninit_analysis::operator()): + Remove. + * gimple-predicate-analysis.cc + (uninit_analysis::collect_phi_def_edges): Use phi_arg_set, + simplify a bit. + * tree-ssa-uninit.cc (defined_args): New global. + (compute_uninit_opnds_pos): Mask with the recorded set + of guarded maybe-uninitialized uses. + (uninit_undef_val_t::operator()): Remove. + (find_uninit_use): Process all PHI uses, recording the + guarded ones and marking the PHI result as uninitialized + consistently. + (warn_uninitialized_phi): Adjust. + (execute_late_warn_uninitialized): Get rid of the PHI worklist + and instead walk the function in RPO order. + * spellcheck.h (best_match::m_best_candidate_len): Initialize. + +2022-08-30 Tamar Christina <tamar.christina@arm.com> + + PR tree-optimization/106744 + * tree-ssa-phiopt.cc (minmax_replacement): Correct arguments. + +2022-08-30 Tamar Christina <tamar.christina@arm.com> + + * expmed.cc (store_bit_field_1): Initialize regnum to 0. + +2022-08-29 David Faust <david.faust@oracle.com> + + PR target/106745 + * config/bpf/coreout.cc (bpf_core_get_sou_member_index): Fix + computation of index for anonymous members. + +2022-08-29 Jose E. Marchesi <jose.marchesi@oracle.com> + + * config/bpf/bpf.cc (bpf_target_macros): Define __bpf__ as a + target macro. + +2022-08-29 H.J. Lu <hjl.tools@gmail.com> + + PR target/106748 + * config/i386/i386-expand.cc + (ix86_avx256_split_vector_move_misalign): Handle E_V16BFmode. + * config/i386/sse.md (V_256H): Add V16BF. + +2022-08-29 Robin Dapp <rdapp@linux.ibm.com> + + * config/s390/s390.cc (s390_address_cost): Declare. + (s390_hard_regno_nregs): Declare. + (s390_rtx_costs): Add handling for REG and MEM in SET. + +2022-08-29 Robin Dapp <rdapp@linux.ibm.com> + + * config/s390/s390.cc (expand_perm_with_vpdi): Recognize swap pattern. + (is_reverse_perm_mask): New function. + (expand_perm_with_rot): Recognize reverse pattern. + (expand_perm_with_vstbrq): New function. + (expand_perm_with_vster): Use vler/vster for element reversal on z15. + (vectorize_vec_perm_const_1): Use. + (s390_vectorize_vec_perm_const): Add expand functions. + * config/s390/vx-builtins.md: Prefer vster over vler. + +2022-08-29 Robin Dapp <rdapp@linux.ibm.com> + + * config/s390/s390.md: Remove UNSPEC_VEC_EXTRACT. + * config/s390/vector.md: Rewrite patterns to use vec_select. + * config/s390/vx-builtins.md (vec_scatter_element<V_HW_2:mode>_SI): + Likewise. + +2022-08-29 Robin Dapp <rdapp@linux.ibm.com> + + PR target/100869 + * config/s390/vector.md (@vpdi4_2<mode>): New pattern. + (rotl<mode>3_di): New pattern. + * config/s390/vx-builtins.md: Use vpdi and verll for reversing + elements. + +2022-08-29 Robin Dapp <rdapp@linux.ibm.com> + + * config/s390/s390.cc (s390_issue_rate): Add z15. + +2022-08-29 Robin Dapp <rdapp@linux.ibm.com> + + * common/config/s390/s390-common.cc: Enable -funroll-loops and + -munroll-only-small-loops for OPT_LEVELS_2_PLUS_SPEED_ONLY. + * config/s390/s390.cc (s390_loop_unroll_adjust): Do not unroll + loops larger than 12 instructions. + (s390_override_options_after_change): Set unroll options. + (s390_option_override_internal): Likewise. + * config/s390/s390.opt: Document munroll-only-small-loops. + +2022-08-29 Richard Biener <rguenther@suse.de> + + * gimple-predicate-analysis.cc (is_loop_exit, + find_control_equiv_block): Inline into single caller ... + (uninit_analysis::init_use_preds): ... here and refactor. + +2022-08-29 Richard Biener <rguenther@suse.de> + + * gimple-predicate-analysis.cc (compute_control_dep_chain): + Inline is_loop_exit and refactor, add comment about + loop exits. + +2022-08-29 Kito Cheng <kito.cheng@sifive.com> + + * config/riscv/riscv.cc (riscv_frame_info): Introduce `reset(void)`; + (riscv_frame_info::reset(void)): New. + (riscv_compute_frame_info): Use riscv_frame_info::reset instead + of memset when clean frame. + +2022-08-29 zhongjuzhe <juzhe.zhong@rivai.ai> + + * config/riscv/riscv.cc (riscv_v_ext_vector_mode_p): New function. + (riscv_classify_address): Disallow PLUS/LO_SUM/CONST_INT address types for RVV. + (riscv_address_insns): Add RVV modes condition. + (riscv_binary_cost): Ditto. + (riscv_rtx_costs): Adjust cost for RVV. + (riscv_secondary_memory_needed): Add RVV modes condition. + (riscv_hard_regno_nregs): Add RVV register allocation. + (riscv_hard_regno_mode_ok): Add RVV register allocation. + (riscv_class_max_nregs): Add RVV register allocation. + * config/riscv/riscv.h (DWARF_FRAME_REGNUM): Add VL/VTYPE and vector registers in Dwarf. + (UNITS_PER_V_REG): New macro. + (FIRST_PSEUDO_REGISTER): Adjust first pseudo num for RVV. + (V_REG_FIRST): New macro. + (V_REG_LAST): Ditto. + (V_REG_NUM): Ditto. + (V_REG_P): Ditto. + (VL_REG_P): Ditto. + (VTYPE_REG_P): Ditto. + (RISCV_DWARF_VL): Ditto. + (RISCV_DWARF_VTYPE): Ditto. + (enum reg_class): Add RVV register types. + (REG_CLASS_CONTENTS): Add RVV register types. + * config/riscv/riscv.md: Add VL/VTYPE register number constants. + +2022-08-29 zhongjuzhe <juzhe.zhong@rivai.ai> + + * config/riscv/riscv.md: Add new type for vector instructions. + +2022-08-28 Peter Bergner <bergner@linux.ibm.com> + + PR target/106017 + * config/rs6000/rs6000.cc (rs6000_invalid_conversion): Remove handling + of MMA pointer conversions. + +2022-08-27 Xi Ruoyao <xry111@xry111.site> + + * config/i386/gcc-auto-profile: Regenerate. + +2022-08-26 Aldy Hernandez <aldyh@redhat.com> + + * real.cc (real_iszero): New. + * real.h (real_iszero): New. + +2022-08-26 Aldy Hernandez <aldyh@redhat.com> + + * real.cc (real_isinf): New overload. + (real_inf): Add sign argument. + * real.h (real_isinf): New overload. + (real_inf): Add sign argument. + +2022-08-26 Marek Polacek <polacek@redhat.com> + + PR c++/81159 + * doc/invoke.texi: Document -Wself-move. + +2022-08-26 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (vrange::set): Set varying. + (vrange::set_nonzero): Same. + (vrange::set_zero): Same. + (vrange::set_nonnegative): Same. + +2022-08-26 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (foperator_equal::op1_range): Do not blindly + copy op2 range when honoring signed zeros. + +2022-08-26 Aldy Hernandez <aldyh@redhat.com> + + * tree-ssa-threadbackward.cc (possibly_profitable_path_p): Always + add newline. + (profitable_path_p): Same. + +2022-08-26 Richard Biener <rguenther@suse.de> + + * gimple-predicate-analysis.h + (uninit_analysis::use_cannot_happen): Remove. + * gimple-predicate-analysis.cc (can_be_invalidated_p): Remove. + (uninit_analysis::use_cannot_happen): Likewise. + (uninit_analysis::is_use_guarded): Do not call + use_cannot_happen. + (dump_predicates): Remove. + (simple_control_dep_chain): Remove edge overload. + +2022-08-26 Tobias Burnus <tobias@codesourcery.com> + + * internal-fn.cc (expand_GOMP_TARGET_REV): New. + * internal-fn.def (GOMP_TARGET_REV): New. + * lto-cgraph.cc (lto_output_node, verify_node_partition): Mark + 'omp target device_ancestor_host' as in_other_partition and don't + error if absent. + * omp-low.cc (create_omp_child_function): Mark as 'noclone'. + * omp-expand.cc (expand_omp_target): For reverse offload, remove + sorry, use device = GOMP_DEVICE_HOST_FALLBACK and create + empty-body nohost function. + * omp-offload.cc (execute_omp_device_lower): Handle + IFN_GOMP_TARGET_REV. + (pass_omp_target_link::execute): For ACCEL_COMPILER, don't + nullify fn argument for reverse offload + +2022-08-26 Jakub Jelinek <jakub@redhat.com> + + * builtins.def (BUILT_IN_ISSIGNALING): New built-in. + * builtins.cc (expand_builtin_issignaling): New function. + (expand_builtin_signbit): Don't overwrite target. + (expand_builtin): Handle BUILT_IN_ISSIGNALING. + (fold_builtin_classify): Likewise. + (fold_builtin_1): Likewise. + * optabs.def (issignaling_optab): New. + * fold-const-call.cc (fold_const_call_ss): Handle + BUILT_IN_ISSIGNALING. + * config/i386/i386.md (issignalingxf2): New expander. + * doc/extend.texi (__builtin_issignaling): Document. + (__builtin_isinf, __builtin_isnan): Clarify behavior with + -ffinite-math-only. + * doc/md.texi (issignaling<mode>2): Likewise. + +2022-08-26 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/106099 + * internal-fn.def (TRAP): Add ECF_LOOPING_CONST_OR_PURE flag. + * tree-cfg.cc (execute_fixup_cfg): Add IFN_TRAP instead of + __builtin_trap to avoid the need of vops. + +2022-08-26 Richard Biener <rguenther@suse.de> + + * gimple-predicate-analysis.cc (dfs_mark_dominating_region): + New helper. + (compute_control_dep_chain): Adjust to honor marked region + if provided. + (uninit_analysis::init_from_phi_def): Pre-mark the dominating + region to improve compute_control_dep_chain walking. + * vec.h (vec<T, va_heap, vl_ptr>::allocated): Add forwarder. + +2022-08-26 Richard Biener <rguenther@suse.de> + + * gimple-predicate-analysis.cc + (uninit_analysis::collect_phi_def_edges): Only expand a + PHI def edge when it is possibly undefined. + +2022-08-26 Martin Liska <mliska@suse.cz> + + * doc/extend.texi: Remove cr16 related stuff. + * doc/install.texi: Likewise. + * doc/invoke.texi: Likewise. + * doc/md.texi: Likewise. + * function-tests.cc (test_expansion_to_rtl): Likewise. + * common/config/cr16/cr16-common.cc: Removed. + * config/cr16/constraints.md: Removed. + * config/cr16/cr16-protos.h: Removed. + * config/cr16/cr16.cc: Removed. + * config/cr16/cr16.h: Removed. + * config/cr16/cr16.md: Removed. + * config/cr16/cr16.opt: Removed. + * config/cr16/predicates.md: Removed. + * config/cr16/t-cr16: Removed. + +2022-08-26 liuhongt <hongtao.liu@intel.com> + + PR target/106704 + * config/i386/i386-builtin.def (BDESC): Add + CODE_FOR_avx_blendvpd256/CODE_FOR_avx_blendvps256 to + corresponding builtins. + * config/i386/i386.cc (ix86_gimple_fold_builtin): + Don't fold IX86_BUILTIN_PBLENDVB256, IX86_BUILTIN_BLENDVPS256, + IX86_BUILTIN_BLENDVPD256 w/o TARGET_AVX2. + +2022-08-25 Marek Polacek <polacek@redhat.com> + + * ginclude/stddef.h: Define nullptr_t. + +2022-08-25 Joseph Myers <joseph@codesourcery.com> + + * gimplify.cc (gimplify_modify_expr): Convert initialization from + a variable-size CONSTRUCTOR to memset before call to + gimplify_modify_expr_rhs. + +2022-08-25 Jason Merrill <jason@redhat.com> + + * dwarf2out.cc (base_type_die): Also use DW_ATE_UTF for char8_t. + +2022-08-25 Andreas Krebbel <krebbel@linux.ibm.com> + + PR target/106101 + * config/s390/predicates.md (subreg_register_operand): New + predicate. + * config/s390/s390-protos.h (s390_gen_lowpart_subreg): New + function prototype. + * config/s390/s390.cc (s390_gen_lowpart_subreg): New function. + (s390_expand_insv): Use s390_gen_lowpart_subreg instead of + gen_lowpart. + * config/s390/s390.md ("*get_tp_64", "*zero_extendhisi2_31") + ("*zero_extendqisi2_31", "*zero_extendqihi2_31"): Likewise. + ("movstrictqi", "movstricthi", "movstrictsi"): Use the + subreg_register_operand predicate instead of register_operand. + +2022-08-25 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/loongarch-protos.h (loongarch_symbol_type): + Add SYMBOL_PCREL64 and change the description for SYMBOL_PCREL. + * config/loongarch/loongarch.cc (loongarch_attribute_table): + New attribute table. + (TARGET_ATTRIBUTE_TABLE): Define the target hook. + (loongarch_handle_model_attribute): New static function. + (loongarch_classify_symbol): Take TARGET_CMODEL_EXTREME and the + model attribute of SYMBOL_REF_DECL into account returning + SYMBOL_PCREL or SYMBOL_PCREL64. + (loongarch_use_anchors_for_symbol_p): New static function. + (TARGET_USE_ANCHORS_FOR_SYMBOL_P): Define the target hook. + (loongarch_symbol_extreme_p): New static function. + (loongarch_symbolic_constant_p): Handle SYMBOL_PCREL64. + (loongarch_symbol_insns): Likewise. + (loongarch_split_symbol_type): Likewise. + (loongarch_split_symbol): Check SYMBOL_PCREL64 instead of + TARGET_CMODEL_EXTREME for PC-relative addressing. + (loongarch_print_operand_reloc): Likewise. + * doc/extend.texi (Variable Attributes): Document new + LoongArch specific attribute. + +2022-08-25 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/loongarch.cc (loongarch_classify_symbol): + Return early if the rtx is not SYMBOL_REF. + +2022-08-25 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106737 + * tree-parloops.cc (transform_to_exit_first_loop_alt): Do not + verify SSA form. + +2022-08-25 Chenghua Xu <xuchenghua@loongson.cn> + + PR target/106459 + * config/loongarch/loongarch.cc (loongarch_build_integer): + Use HOST_WIDE_INT. + * config/loongarch/loongarch.h (IMM_REACH): Likewise. + (HWIT_1U): New Defined. + (LU12I_OPERAND): Use HOST_WIDE_INT. + (LU32I_OPERAND): Likewise. + (LU52I_OPERAND): Likewise. + (HWIT_UC_0xFFF): Likwise. + +2022-08-24 Andrew Pinski <apinski@marvell.com> + + PR target/106632 + PR target/106588 + * config/riscv/bitmanip.md (*shNadduw): Use n constraint + instead of i. + (*slliuw): Likewise. + (*bexti): Likewise. Also add a check for operands[2] to be less + than the mode bitsize. + +2022-08-24 Andrew Pinski <apinski@marvell.com> + + * config/riscv/constraints.md (DbS): New constraint. + (DnS): New constraint. + * config/riscv/bitmanip.md (*bset<mode>_1_mask): Use new constraint. + (*bclr<mode>): Likewise. + (*binvi<mode>): Likewise. + +2022-08-24 Andrew Pinski <apinski@marvell.com> + + PR target/106586 + * config/riscv/predicates.md (single_bit_mask_operand): + Use SINGLE_BIT_MASK_OPERAND instead of directly calling pow2p_hwi. + (not_single_bit_mask_operand): Likewise. + * config/riscv/riscv.cc (riscv_build_integer_1): Don't special case + 1<<31 for 32bits as it is already handled. + Call trunc_int_for_mode on the upper part after the subtraction. + (riscv_move_integer): Call trunc_int_for_mode before generating + the integer just make sure the constant has been sign extended + corectly. + (riscv_emit_int_compare): Call trunc_int_for_mode after doing the + addition for the new rhs. + * config/riscv/riscv.h (SINGLE_BIT_MASK_OPERAND): If !TARGET64BIT, + then mask off the upper 32bits of the HWI as it will be sign extended. + +2022-08-24 Andrew Pinski <apinski@marvell.com> + + * config/riscv/constraints.md (DsS): New constraint. + (DsD): New constraint. + * config/riscv/iterators.md (shiftm1c): New iterator. + * config/riscv/bitmanip.md (*bset<mode>_mask): + Use shiftm1c. + (*bset<mode>_1_mask): Likewise. + +2022-08-24 Andrew Pinski <apinski@marvell.com> + + * config/riscv/constraints.md (Ds3): New constraint. + * config/riscv/predicates.md (imm123_operand): New predicate. + * config/riscv/bitmanip.md (*shNadd): Use Ds3 and imm123_operand. + (*shNadduw): Likewise. + +2022-08-24 Andrew Pinski <apinski@marvell.com> + + * config/riscv/riscv.cc (riscv_print_operand): + Handle '~'. + (riscv_print_operand_punct_valid_p): New function + (TARGET_PRINT_OPERAND_PUNCT_VALID_P): Define. + * config/riscv/bitmanip.md (<bitmanip_optab>si2/clz_ctz_pcnt): + Use %~ instead of conditional the pattern on TARGET_64BIT. + (rotrsi3): Likewise. + (rotlsi3): Likewise. + * config/riscv/riscv.md: Add ~ to the list of modifiers. + (addsi3): Use %~ instead of conditional the pattern on TARGET_64BIT. + (subsi3): Likewise. + (negsi2): Likewise. + (mulsi3): Likewise. + (optab>si3/any_div): Likewise. + (*add<mode>hi3): Likewise. + (<optab>si3/any_shift): Likewise. + +2022-08-24 Andrew Pinski <apinski@marvell.com> + + * config/riscv/riscv.cc (riscv_print_operand): Make a mention to + keep the list in riscv.md in sync with this list. + * config/riscv/riscv.md: Add list of modifiers as comments. + +2022-08-24 Andrew Pinski <apinski@marvell.com> + + * config/riscv/sync.md (any_atomic, atomic_optab): Move to ... + * config/riscv/iterators.md: Here. + +2022-08-24 Andrew Pinski <apinski@marvell.com> + + * config/riscv/bitmanip.md + (bitmanip_bitwise, bitmanip_minmax, clz_ctz_pcna, + tbitmanip_optab, bitmanip_insn, shiftm1): Move to ... + * config/riscv/iterators.md: Here. + +2022-08-24 Andrew Pinski <apinski@marvell.com> + + * config/riscv/riscv.md (GPR): Move to new file. + (P, X, BR): Likewise. + (MOVE32, MOVE64, SHORT): Likewise. + (HISI, SUPERQI, SUBX): Likewise. + (ANYI, ANYF, SOFTF): Likewise. + (size, load, default_load): Likewise. + (softload, store, softstore): Likewise. + (reg, fmt, ifmt, amo): Likewise. + (UNITMODE, HALFMODE): Likewise. + (RINT, rint_pattern, rint_rm): Likewise. + (QUIET_COMPARISON, quiet_pattern, QUIET_PATTERN): Likewise. + (any_extend, any_shiftrt, any_shift): Likewise. + (any_bitwise): Likewise. + (any_div, any_mod): Likewise. + (any_gt, any_ge, any_lt, any_le): Likewise. + (u, su): Likewise. + (optab, insn): Likewise. + * config/riscv/iterators.md: New file. + +2022-08-24 Andrew Pinski <apinski@marvell.com> + + PR target/106601 + * config/riscv/bitmanip.md (bswaphi2): New pattern. + +2022-08-24 Andrew Pinski <apinski@marvell.com> + + PR target/106600 + * config/riscv/bitmanip.md (bswap<mode>2): Remove + condition on TARGET_64BIT as X is already conditional there. + +2022-08-24 Joseph Myers <joseph@codesourcery.com> + + * tree.cc (build_real): Give DFP dconst0 the minimum quantum + exponent for the type. + +2022-08-24 Jose E. Marchesi <jose.marchesi@oracle.com> + + PR target/106733 + * config/bpf/bpf.cc (bpf_legitimate_address_p): Recognize integer + constants as legitimate addresses for functions. + (bpf_small_register_classes_for_mode_p): Define target hook. + +2022-08-24 Richard Biener <rguenther@suse.de> + + * gimple-predicate-analysis.cc: Move predicate normalization + after the comment documenting it. + +2022-08-24 Richard Biener <rguenther@suse.de> + + * gimple-predicate-analysis.h (predicate): Split out + non-predicate related functionality into .. + (uninit_analysis): .. this new class. + * gimple-predicate-analysis.cc: Refactor into two classes. + * tree-ssa-uninit.cc (find_uninit_use): Use uninit_analysis. + +2022-08-24 Richard Biener <rguenther@suse.de> + + * gimple-predicate-analysis.cc (predicate::use_cannot_happen): + Do simple_control_dep_chain only up to cd_root, add the PHI + operand edge to the chains like init_from_phi_def does. + (predicate::is_use_guarded): Speedup early out, avoid half-way + initializing the PHI def predicate. + +2022-08-24 Jakub Jelinek <jakub@redhat.com> + + PR target/106721 + * config/i386/sse.md (shuffletype): Add V32BF, V16BF and V8BF entries. + Change V32HF, V16HF and V8HF entries from "f" to "i". + (iptr): Add V32BF, V16BF, V8BF and BF entries. + (i128vldq): Add V16HF and V16BF entries. + (avx512er_vmrcp28<mode><mask_name><round_saeonly_name>): Fix typo, + mask_opernad3 -> mask_operand3. + +2022-08-24 Martin Liska <mliska@suse.cz> + Jørgen Kvalsvik <j@lambda.is> + + * gcov.cc (add_line_counts): Add group functions to coverage + summary. + (accumulate_line_counts): Similarly for files. + +2022-08-24 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/genopts/loongarch-strings: Support code model medium. + * config/loongarch/genopts/loongarch.opt.in: Likewise. + * config/loongarch/loongarch-def.c: Likewise. + * config/loongarch/loongarch-def.h (CMODEL_LARGE): Likewise. + (CMODEL_EXTREME): Likewise. + (N_CMODEL_TYPES): Likewise. + (CMODEL_MEDIUM): Likewise. + * config/loongarch/loongarch-opts.cc: Likewise. + * config/loongarch/loongarch-opts.h (TARGET_CMODEL_MEDIUM): Likewise. + * config/loongarch/loongarch-str.h (STR_CMODEL_MEDIUM): Likewise. + * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr): + Tls symbol Loading support medium mode. + (loongarch_legitimize_call_address): When medium mode, make a symbolic + jump with two instructions. + (loongarch_option_override_internal): Support medium. + * config/loongarch/loongarch.md (@pcalau12i<mode>): New template. + (@sibcall_internal_1<mode>): New function call templates added to support + medium mode. + (@sibcall_value_internal_1<mode>): Likewise. + (@sibcall_value_multiple_internal_1<mode>): Likewise. + (@call_internal_1<mode>): Likewise. + (@call_value_internal_1<mode>): Likewise. + (@call_value_multiple_internal_1<mode>): Likewise. + * config/loongarch/loongarch.opt: Support medium. + * config/loongarch/predicates.md: Add processing about medium mode. + * doc/invoke.texi: Document for '-mcmodel=medium'. + +2022-08-24 Richard Biener <rguenther@suse.de> + + * gimple-predicate-analysis.cc (predicate::use_cannot_happen): + Start the compute_control_dep_chain walk from the immediate + dominator of the PHI. + +2022-08-23 H.J. Lu <hjl.tools@gmail.com> + + PR target/106714 + * config/i386/amxtileintrin.h (_tile_loadd_internal): Cast to + __PTRDIFF_TYPE__. + (_tile_stream_loadd_internal): Likewise. + (_tile_stored_internal): Likewise. + +2022-08-23 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106722 + * gimple-predicate-analysis.h (MAX_NUM_CHAINS, MAX_CHAIN_LEN, + MAX_POSTDOM_CHECK, MAX_SWITCH_CASES): Move ... + * gimple-predicate-analysis.cc: ... here and document. + (simple_control_dep_chain): New function, factored from + predicate::use_cannot_happen. + (predicate::use_cannot_happen): Adjust. + (predicate::predicate): Use simple_control_dep_chain as fallback. + +2022-08-23 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (foperator_equal::op1_range): Set range to + range of op2. + +2022-08-23 Richard Biener <rguenther@suse.de> + + * gimple-predicate-analysis.cc (is_loop_exit): Split out + from ... + (is_non_loop_exit_postdominating): ... here. Remove after + inlining ... + (find_control_equiv_block): ... here. + (compute_control_dep_chain): ... and here. + (predicate::is_use_guarded): Do not excempt loop exits + from short-cutting the case of the use post-dominating the + PHI definition. + +2022-08-23 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/106687 + * range-op.cc (operator_minus::lhs_op1_relation): Return VREL_LE + for the VREL_GT case as well. + +2022-08-22 Dimitar Dimitrov <dimitar@dinux.eu> + + * config/pru/pru.md (pru_<code>di3): New alternative for + two operands but without earlyclobber. + +2022-08-22 Dimitar Dimitrov <dimitar@dinux.eu> + + * config/pru/pru.md (prumov<mode>, mov<mode>): Add + variants for loading -1 consts. + +2022-08-22 Dimitar Dimitrov <dimitar@dinux.eu> + + PR target/106564 + * config/pru/constraints.md (Um): New constraint for -1. + (Uf): New constraint for IOR fill-bytes constants. + (Uz): New constraint for AND zero-bytes constants. + * config/pru/predicates.md (const_fillbytes_operand): New + predicate for IOR fill-bytes constants. + (const_zerobytes_operand): New predicate for AND zero-bytes + constants. + * config/pru/pru-protos.h (pru_output_sign_extend): Remove. + (struct pru_byterange): New struct to describe a byte range. + (pru_calc_byterange): New declaration. + * config/pru/pru.cc (pru_rtx_costs): Add penalty for + 64-bit zero-extend. + (pru_output_sign_extend): Remove. + (pru_calc_byterange): New helper function to extract byte + range info from a constant. + (pru_print_operand): Remove 'y' and 'z' print modifiers. + * config/pru/pru.md (zero_extendqidi2): New pattern. + (zero_extendhidi2): New pattern. + (zero_extendsidi2): New pattern. + (extend<EQS0:mode><EQD:mode>2): Rewrite as an expand. + (@pru_ior_fillbytes<mode>): New pattern. + (@pru_and_zerobytes<mode>): New pattern. + (<code>di3): Rewrite as an expand and handle ZERO and FILL + special cases. + (pru_<code>di3): New name for <code>di3. + (@cbranch_qbbx_const_<BIT_TEST:code><HIDI:mode>): New pattern to + handle bit-test for 64-bit registers. + +2022-08-22 Richard Biener <rguenther@suse.de> + + * gimple-predicate-analysis.h (predicate::m_use_expr): Remove. + (predicate::def_expr): Likewise. + (predicate::use_expr): Likewise. + (predicate::expr): Likewise. + * gimple-predicate-analysis.cc (predicate::def_expr): Remove. + (predicate::use_expr): Likewise. + (predicate::expr): Likewise. + (predicate::is_use_guarded): Do not build m_use_expr. + +2022-08-22 Martin Liska <mliska@suse.cz> + + PR lto/106700 + * configure.ac: Detect O_NONBLOCK flag for open. + * config.in: Regenerate. + * configure: Regenerate. + * opts-common.cc (jobserver_info::connect): Set is_connected + properly based on O_NONBLOCK. + * opts-jobserver.h (struct jobserver_info): Add is_connected + member variable. + +2022-08-22 zhongjuzhe <juzhe.zhong@rivai.ai> + + * simplify-rtx.cc (test_vector_subregs_fore_back): Make first value + and repeat value different. + +2022-08-22 Tobias Burnus <tobias@codesourcery.com> + + PR lto/106686 + * lto-wrapper.cc (free_array_of_ptrs): Move before tool_cleanup. + (tool_cleanup): Unlink offload_names. + (compile_offload_image): Take filename argument to set it early. + (compile_images_for_offload_targets): Update call; set + offload_names to NULL after freeing the array. + +2022-08-22 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105937 + * tree-ssa-uninit.cc (find_uninit_use): Do not queue PHIs + on backedges. + (execute_late_warn_uninitialized): Mark backedges. + +2022-08-22 Richard Biener <rguenther@suse.de> + + * gimple-predicate-analysis.cc (predicate::use_cannot_happen): + If the use is guarded with multiple predicate paths compute + the predicates intersection before going forward. When + compute_control_dep_chain wasn't able to come up with at + least one path from function entry to the PHI edge compute + a conservative sparse path instead. + +2022-08-20 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/loongarch-opts.cc: Allow cmodel to be extreme. + * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr): + Add extreme support for TLS GD and LD types. + (loongarch_legitimize_tls_address): Add extreme support for TLS LE + and IE. + (loongarch_split_symbol): When compiling with -mcmodel=extreme, + the symbol address will be obtained through five instructions. + (loongarch_print_operand_reloc): Add support. + (loongarch_print_operand): Add support. + (loongarch_print_operand_address): Add support. + (loongarch_option_override_internal): Set '-mcmodel=extreme' option + incompatible with '-mno-explicit-relocs'. + * config/loongarch/loongarch.md (@lui_l_hi20<mode>): + Loads bits 12-31 of data into registers. + (lui_h_lo20): Load bits 32-51 of the data and spell bits 0-31 of + the source register. + (lui_h_hi12): Load bits 52-63 of the data and spell bits 0-51 of + the source register. + * config/loongarch/predicates.md: Symbols need to be decomposed + when defining the macro TARGET_CMODEL_EXTREME + * doc/invoke.texi: Modify the description information of cmodel in the document. + Document -W[no-]extreme-plt. + +2022-08-19 Tobias Burnus <tobias@codesourcery.com> + + * config/gcn/mkoffload.cc (main): Add omp_requires_file and dbgobj to + files_to_cleanup. + * config/i386/intelmic-mkoffload.cc (prepare_target_image): Add + omp_requires_file to temp_files. + * config/nvptx/mkoffload.cc (omp_requires_file): New global static var. + (main): Remove local omp_requires_file var. + (tool_cleanup): Handle omp_requires_file. + +2022-08-19 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-path.cc (path_range_query::path_range_query): + Remove constructor that takes edge. + * gimple-range-path.h (class path_range_query): Same. + * tree-ssa-loop-ch.cc (edge_range_query): New. + (entry_loop_condition_is_static): Call edge_range_query. + +2022-08-18 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.h + (enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS): + Add new register class "ISC_REGS". + * config/xtensa/constraints.md (c): Add new register constraint. + * config/xtensa/xtensa.md (define_constants): Remove "A11_REG". + (sibcall_internal, sibcall_value_internal): + Change to use the new register constraint, and remove two split + patterns for fixups that are no longer needed. + +2022-08-18 Maciej W. Rozycki <macro@embecosm.com> + + * config/riscv/riscv.md (*mov<GPR:mode><X:mode>cc): Fix output + pattern formatting. + +2022-08-18 Tim Lange <mail@tim-lange.me> + + PR analyzer/106181 + * doc/invoke.texi: Add Wanalyzer-imprecise-fp-arithmetic. + +2022-08-18 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-path.cc (path_range_query::path_range_query): Add + various constructors to take a path. + (path_range_query::~path_range_query): Remove m_alloced_ranger. + (path_range_query::range_on_path_entry): Adjust for m_ranger being + a reference. + (path_range_query::set_path): Rename to... + (path_range_query::reset_path): ...this and call compute_ranges. + (path_range_query::ssa_range_in_phi): Adjust for m_ranger + reference. + (path_range_query::range_defined_in_block): Same. + (path_range_query::compute_ranges_in_block): Same. + (path_range_query::adjust_for_non_null_uses): Same. + (path_range_query::compute_exit_dependencies): Use m_path instead + of argument. + (path_range_query::compute_ranges): Remove path argument. + (path_range_query::range_of_stmt): Adjust for m_ranger reference. + (path_range_query::compute_outgoing_relations): Same. + * gimple-range-path.h (class path_range_query): Add various + constructors. + Make compute_ranges and compute_exit_dependencies private. + Rename set_path to reset_path. + Make m_ranger a reference. + Remove m_alloced_ranger. + * tree-ssa-dom.cc (pass_dominator::execute): Adjust constructor to + path_range_query. + * tree-ssa-loop-ch.cc (entry_loop_condition_is_static): Take a + ranger and instantiate a new path_range_query every time. + (ch_base::copy_headers): Pass ranger instead of path_range_query. + * tree-ssa-threadbackward.cc (class back_threader): Remove m_solver. + (back_threader::~back_threader): Remove m_solver. + (back_threader::find_taken_edge_switch): Adjust for m_ranger + reference. + (back_threader::find_taken_edge_cond): Same. + (back_threader::dump): Remove m_solver. + (back_threader::back_threader): Move verify_marked_backedges + here from the path_range_query constructor. + * tree-ssa-threadedge.cc (hybrid_jt_simplifier::simplify): Move + some code from compute_ranges_from_state here. + (hybrid_jt_simplifier::compute_ranges_from_state): Rename... + (hybrid_jt_simplifier::compute_exit_dependencies): ...to this. + * tree-ssa-threadedge.h (class hybrid_jt_simplifier): Rename + compute_ranges_from_state to compute_exit_dependencies. + Remove m_path. + +2022-08-18 Richard Biener <rguenther@suse.de> + + PR middle-end/106617 + * match.pd ((a ? b : c) > d -> a ? (b > d) : (c > d)): Fix + guard, disable on GENERIC to not cause quadratic behavior + with the fold-const.cc implementation and the use of ! + +2022-08-18 Andrew Pinski <apinski@marvell.com> + + PR gcov-profile/106659 + * gcov-dump.cc (INCLUDE_VECTOR): Include vector.h with + INCLUDE_VECTOR. + +2022-08-18 konglin1 <lingling.kong@intel.com> + + * config/i386/i386-expand.cc (ix86_expand_sse_movcc): Handle vector + BFmode. + (ix86_expand_vector_init_duplicate): Support vector BFmode. + (ix86_expand_vector_init_one_nonzero): Ditto. + (ix86_expand_vector_init_one_var): Ditto. + (ix86_expand_vector_init_concat): Ditto. + (ix86_expand_vector_init_interleave): Ditto. + (ix86_expand_vector_init_general): Ditto. + (ix86_expand_vector_init): Ditto. + (ix86_expand_vector_set_var): Ditto. + (ix86_expand_vector_set): Ditto. + (ix86_expand_vector_extract): Ditto. + * config/i386/i386.cc (classify_argument): Add BF vector modes. + (function_arg_64): Ditto. + (ix86_gimplify_va_arg): Ditto. + (ix86_get_ssemov): Ditto. + * config/i386/i386.h (VALID_AVX256_REG_MODE): Add BF vector modes. + (VALID_AVX512F_REG_MODE): Ditto. + (host_detect_local_cpu): Ditto. + (VALID_SSE2_REG_MODE): Ditto. + * config/i386/i386.md: Add BF vector modes. + (MODE_SIZE): Ditto. + (ssemodesuffix): Add bf suffix for BF vector modes. + (ssevecmode): Ditto. + * config/i386/sse.md (VMOVE): Adjust for BF vector modes. + (VI12HFBF_AVX512VL): Ditto. + (V_256_512): Ditto. + (VF_AVX512HFBF16): Ditto. + (VF_AVX512BWHFBF16): Ditto. + (VIHFBF): Ditto. + (avx512): Ditto. + (VIHFBF_256): Ditto. + (VIHFBF_AVX512BW): Ditto. + (VI2F_256_512):Ditto. + (V8_128):Ditto. + (V16_256): Ditto. + (V32_512): Ditto. + (sseinsnmode): Ditto. + (sseconstm1): Ditto. + (sseintmodesuffix): New mode_attr. + (avx512fmaskmode): Ditto. + (avx512fmaskmodelower): Ditto. + (ssedoublevecmode): Ditto. + (ssehalfvecmode): Ditto. + (ssehalfvecmodelower): Ditto. + (ssescalarmode): Add vector BFmode mapping. + (ssescalarmodelower): Ditto. + (ssexmmmode): Ditto. + (ternlogsuffix): Ditto. + (ssescalarsize): Ditto. + (sseintprefix): Ditto. + (i128): Ditto. + (xtg_mode): Ditto. + (bcstscalarsuff): Ditto. + (<avx512>_blendm<mode>): New define_insn for BFmode. + (<avx512>_store<mode>_mask): Ditto. + (vcond_mask_<mode><avx512fmaskmodelower>): Ditto. + (vec_set<mode>_0): New define_insn for BF vector set. + (V8BFH_128): New mode_iterator for BFmode. + (avx512fp16_mov<mode>): Ditto. + (vec_set<mode>): New define_insn for BF vector set. + (@vec_extract_hi_<mode>): Ditto. + (@vec_extract_lo_<mode>): Ditto. + (vec_set_hi_<mode>): Ditto. + (vec_set_lo_<mode>): Ditto. + (*vec_extract<mode>_0): New define_insn_and_split for BF + vector extract. + (*vec_extract<mode>): New define_insn. + (VEC_EXTRACT_MODE): Add BF vector modes. + (PINSR_MODE): Add V8BF. + (sse2p4_1): Ditto. + (pinsr_evex_isa): Ditto. + (<sse2p4_1>_pinsr<ssemodesuffix>): Adjust to support + insert for V8BFmode. + (pbroadcast_evex_isa): Add BF vector modes. + (AVX2_VEC_DUP_MODE): Ditto. + (VEC_INIT_MODE): Ditto. + (VEC_INIT_HALF_MODE): Ditto. + (avx2_pbroadcast<mode>): Adjust to support BF vector mode + broadcast. + (avx2_pbroadcast<mode>_1): Ditto. + (<avx512>_vec_dup<mode>_1): Ditto. + (<mask_codefor><avx512>_vec_dup_gpr<mode><mask_name>): + Ditto. + +2022-08-18 Martin Liska <mliska@suse.cz> + + * configure: Regenerate. + +2022-08-18 Haochen Gui <guihaoc@gcc.gnu.org> + + PR target/103109 + * config/rs6000/rs6000.md (<u>maddditi4): New pattern for multiply-add. + (<u>madddi4_highpart): New. + (<u>madddi4_highpart_le): New. + +2022-08-18 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-path.cc + (path_range_query::compute_exit_dependencies): Use + gimple_range_ssa_names. + +2022-08-18 zhongjuzhe <juzhe.zhong@rivai.ai> + + * config/riscv/predicates.md: Adjust runtime invariant. + * config/riscv/riscv-modes.def (MAX_BITSIZE_MODE_ANY_MODE): New. + (NUM_POLY_INT_COEFFS): New. + * config/riscv/riscv-protos.h (riscv_initial_elimination_offset):Adjust + runtime invariant. + * config/riscv/riscv-sr.cc (riscv_remove_unneeded_save_restore_calls): + Adjust runtime invariant. + * config/riscv/riscv.cc (struct riscv_frame_info): Adjust runtime + invariant. + (enum riscv_microarchitecture_type): Ditto. + (riscv_valid_offset_p): Ditto. + (riscv_valid_lo_sum_p): Ditto. + (riscv_address_insns): Ditto. + (riscv_load_store_insns): Ditto. + (riscv_legitimize_move): Ditto. + (riscv_binary_cost): Ditto. + (riscv_rtx_costs): Ditto. + (riscv_output_move): Ditto. + (riscv_extend_comparands): Ditto. + (riscv_flatten_aggregate_field): Ditto. + (riscv_get_arg_info): Ditto. + (riscv_pass_by_reference): Ditto. + (riscv_elf_select_rtx_section): Ditto. + (riscv_stack_align): Ditto. + (riscv_compute_frame_info): Ditto. + (riscv_initial_elimination_offset): Ditto. + (riscv_set_return_address): Ditto. + (riscv_for_each_saved_reg): Ditto. + (riscv_first_stack_step): Ditto. + (riscv_expand_prologue): Ditto. + (riscv_expand_epilogue): Ditto. + (riscv_can_use_return_insn): Ditto. + (riscv_secondary_memory_needed): Ditto. + (riscv_hard_regno_nregs): Ditto. + (riscv_convert_vector_bits): New. + (riscv_option_override): Adjust runtime invariant. + (riscv_promote_function_mode): Ditto. + * config/riscv/riscv.h (POLY_SMALL_OPERAND_P): New. + (BITS_PER_RISCV_VECTOR): New. + (BYTES_PER_RISCV_VECTOR): New. + * config/riscv/riscv.md: Adjust runtime invariant. + +2022-08-18 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr): + Get __tls_get_addr address through got table when disable plt. + +2022-08-18 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.cc (xtensa_expand_prologue): + Use an "addmi" machine instruction for updating the stack pointer + rather than addition/subtraction via hard register A9, if the amount + of change satisfies the literal value conditions of that instruction + when the CALL0 ABI is used. + (xtensa_expand_epilogue): Ditto. + And also inhibit the stack pointer addition of constant zero. + +2022-08-17 Roger Sayle <roger@nextmovesoftware.com> + + PR target/106640 + * config/i386/i386-features.cc + (timde_scalar_chain::compute_convert_gain): Replace incorrect use + of XINT with INTVAL (XEXP (src, 1)). + +2022-08-17 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-path.cc + (path_range_query::compute_ranges_in_block): Remove + set_root_oracle call. + (path_range_query::compute_ranges): Pass ranger oracle to + reset_path. + * value-relation.cc (path_oracle::reset_path): Set root oracle. + * value-relation.h (path_oracle::reset_path): Add root oracle + argument. + +2022-08-17 Marek Polacek <polacek@redhat.com> + + PR c++/89780 + * diagnostic-spec.cc (nowarn_spec_t::nowarn_spec_t): Handle + OPT_Wpessimizing_move and OPT_Wredundant_move. + * diagnostic-spec.h (nowarn_spec_t): Add NW_REDUNDANT enumerator. + +2022-08-17 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org> + Jakub Jelinek <jakub@redhat.com> + + PR fortran/46539 + * common.opt (static-libquadmath): New option. + * gcc.cc (driver_handle_option): Always accept -static-libquadmath. + * config/darwin.h (LINK_SPEC): Handle -static-libquadmath. + +2022-08-17 Tobias Burnus <tobias@codesourcery.com> + + * lto-cgraph.cc (input_offload_tables): Improve requires diagnostic + when filenames come out identically. + +2022-08-17 Tobias Burnus <tobias@codesourcery.com> + + PR middle-end/106548 + * omp-low.cc (lower_rec_input_clauses): Use build_outer_var_ref + for 'simd' linear-step values that are variable. + +2022-08-17 Tobias Burnus <tobias@codesourcery.com> + Chung-Lin Tang <cltang@codesourcery.com> + + PR c++/104493 + * gimplify.cc (omp_notice_variable): Call omp_mappable_type + instead of removed langhook. + * omp-general.h (omp_mappable_type): New prototype. + * omp-general.cc (omp_mappable_type): New; moved from ... + * langhooks.cc (lhd_omp_mappable_type): ... here. + * langhooks-def.h (lhd_omp_mappable_type, + LANG_HOOKS_OMP_MAPPABLE_TYPE): Remove. + (LANG_HOOKS_FOR_TYPES_INITIALIZER): Remote the latter. + * langhooks.h (struct lang_hooks_for_types): Remove + omp_mappable_type. + +2022-08-17 Christophe Lyon <christophe.lyon@arm.com> + + * config.gcc (arm): Define with_float to hard if target name ends + with 'hf'. + +2022-08-17 Richard Biener <rguenther@suse.de> + + * tree-ssa-threadbackward.cc + (back_threader_profitability): Split profitable_path_p + into possibly_profitable_path_p and itself, keep state + as new members. + (back_threader::m_profit): Remove. + (back_threader::find_paths): Likewise. + (back_threader::maybe_register_path): Take profitability + instance as parameter. + (back_threader::find_paths_to_names): Likewise. Use + possibly_profitable_path_p and avoid the path range query + when the path is currently too large. + (back_threader::find_paths): Fold into ... + (back_threader::maybe_thread_block): ... this. + (get_gimple_control_stmt): Remove. + (back_threader_profitability::possibly_profitable_path_p): + Split out from profitable_path_p, do early profitability + checks. + (back_threader_profitability::profitable_path_p): Do final + profitability path after the taken edge has been determined. + +2022-08-17 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/loongarch.md (fmax<mode>3): New RTL pattern. + (fmin<mode>3): Likewise. + +2022-08-17 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-fold.cc (gimple_range_ssa_names): New. + * gimple-range-fold.h (gimple_range_ssa_names): New prototype. + * gimple-range-gori.cc (range_def_chain::get_def_chain): Move + code to new routine. + +2022-08-16 Martin Liska <mliska@suse.cz> + + PR target/106637 + * doc/install.texi: Remove link to www.bullfreeware.com + +2022-08-16 Kito Cheng <kito.cheng@sifive.com> + + * common/config/riscv/riscv-common.cc (riscv_implied_info): Add + zfh and zfhmin. + (riscv_ext_version_table): Ditto. + (riscv_ext_flag_table): Ditto. + * config/riscv/riscv-opts.h (MASK_ZFHMIN): New. + (MASK_ZFH): Ditto. + (TARGET_ZFHMIN): Ditto. + (TARGET_ZFH): Ditto. + * config/riscv/riscv.cc (riscv_output_move): Handle HFmode move + for zfh and zfhmin. + (riscv_emit_float_compare): Handle HFmode. + * config/riscv/riscv.md (ANYF): Add HF. + (SOFTF): Add HF. + (load): Ditto. + (store): Ditto. + (truncsfhf2): New. + (truncdfhf2): Ditto. + (extendhfsf2): Ditto. + (extendhfdf2): Ditto. + (*movhf_hardfloat): Ditto. + (*movhf_softfloat): Make sure not ZFHMIN. + * config/riscv/riscv.opt (riscv_zf_subext): New. + +2022-08-16 Kito Cheng <kito.cheng@sifive.com> + + * config/riscv/riscv-builtins.cc: include stringpool.h + (riscv_float16_type_node): New. + (riscv_init_builtin_types): Ditto. + (riscv_init_builtins): Call riscv_init_builtin_types. + * config/riscv/riscv-modes.def (HF): New. + * config/riscv/riscv.cc (riscv_output_move): Handle HFmode. + (riscv_mangle_type): New. + (riscv_scalar_mode_supported_p): Ditto. + (riscv_libgcc_floating_mode_supported_p): Ditto. + (riscv_excess_precision): Ditto. + (riscv_floatn_mode): Ditto. + (riscv_init_libfuncs): Ditto. + (TARGET_MANGLE_TYPE): Ditto. + (TARGET_SCALAR_MODE_SUPPORTED_P): Ditto. + (TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P): Ditto. + (TARGET_INIT_LIBFUNCS): Ditto. + (TARGET_C_EXCESS_PRECISION): Ditto. + (TARGET_FLOATN_MODE): Ditto. + * config/riscv/riscv.md (mode): Add HF. + (softload): Add HF. + (softstore): Ditto. + (fmt): Ditto. + (UNITMODE): Ditto. + (movhf): New. + (*movhf_softfloat): New. + +2022-08-16 Richard Biener <rguenther@suse.de> + + * tree-ssa-threadbackward.cc (back_threader::find_paths_to_names): + Do not walk further if we are leaving the current loop. + +2022-08-16 Sergei Trofimovich <siarheit@google.com> + + PR driver/106624 + * gcc.cc (driver::detect_jobserver): Allocate storage xputenv() + argument using xstrdup(). + +2022-08-16 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-path.cc (path_range_query::import_p): Rename to... + (path_range_query::exit_dependency_p): ...this. + (path_range_query::dump): Rename imports to exit dependencies. + (path_range_query::compute_ranges_in_phis): Same. + (path_range_query::compute_ranges_in_block): Same. + (path_range_query::adjust_for_non_null_uses): Same. + (path_range_query::compute_ranges): Same. + (path_range_query::compute_phi_relations): Same. + (path_range_query::add_to_imports): Rename to... + (path_range_query::add_to_exit_dependencies): ...this. + (path_range_query::compute_imports): Rename to... + (path_range_query::compute_exit_dependencies): ...this. + * gimple-range-path.h (class path_range_query): Rename imports to + exit dependencies. + +2022-08-16 Martin Liska <mliska@suse.cz> + + * value-range-storage.h (class obstack_vrange_allocator): Mark + the class as final. + (class ggc_vrange_allocator): Likewise. + +2022-08-16 Martin Liska <mliska@suse.cz> + + * value-range-equiv.h (class value_range_equiv): Add virtual + destructor. + * value-range.h: Likewise. + +2022-08-16 Richard Biener <rguenther@suse.de> + + PR middle-end/106630 + * match.pd ((T)(x * CST) -> (T)x * CST): Restrict to + narrowing conversions. + +2022-08-16 Martin Liska <mliska@suse.cz> + + * value-range-equiv.h (class value_range_equiv): + +2022-08-16 Martin Liska <mliska@suse.cz> + + * config/i386/i386-features.h (class general_scalar_chain): Add + final override for a method. + (class timode_scalar_chain): Likewise. + +2022-08-16 Richard Biener <rguenther@suse.de> + + * doc/invoke.texi (max-jump-thread-paths): Adjust. + +2022-08-16 Martin Liska <mliska@suse.cz> + + * opts-common.cc (jobserver_info::connect): Open fifo + in non-blocking mode. + +2022-08-16 Kewen.Lin <linkw@gcc.gnu.org> + + PR target/103353 + * config/rs6000/mma.md (define_expand movoo): Move TARGET_MMA condition + check to preparation statements and add handlings for !TARGET_MMA. + (define_expand movxo): Likewise. + +2022-08-16 Kewen Lin <linkw@linux.ibm.com> + + PR tree-optimization/106322 + * tree-vect-stmts.cc (vectorizable_call): Don't allow + vect_emulated_vector_p type for both vectype_in and vectype_out. + +2022-08-16 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * common/config/xtensa/xtensa-common.cc + (xtensa_option_optimization_table): Add OPT_fsplit_wide_types_early + for OPT_LEVELS_ALL in order to restore pre-GCC10 behavior. + +2022-08-15 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/106621 + * value-range.cc (irange::set): Check for POLY_INT_CST early. + +2022-08-15 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/i386-features.cc + (timode_scalar_chain::compute_convert_gain): Provide costs for + shifts and rotates. + (timode_scalar_chain::convert_insn): Handle ASHIFTRT, ROTATERT + and ROTATE just like existing ASHIFT and LSHIFTRT cases. + (timode_scalar_to_vector_candidate_p): Handle all shifts and + rotates by integer constants between 0 and 127. + +2022-08-15 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/i386-features.cc + (timode_scalar_chain::compute_convert_gain): Provide gains for + comparisons against 0/-1, including "*testti" patterns. + +2022-08-15 Roger Sayle <roger@nextmovesoftware.com> + + PR tree-optimization/64992 + PR tree-optimization/98956 + * match.pd (ne (lshift @0 @1) 0): Simplify (X << C) != 0 to X + when X is zero_one_valued_p and the shift constant C is valid. + (eq (lshift @0 @1) 0): Likewise, simplify (X << C) == 0 to !X + when X is zero_one_valued_p and the shift constant C is valid. + +2022-08-15 Roger Sayle <roger@nextmovesoftware.com> + Richard Biener <rguenther@suse.de> + + PR tree-optimization/71343 + * match.pd (op (lshift @0 @1) (lshift @2 @1)): Optimize the + expression (X<<C) + (Y<<C) to (X+Y)<<C for multiple operators. + (op (rshift @0 @1) (rshift @2 @1)): Likewise, simplify (X>>C)^(Y>>C) + to (X^Y)>>C for binary logical operators, AND, IOR and XOR. + +2022-08-15 Richard Biener <rguenther@suse.de> + + * gimple-range-path.cc (range_on_path_entry): Just + call range_on_entry. + +2022-08-15 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/106590 + * ifcvt.cc (check_for_cc_cmp_clobbers): New function. + (noce_convert_multiple_sets_1): If SEQ sets or clobbers any regs + mentioned in cc_cmp or rev_cc_cmp, don't consider seq2 for any + further conditional moves. + +2022-08-15 konglin1 <lingling.kong@intel.com> + + * config/i386/i386-builtin-types.def (BFLOAT16): New primitive type. + * config/i386/i386-builtins.cc : Support __bf16 type for i386 backend. + (ix86_register_bf16_builtin_type): New function. + (ix86_bf16_type_node): New. + (ix86_bf16_ptr_type_node): Ditto. + (ix86_init_builtin_types): Add ix86_register_bf16_builtin_type function call. + * config/i386/i386-modes.def (FLOAT_MODE): Add BFmode. + (ADJUST_FLOAT_FORMAT): Ditto. + * config/i386/i386.cc (classify_argument): Handle BFmode. + (construct_container): Ditto. + (function_value_32): Return __bf16 by %xmm0. + (function_value_64): Return __bf16 by SSE register. + (ix86_output_ssemov): Handle BFmode. + (ix86_legitimate_constant_p): Disable BFmode constant double. + (ix86_secondary_reload): Require gpr as intermediate register + to store __bf16 from sse register when sse4 is not available. + (ix86_scalar_mode_supported_p): Enable __bf16 under sse2. + (ix86_mangle_type): Add manlging for __bf16 type. + (ix86_invalid_conversion): New function for target hook. + (ix86_invalid_unary_op): Ditto. + (ix86_invalid_binary_op): Ditto. + (TARGET_INVALID_CONVERSION): New define for target hook. + (TARGET_INVALID_UNARY_OP): Ditto. + (TARGET_INVALID_BINARY_OP): Ditto. + * config/i386/i386.h (host_detect_local_cpu): Add BFmode. + * config/i386/i386.md ("mode"): Add BFmode. + (MODE_SIZE): Ditto. + (X87MODEFH): Ditto. + (HFBF): Add new define_mode_iterator. + (*pushhf_rex64): Change for BFmode. + (*push<mode>_rex64): Ditto. + (*pushhf): Ditto. + (*push<mode>): Ditto. + (MODESH): Ditto. + (hfbfconstf): Add new define_mode_attr. + (*mov<mode>_internal): Add BFmode. + +2022-08-13 Roger Sayle <roger@nextmovesoftware.com> + Uroš Bizjak <ubizjak@gmail.com> + + * config/i386/predicates.md (const_0_to_255_not_mul_8_operand): + New predicate for values between 0/1 and 255, not multiples of 8. + * config/i386/sse.md (ashlv1ti3): Delay lowering of logical left + shifts by constant bit counts. + (*ashlvti3_internal): New define_insn_and_split that lowers + logical left shifts by constant bit counts, that aren't multiples + of 8, before reload. + (lshrv1ti3): Delay lowering of logical right shifts by constant. + (*lshrv1ti3_internal): New define_insn_and_split that lowers + logical right shifts by constant bit counts, that aren't multiples + of 8, before reload. + (ashrv1ti3):: Delay lowering of arithmetic right shifts by + constant bit counts. + (*ashrv1ti3_internal): New define_insn_and_split that lowers + arithmetic right shifts by constant bit counts before reload. + (rotlv1ti3): Delay lowering of rotate left by constant. + (*rotlv1ti3_internal): New define_insn_and_split that lowers + rotate left by constant bits counts before reload. + (rotrv1ti3): Delay lowering of rotate right by constant. + (*rotrv1ti3_internal): New define_insn_and_split that lowers + rotate right by constant bits counts before reload. + +2022-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com> + + * doc/invoke.texi (Arm Options): Document -mcpu=cortex-m55 options. + +2022-08-12 Jan Hubicka <hubicka@ucw.cz> + + PR middle-end/106057 + * ipa-devirt.cc (type_or_derived_type_possibly_instantiated_p): New + function. + (possible_polymorphic_call_targets): Use it. + +2022-08-12 Andrew Carlotti <andrew.carlotti@arm.com> + + * tree-ssa-loop.h: Improve comment + +2022-08-12 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/106506 + * tree-ssa-phiopt.cc (spaceship_replacement): Don't punt for + is_cast or orig_use_lhs cases if phi_bb has 3 predecessors. + +2022-08-12 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106593 + * tree-ssa-threadbackward.cc (back_threader::find_paths): + If the imports from the conditional do not satisfy + gimple_range_ssa_p don't try to thread anything. + +2022-08-12 Tamar Christina <tamar.christina@arm.com> + + PR target/106524 + * config/aarch64/aarch64-sve.md (*fcmuo<mode>_nor_combine, + *fcmuo<mode>_bic_combine): Don't accept comparisons against zero. + +2022-08-12 Tim Lange <mail@tim-lange.me> + + PR analyzer/106000 + * doc/invoke.texi: Add Wanalyzer-out-of-bounds. + +2022-08-12 Andrew Pinski <apinski@marvell.com> + + * config/aarch64/aarch64.md: Remove comment + about MD_INCLUDES as it is out of date and not needed. + +2022-08-11 Richard Biener <rguenther@suse.de> + + * gimple-range-path.cc (path_range_query::compute_imports): + Restrict walking SSA defs to blocks inside the path. Track + the same operands as range_def_chain::get_def_chain does. + +2022-08-11 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106514 + * tree-ssa-threadbackward.cc (back_threader::find_paths_to_names): + Compute and unwind both m_imports and interesting on the fly during + path discovery. + (back_threader::find_paths): Compute the original m_imports + from just the SSA uses of the exit conditional. Drop + handling single_succ_to_potentially_threadable_block. + * gimple-range-path.cc (path_range_query::ssa_range_in_phi): Handle + constant PHI arguments without crashing. Use PHI_ARG_DEF_FROM_EDGE. + +2022-08-11 Richard Biener <rguenther@suse.de> + + * gimple-range-path.h (path_range_query::compute_imports): + Take path as argument, not the exit block. + * gimple-range-path.cc (path_range_query::compute_imports): + Likewise, and adjust, avoiding possibly stale m_path. + (path_range_query::compute_outgoing_relations): Register + relations for all conditionals. + * tree-ssa-threadbackward.cc (back_threader::find_paths): + Adjust. + +2022-08-11 Kewen Lin <linkw@linux.ibm.com> + + * config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Fix the + oversight on ENB_CELL by simplifying with rs6000_builtin_is_supported. + (rs6000_expand_builtin): Simplify with rs6000_builtin_is_supported. + +2022-08-11 Kewen Lin <linkw@linux.ibm.com> + + * config/rs6000/rs6000-internal.h (rs6000_global_entry_point_needed_p): + Remove function declaration. + +2022-08-10 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106513 + * gimple-ssa-store-merging.cc (do_shift_rotate): Use uint64_t + for head_marker. + +2022-08-10 Martin Liska <mliska@suse.cz> + + PR lto/106328 + * opts-jobserver.h (struct jobserver_info): Add pipefd. + (jobserver_info::connect): New. + (jobserver_info::disconnect): Likewise. + (jobserver_info::get_token): Likewise. + (jobserver_info::return_token): Likewise. + * opts-common.cc: Implement the new functions. + +2022-08-10 Martin Liska <mliska@suse.cz> + + * opts-jobserver.h: Add one member. + * opts-common.cc (jobserver_info::jobserver_info): Parse FIFO + format of --jobserver-auth. + +2022-08-10 Martin Liska <mliska@suse.cz> + + * gcc.cc (driver::detect_jobserver): Remove and move to + jobserver.h. + * lto-wrapper.cc (jobserver_active_p): Likewise. + (run_gcc): Likewise. + * opts-jobserver.h: New file. + * opts-common.cc (jobserver_info::jobserver_info): New function. + +2022-08-09 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/i386-features.cc (scalar_chain::convert_compare): + Create new pseudos only when/if needed. Add support for TEST, + i.e. (COMPARE (AND x y) (const_int 0)), using UNSPEC_PTEST. + When broadcasting V2DImode and V4SImode use new pseudo register. + (timode_scalar_chain::convert_op): Do nothing if operand is + already V1TImode. Avoid generating useless SUBREG conversions, + i.e. (SUBREG:V1TImode (REG:V1TImode) 0). Handle CONST_WIDE_INT + in addition to CONST_INT by using CONST_SCALAR_INT_P. + (convertible_comparison_p): Use CONST_SCALAR_INT_P to match both + CONST_WIDE_INT and CONST_INT. Recognize new *testti_doubleword + pattern as an STV candidate. + (timode_scalar_to_vector_candidate_p): Allow CONST_SCALAR_INT_P + operands in binary logic operations. + * config/i386/i386.cc (ix86_rtx_costs) <case UNSPEC>: Add costs + for UNSPEC_PTEST; a PTEST that performs an AND has the same cost + as regular PTEST, i.e. cost->sse_op. + * config/i386/i386.md (*testti_doubleword): New pre-reload + define_insn_and_split that recognizes comparison of TI mode AND + against zero. + * config/i386/sse.md (*ptest<mode>_and): New pre-reload + define_insn_and_split that recognizes UNSPEC_PTEST of identical + AND operands. + +2022-08-09 Roger Sayle <roger@nextmovesoftware.com> + Richard Biener <rguenther@suse.de> + + PR middle-end/21137 + PR tree-optimization/98954 + * fold-const.cc (fold_binary_loc): Remove optimizations to + optimize ((X >> C1) & C2) ==/!= 0. + * match.pd (cmp (bit_and (lshift @0 @1) @2) @3): Remove wi::ctz + check, and handle all values of INTEGER_CSTs @2 and @3. + (cmp (bit_and (rshift @0 @1) @2) @3): Likewise, remove wi::clz + checks, and handle all values of INTEGER_CSTs @2 and @3. + +2022-08-09 David Malcolm <dmalcolm@redhat.com> + + * doc/invoke.texi (Static Analyzer Options): Add notes on which + functions the analyzer has hardcoded knowledge of. + +2022-08-09 Andrew Stubbs <ams@codesourcery.com> + + * config/gcn/gcn.cc (gcn_function_value): Allow vector return values. + (num_arg_regs): Allow vector arguments. + (gcn_function_arg): Likewise. + (gcn_function_arg_advance): Likewise. + (gcn_arg_partial_bytes): Likewise. + (gcn_return_in_memory): Likewise. + (gcn_expand_epilogue): Get return value from v8. + * config/gcn/gcn.h (RETURN_VALUE_REG): Set to v8. + (FIRST_PARM_REG): USE FIRST_SGPR_REG for clarity. + (FIRST_VPARM_REG): New. + (FUNCTION_ARG_REGNO_P): Allow vector parameters. + (struct gcn_args): Add vnum field. + (LIBCALL_VALUE): All vector return values. + * config/gcn/gcn.md (gcn_call_value): Add vector constraints. + (gcn_call_value_indirect): Likewise. + +2022-08-09 Richard Biener <rguenther@suse.de> + + * omp-expand.cc (expand_omp_atomic_load): Emit GIMPLE + directly. Avoid update_ssa when in SSA form. + (expand_omp_atomic_store): Likewise. + (expand_omp_atomic_fetch_op): Avoid update_ssa when in SSA + form. + (expand_omp_atomic_pipeline): Likewise. + (expand_omp_atomic_mutex): Likewise. + * tree-parloops.cc (gen_parallel_loop): Use + TODO_update_ssa_no_phi after loop_version. + +2022-08-09 Richard Biener <rguenther@suse.de> + + * doc/invoke.texi (max-fsm-thread-length): Remove. + * params.opt (max-fsm-thread-length): Likewise. + * tree-ssa-threadbackward.cc + (back_threader_profitability::profitable_path_p): Do not + check max-fsm-thread-length. + +2022-08-09 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106514 + * params.opt (max-jump-thread-paths): New. + * doc/invoke.texi (max-jump-thread-paths): Document. + * tree-ssa-threadbackward.cc (back_threader::find_paths_to_names): + Honor max-jump-thread-paths, take overall_path argument. + (back_threader::find_paths): Pass 1 as initial overall_path. + +2022-08-09 Tobias Burnus <tobias@codesourcery.com> + + PR middle-end/106492 + * omp-low.cc (lower_rec_input_clauses): Add missing folding + to data type of linear-clause list item. + +2022-08-08 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/106556 + * gimple-range-gori.cc (gori_compute::condexpr_adjust): Use the + type of the cond_expr operands being evaluted. + +2022-08-08 Tom Honermann <tom@honermann.net> + + * ginclude/stdatomic.h (atomic_char8_t, + ATOMIC_CHAR8_T_LOCK_FREE): New typedef and macro. + +2022-08-08 Andrew Pinski <apinski@marvell.com> + + PR middle-end/103645 + * gimplify.cc (gimplify_init_constructor): Don't build/add + gimple assignment of an empty type. + +2022-08-08 Richard Biener <rguenther@suse.de> + + PR lto/106540 + PR lto/106334 + * dwarf2out.cc (dwarf2out_register_external_die): Restore + original assert. + * lto-streamer-in.cc (lto_read_tree_1): Use lto_input_tree_1 + to input DECL_INITIAL, avoiding to commit drefs. + +2022-08-07 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/i386.md (*cmp<dwi>_doubleword): Change predicate + for x86_64_hilo_general_operand to general operand. Call + force_reg on parts that are not x86_64_immediate_operand. + +2022-08-05 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/105947 + * doc/invoke.texi: Add -Wanalyzer-jump-through-null. + +2022-08-05 Roger Sayle <roger@nextmovesoftware.com> + + * expmed.cc (emit_store_flag_1): Move code to expand double word + equality and inequality against zero or -1, using word operations, + to after trying to use the backend's cstore<mode>4 optab/expander. + +2022-08-05 Tamar Christina <tamar.christina@arm.com> + + PR middle-end/106534 + * tree-ssa-phiopt.cc (tree_ssa_phiopt_worker): Guard the + value_replacement and store_elim from diamonds. + +2022-08-05 Richard Biener <rguenther@suse.de> + + * tree-ssa-threadbackward.cc (back_threader::maybe_register_path): + Check whether the registry register_path rejected the path. + (back_threader_registry::register_path): Return whether + register_jump_thread succeeded. + +2022-08-05 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/106514 + * value-range.cc (unsupported_range::unsupported_range): Move... + * value-range.h (unsupported_range::unsupported_range): ...here. + (unsupported_range::set_undefined): New. + +2022-08-05 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106533 + * tree-loop-distribution.cc (loop_distribution::execute): Continue + analyzing the inner loops when find_seed_stmts_for_distribution + fails. + +2022-08-05 Andrew Pinski <apinski@marvell.com> + + * config/riscv/predicates.md (splittable_const_int_operand): + Remove the check for TARGET_64BIT for single bit const values. + +2022-08-04 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/106514 + * gimple-range-path.cc (path_range_query::compute_ranges_in_block): + Use EXECUTE_IF_AND_IN_BITMAP to loop over 2 bitmaps. + +2022-08-04 Tamar Christina <tamar.christina@arm.com> + + * match.pd: New bit_not rule. + +2022-08-04 Tamar Christina <tamar.christina@arm.com> + + PR middle-end/106519 + * tree-ssa-phiopt.cc (tree_ssa_phiopt_worker): Check final phi edge for + diamond shapes. + +2022-08-04 Sam Feifer <sfeifer@redhat.com> + + PR tree-optimization/106243 + * match.pd (-x & 1): New simplification. + +2022-08-04 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106521 + * gimple-loop-jam.cc (tree_loop_unroll_and_jam): Perform + CFG cleanup manually before rewriting into LC SSA. + +2022-08-04 Richard Biener <rguenther@suse.de> + + * tree-ssa-threadbackward.cc (populate_worklist): Remove. + (back_threader::resolve_phi): Likewise. + (back_threader::find_paths_to_names): Rewrite greedy search. + +2022-08-04 Ilya Leoshkevich <iii@linux.ibm.com> + + * config/s390/vector.md (V_HW_FT): New iterator. + * config/s390/vx-builtins.md (vsel<mode>): Use V_HW_FT instead + of V_HW. + +2022-08-03 Michael Meissner <meissner@linux.ibm.com> + + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove code + setting -mblock-ops-vector-pair. + +2022-08-03 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/106514 + * value-relation.cc (path_oracle::killing_def) Do not walk the + equivalence set clearing bits. + +2022-08-03 Tamar Christina <tamar.christina@arm.com> + + * tree-ssa-phiopt.cc (minmax_replacement): Optionally search for the phi + sequence of a three-way conditional. + (replace_phi_edge_with_variable): Support diamonds. + (tree_ssa_phiopt_worker): Detect diamond phi structure for three-way + min/max. + (strip_bit_not, invert_minmax_code): New. + +2022-08-03 Richard Earnshaw <rearnsha@arm.com> + + PR rtl-optimization/106187 + * alias.h (mems_same_for_tbaa_p): Declare. + * alias.cc (mems_same_for_tbaa_p): New function. + * dse.cc (record_store): Use it instead of open-coding + alias check. + * cselib.h (cselib_redundant_set_p): Declare. + * cselib.cc: Include alias.h + (cselib_redundant_set_p): New function. + * cfgcleanup.cc: (mark_effect): Use cselib_redundant_set_p instead + of rtx_equal_for_cselib_p. + * postreload.cc (reload_cse_simplify): Use cselib_redundant_set_p. + (reload_cse_noop_set_p): Delete. + +2022-08-03 Martin Liska <mliska@suse.cz> + + * doc/gcov-dump.texi: Document the new option. + * gcov-dump.cc (main): Parse the new option. + (print_usage): Show the option. + (tag_counters): Sort key:value pairs of TOP N counter. + +2022-08-03 Martin Liska <mliska@suse.cz> + + * profile.cc (compute_branch_probabilities): Do not collect + stats unless TDF_DETAILS. + +2022-08-03 Roger Sayle <roger@nextmovesoftware.com> + Uroš Bizjak <ubizjak@gmail.com> + + PR target/47949 + * config/i386/i386.md (peephole2): New peephole2 to convert + SWI48 moves to/from %rax/%eax where the src is dead to xchg, + when optimizing for minimal size with -Oz. + +2022-08-03 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/i386.md (*cmp<dwi>_doubleword): Add a special case + to split comparisons against -1 using AND and CMP -1 instructions. + +2022-08-03 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/i386-features.cc (compute_convert_gain): Add gain + for converting suitable TImode shift to a V1TImode shift. + (timode_scalar_chain::convert_insn): Add support for converting + suitable ASHIFT and LSHIFTRT. + (timode_scalar_to_vector_candidate_p): Consider logical shifts + by integer constants that are multiples of 8 to be candidates. + +2022-08-03 Roger Sayle <roger@nextmovesoftware.com> + Segher Boessenkool <segher@kernel.crashing.org> + Richard Sandiford <richard.sandiford@arm.com> + + * simplify-rtx.cc (simplify_unary_operation_1) <ABS>: Add + optimizations for CLRSB, PARITY, POPCOUNT, SS_ABS and LSHIFTRT + that are all positive to complement the existing FFS and + idempotent ABS simplifications. + <SIGN_EXTEND>: Canonicalize SIGN_EXTEND to ZERO_EXTEND when + val_signbit_known_clear_p is true of the operand. + Simplify sign extensions of SUBREG truncations of operands + that are already suitably (zero) extended. + <ZERO_EXTEND>: Simplify zero extensions of SUBREG truncations + of operands that are already suitably zero extended. + +2022-08-02 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/106510 + * gimple-range-fold.cc (fur_source::register_outgoing_edges): + Check for unsupported statements early. + +2022-08-02 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/106474 + * gimple-range-cache.cc (ranger_cache::fill_block_cache): Query + range of equivalences that may contribute to the range. + +2022-08-02 Jose E. Marchesi <jose.marchesi@oracle.com> + + * btfout.cc (output_asm_btf_vlen_bytes): Do not use the CHAR + encoding bit in BTF. + +2022-08-02 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-fold.cc (fold_using_range::range_of_phi): Remove + irange check. + (tree_lower_bound): New. + (tree_upper_bound): New. + (fold_using_range::range_of_ssa_name_with_loop_info): Convert to + vrange. + * gimple-range-fold.h (range_of_ssa_name_with_loop_info): Change + argument to vrange. + +2022-08-02 Richard Biener <rguenther@suse.de> + + * tree-ssa-threadbackward.cc + (back_threader_profitability::profitable_path_p): Apply + size constraints to all paths again. + +2022-08-02 Aldy Hernandez <aldyh@redhat.com> + + * range-op-float.cc (finite_operands_p): New. + (frelop_early_resolve): New. + (default_frelop_fold_range): New. + (class foperator_equal): New. + (class foperator_not_equal): New. + (class foperator_lt): New. + (class foperator_le): New. + (class foperator_gt): New. + (class foperator_ge): New. + (class foperator_unordered): New. + (class foperator_ordered): New. + (class foperator_relop_unknown): New. + (floating_op_table::floating_op_table): Add above classes to + floating op table. + * value-range.h (frange::supports_p): Enable. + +2022-08-02 Aldy Hernandez <aldyh@redhat.com> + + * tree-core.h (struct tree_ssa_name): Add frange_info and + reshuffle the rest. + * value-range-storage.cc (vrange_storage::alloc_slot): Add case + for frange. + (vrange_storage::set_vrange): Same. + (vrange_storage::get_vrange): Same. + (vrange_storage::fits_p): Same. + (frange_storage_slot::alloc_slot): New. + (frange_storage_slot::set_frange): New. + (frange_storage_slot::get_frange): New. + (frange_storage_slot::fits_p): New. + * value-range-storage.h (class frange_storage_slot): New. + +2022-08-02 Aldy Hernandez <aldyh@redhat.com> + + * ipa-prop.cc (ipa_compute_jump_functions_for_edge): Limit ranger + query to integrals. + +2022-08-02 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (frange::set): Initialize m_props and cleanup. + +2022-08-02 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106497 + * tree-ssa-threadupdate.cc (fwd_jt_path_registry::update_cfg): + Also verify we can copy EDGE_COPY_SRC_JOINER_BLOCK. + +2022-08-02 Martin Liska <mliska@suse.cz> + + * profile.cc (compute_branch_probabilities): Dump details only + if TDF_DETAILS. + * symtab.cc (symtab_node::dump_base): Do not dump pointer unless + TDF_ADDRESS is used, it makes comparison harder. + +2022-08-02 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106498 + * omp-expand.cc (expand_omp_taskreg): Do not perform virtual + SSA update here. + (expand_omp_for): Or here. + (execute_expand_omp): Instead schedule it here together + with CFG cleanup via TODO. + +2022-08-02 Richard Biener <rguenther@suse.de> + + PR lto/106334 + * dwarf2out.cc (dwarf2out_register_external_die): Adjust + assert. + +2022-08-02 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106495 + * tree-ssa-threadbackward.cc + (back_threader_profitability::profitable_path_p): If known_edge + is probably never executed avoid threading. + +2022-08-01 David Malcolm <dmalcolm@redhat.com> + + * doc/invoke.texi (-Wanalyzer-putenv-of-auto-var): Fix copy&paste + error. + +2022-08-01 Roger Sayle <roger@nextmovesoftware.com> + Uroš Bizjak <ubizjak@gmail.com> + + PR target/106481 + * config/i386/i386-features.cc (timode_scalar_chain::convert_insn): + Convert a CONST_SCALAR_INT_P in a REG_EQUAL note into a V1TImode + CONST_VECTOR. + +2022-08-01 H.J. Lu <hjl.tools@gmail.com> + + PR target/83782 + * config/i386/i386.cc (ix86_ifunc_ref_local_ok): New. + (TARGET_IFUNC_REF_LOCAL_OK): Use it. + +2022-08-01 Jose E. Marchesi <jose.marchesi@oracle.com> + + PR debug/106263 + * ctfc.h (struct ctf_dtdef): Add field linkage. + * ctfc.cc (ctf_add_function): Set ctti_linkage. + * dwarf2ctf.cc (gen_ctf_function_type): Pass a linkage for + function types and subprograms. + * btfout.cc (btf_asm_func_type): Emit linkage information for the + function. + (btf_dtd_emit_preprocess_cb): Propagate the linkage information + for functions. + +2022-08-01 Andrew Stubbs <ams@codesourcery.com> + Jakub Jelinek <jakub@redhat.com> + + * omp-simd-clone.cc (simd_clone_adjust): Convert shift_cnt to match + the mask type. + +2022-08-01 Sam Feifer <sfeifer@redhat.com> + + PR tree-optimization/104992 + * match.pd (x / y * y == x): New simplification. + +2022-08-01 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (tree_compare): New. + (frange::set): Make more general. + (frange::normalize_kind): Cleanup and return bool. + (frange::union_): Use normalize_kind return value. + (frange::intersect): Same. + (frange::verify_range): Remove unnecessary else. + * value-range.h (vrp_val_max): Move before frange class. + (vrp_val_min): Same. + (frange::frange): Remove set to m_type. + +2022-08-01 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (vrange::supports_type_p): Use const_tree. + (irange::supports_type_p): Same. + (frange::supports_type_p): Same. + * value-range.h (Value_Range::supports_type_p): Same. + (irange::supports_p): Same. + +2022-08-01 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-fold.cc (fold_using_range::range_of_phi): Only + query SCEV for integers. + (fold_using_range::range_of_ssa_name_with_loop_info): Remove + irange check. + +2022-07-31 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/i386.md (define_expand <any_rotate>ti3): For + rotations by 64 bits use new rot[lr]64ti2_doubleword pattern. + (rot[lr]64ti2_doubleword): New post-reload splitter. + +2022-07-31 Roger Sayle <roger@nextmovesoftware.com> + H.J. Lu <hjl.tools@gmail.com> + + PR target/106450 + * config/i386/i386-features.cc (timode_check_non_convertible_regs): + Do nothing if REGNO is set in the REGS bitmap, or is a hard reg. + (timode_remove_non_convertible_regs): Update comment. + Call timode_check_non_convertible_reg on all TImode register + DEFs and USEs in each instruction. + +2022-07-30 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md: Change hard register number used in + the split patterns for indirect sibling call fixups from 10 to 11, + the last free one for the CALL0 ABI. + +2022-07-30 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.cc (xtensa_rtx_costs): + Add new case for IF_THEN_ELSE. + +2022-07-29 Andrew Stubbs <ams@codesourcery.com> + + * config/gcn/gcn-valu.md (V_INT_noHI): New iterator. + (<expander><mode>3<exec>): Use V_INT_noHI. + (v<expander><mode>3<exec>): Likewise. + +2022-07-29 Andrew Stubbs <ams@codesourcery.com> + + * config/gcn/gcn.md (one_cmpldi2): New. + +2022-07-29 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105679 + * tree-ssa-threadbackward.cc + (back_threader_profitability::profitable_path_p): Avoid threading + when the entry edge is probably never executed. + +2022-07-29 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106422 + * tree-ssa-threadupdate.cc (fwd_jt_path_registry::update_cfg): + Check whether we can copy thread blocks and cancel the thread if not. + +2022-07-29 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/106449 + * omp-expand.cc (expand_omp_simd): Fix up handling of pointer + iterators in non-rectangular simd loops. Unshare fd->loops[i].n2 + or n2 before regimplifying it inside of a condition. + +2022-07-29 Jakub Jelinek <jakub@redhat.com> + + * omp-expand.cc (expand_omp_for_init_counts, expand_omp_for_init_vars, + extract_omp_for_update_vars, expand_omp_for_ordered_loops, + expand_omp_simd): Don't fold_convert second argument to + fold_build_pointer_plus to sizetype. + +2022-07-29 Lulu Cheng <chenglulu@loongson.cn> + + * config.in: Regenerate. + * config/loongarch/loongarch.h (ASM_PREFERRED_EH_DATA_FORMAT): + Select the value of the macro definition according to whether + HAVE_AS_EH_FRAME_PCREL_ENCODING_SUPPORT is defined. + * configure: Regenerate. + * configure.ac: Reinstate HAVE_AS_EH_FRAME_PCREL_ENCODING_SUPPORT test. + +2022-07-29 Richard Biener <rguenther@suse.de> + + * gimple-ssa-warn-restrict.cc (builtin_memref::set_base_and_offset): + Use CONVERT_EXPR_CODE_P. + +2022-07-29 Richard Biener <rguenther@suse.de> + + * tree-vect-patterns.cc (vect_recog_bool_pattern): Use + get_vectype_for_scalar_type instead of + vect_get_vector_types_for_stmt. + +2022-07-28 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/105893 + * doc/invoke.texi: Add -Wanalyzer-putenv-of-auto-var. + +2022-07-28 David Malcolm <dmalcolm@redhat.com> + + * doc/invoke.texi (-fdiagnostics-show-cwe): Use uref rather than + url. + (Static Analyzer Options): Likewise. Add urefs for all of the + warnings that have associated CWE identifiers. + +2022-07-28 Maciej W. Rozycki <macro@embecosm.com> + + * doc/implement-c.texi (Floating point implementation): Mention + `-fno-trapping-math' in the context of FENV_ACCESS pragma. + * doc/invoke.texi (Optimize Options): Clarify FENV_ACCESS pragma + implication in the descriptions of `-fno-trapping-math' and + `-frounding-math'. + +2022-07-28 Maciej W. Rozycki <macro@embecosm.com> + + * config/riscv/riscv.md (UNSPECV_FSNVSNAN): New constant. + (QUIET_PATTERN): New int attribute. + (f<quiet_pattern>_quiet<ANYF:mode><X:mode>4): Emit the intended + RTL insns entirely within the preparation statements. + (*f<quiet_pattern>_quiet<ANYF:mode><X:mode>4_default) + (*f<quiet_pattern>_quiet<ANYF:mode><X:mode>4_snan): Remove + insns. + (*riscv_fsnvsnan<mode>2): New insn. + +2022-07-28 Richard Biener <rguenther@suse.de> + + PR middle-end/106457 + * tree.cc (array_at_struct_end_p): Handle array objects + specially. + +2022-07-28 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/106099 + * internal-fn.def (TRAP): New internal fn. + * internal-fn.h (expand_TRAP): Declare. + * internal-fn.cc (expand_TRAP): Define. + * gimple.cc (gimple_build_builtin_unreachable): For BUILT_IN_TRAP, + use internal fn rather than builtin. + +2022-07-27 Andrew Carlotti <andrew.carlotti@arm.com> + + * doc/loop.texi: Refer to LOOPS_HAVE_RECORDED_EXITS instead. + +2022-07-27 WANG Xuerui <i@xen0n.name> + + * doc/invoke.texi: Document -m[no-]explicit-relocs for + LoongArch. + +2022-07-27 Maciej W. Rozycki <macro@embecosm.com> + + * config/riscv/riscv.md (stack_protect_set_<mode>): Remove + duplicate backslashes. + +2022-07-27 Maciej W. Rozycki <macro@embecosm.com> + + * config/riscv/riscv.cc (riscv_rtx_costs) <IF_THEN_ELSE>: New + case. + +2022-07-27 Jakub Jelinek <jakub@redhat.com> + + PR debug/106261 + * cgraphunit.cc (cgraph_node::assemble_thunks_and_aliases): Don't + output asm thunks for -dx. + +2022-07-27 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/106332 + * opts-common.cc (candidates_list_and_hint): Add gcc_assert + that candidates is not an empty vector. + +2022-07-27 Xi Ruoyao <xry111@xry111.site> + + * configure.ac (HAVE_AS_EXPLICIT_RELOCS): Define to 1 if the + assembler supports explicit relocation for LoongArch. + * configure: Regenerate. + * config/loongarch/loongarch-opts.h (HAVE_AS_EXPLICIT_RELOCS): + Define to 0 if not defined. + * config/loongarch/genopts/loongarch.opt.in + (TARGET_EXPLICIT_RELOCS): Default to HAVE_AS_EXPLICIT_RELOCS. + * config/loongarch/loongarch.opt: Regenerate. + +2022-07-26 Peter Bergner <bergner@linux.ibm.com> + + PR c/106016 + * expr.cc (count_type_elements): Handle OPAQUE_TYPE. + +2022-07-26 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/loongarch-opts.cc: Modify the output message string + of the warning. + +2022-07-26 Martin Liska <mliska@suse.cz> + + * doc/tm.texi.in: Fix placement of defmac. + * doc/tm.texi: Copy. + +2022-07-26 Martin Liska <mliska@suse.cz> + + * doc/tm.texi.in: Fix cross @defmac and @hook. + * doc/tm.texi: Copy. + +2022-07-26 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/106444 + * value-range-pretty-print.cc (vrange_printer::visit): Handle + legacy ranges. + (vrange_printer::print_irange_bound): Work on wide_int's. + * value-range-pretty-print.h (print_irange_bound): Same. + * value-range.cc (irange::get_nonzero_bits): Handle legacy ranges. + +2022-07-26 Richard Biener <rguenther@suse.de> + + * tree-ssa-alias.cc (ptr_derefs_may_alias_p): If ptr1 + points to a constant continue checking ptr2. + +2022-07-26 Andrew Carlotti <Andrew.Carlotti@arm.com> + + * config/aarch64/aarch64-builtins.cc + (MODE_d_bf16, MODE_d_f16, MODE_d_f32, MODE_d_f64, MODE_d_s8) + (MODE_d_s16, MODE_d_s32, MODE_d_s64, MODE_d_u8, MODE_d_u16) + (MODE_d_u32, MODE_d_u64, MODE_d_p8, MODE_d_p16, MODE_d_p64) + (MODE_q_bf16, MODE_q_f16, MODE_q_f32, MODE_q_f64, MODE_q_s8) + (MODE_q_s16, MODE_q_s32, MODE_q_s64, MODE_q_u8, MODE_q_u16) + (MODE_q_u32, MODE_q_u64, MODE_q_p8, MODE_q_p16, MODE_q_p64) + (MODE_q_p128): Define macro to map to corresponding mode name. + (QUAL_bf16, QUAL_f16, QUAL_f32, QUAL_f64, QUAL_s8, QUAL_s16) + (QUAL_s32, QUAL_s64, QUAL_u8, QUAL_u16, QUAL_u32, QUAL_u64) + (QUAL_p8, QUAL_p16, QUAL_p64, QUAL_p128): Define macro to map to + corresponding qualifier name. + (LENGTH_d, LENGTH_q): Define macro to map to "" or "q" suffix. + (SIMD_INTR_MODE, SIMD_INTR_QUAL, SIMD_INTR_LENGTH_CHAR): Macro + functions for the above mappings + (VREINTERPRET_BUILTIN2, VREINTERPRET_BUILTINS1, VREINTERPRET_BUILTINS) + (VREINTERPRETQ_BUILTIN2, VREINTERPRETQ_BUILTINS1) + (VREINTERPRETQ_BUILTINS, VREINTERPRET_BUILTIN) + (AARCH64_SIMD_VREINTERPRET_BUILTINS): New macros to create definitions + for all vreinterpret intrinsics + (enum aarch64_builtins): Add vreinterpret function codes + (aarch64_init_simd_intrinsics): New + (handle_arm_neon_h): Improved comment. + (aarch64_general_fold_builtin): Fold vreinterpret calls + * config/aarch64/arm_neon.h + (vreinterpret_p8_f16, vreinterpret_p8_f64, vreinterpret_p8_s8) + (vreinterpret_p8_s16, vreinterpret_p8_s32, vreinterpret_p8_s64) + (vreinterpret_p8_f32, vreinterpret_p8_u8, vreinterpret_p8_u16) + (vreinterpret_p8_u32, vreinterpret_p8_u64, vreinterpret_p8_p16) + (vreinterpret_p8_p64, vreinterpretq_p8_f64, vreinterpretq_p8_s8) + (vreinterpretq_p8_s16, vreinterpretq_p8_s32, vreinterpretq_p8_s64) + (vreinterpretq_p8_f16, vreinterpretq_p8_f32, vreinterpretq_p8_u8) + (vreinterpretq_p8_u16, vreinterpretq_p8_u32, vreinterpretq_p8_u64) + (vreinterpretq_p8_p16, vreinterpretq_p8_p64, vreinterpretq_p8_p128) + (vreinterpret_p16_f16, vreinterpret_p16_f64, vreinterpret_p16_s8) + (vreinterpret_p16_s16, vreinterpret_p16_s32, vreinterpret_p16_s64) + (vreinterpret_p16_f32, vreinterpret_p16_u8, vreinterpret_p16_u16) + (vreinterpret_p16_u32, vreinterpret_p16_u64, vreinterpret_p16_p8) + (vreinterpret_p16_p64, vreinterpretq_p16_f64, vreinterpretq_p16_s8) + (vreinterpretq_p16_s16, vreinterpretq_p16_s32, vreinterpretq_p16_s64) + (vreinterpretq_p16_f16, vreinterpretq_p16_f32, vreinterpretq_p16_u8) + (vreinterpretq_p16_u16, vreinterpretq_p16_u32, vreinterpretq_p16_u64) + (vreinterpretq_p16_p8, vreinterpretq_p16_p64, vreinterpretq_p16_p128) + (vreinterpret_p64_f16, vreinterpret_p64_f64, vreinterpret_p64_s8) + (vreinterpret_p64_s16, vreinterpret_p64_s32, vreinterpret_p64_s64) + (vreinterpret_p64_f32, vreinterpret_p64_u8, vreinterpret_p64_u16) + (vreinterpret_p64_u32, vreinterpret_p64_u64, vreinterpret_p64_p8) + (vreinterpret_p64_p16, vreinterpretq_p64_f64, vreinterpretq_p64_s8) + (vreinterpretq_p64_s16, vreinterpretq_p64_s32, vreinterpretq_p64_s64) + (vreinterpretq_p64_f16, vreinterpretq_p64_f32, vreinterpretq_p64_p128) + (vreinterpretq_p64_u8, vreinterpretq_p64_u16, vreinterpretq_p64_p16) + (vreinterpretq_p64_u32, vreinterpretq_p64_u64, vreinterpretq_p64_p8) + (vreinterpretq_p128_p8, vreinterpretq_p128_p16, vreinterpretq_p128_f16) + (vreinterpretq_p128_f32, vreinterpretq_p128_p64, vreinterpretq_p128_s64) + (vreinterpretq_p128_u64, vreinterpretq_p128_s8, vreinterpretq_p128_s16) + (vreinterpretq_p128_s32, vreinterpretq_p128_u8, vreinterpretq_p128_u16) + (vreinterpretq_p128_u32, vreinterpret_f16_f64, vreinterpret_f16_s8) + (vreinterpret_f16_s16, vreinterpret_f16_s32, vreinterpret_f16_s64) + (vreinterpret_f16_f32, vreinterpret_f16_u8, vreinterpret_f16_u16) + (vreinterpret_f16_u32, vreinterpret_f16_u64, vreinterpret_f16_p8) + (vreinterpret_f16_p16, vreinterpret_f16_p64, vreinterpretq_f16_f64) + (vreinterpretq_f16_s8, vreinterpretq_f16_s16, vreinterpretq_f16_s32) + (vreinterpretq_f16_s64, vreinterpretq_f16_f32, vreinterpretq_f16_u8) + (vreinterpretq_f16_u16, vreinterpretq_f16_u32, vreinterpretq_f16_u64) + (vreinterpretq_f16_p8, vreinterpretq_f16_p128, vreinterpretq_f16_p16) + (vreinterpretq_f16_p64, vreinterpret_f32_f16, vreinterpret_f32_f64) + (vreinterpret_f32_s8, vreinterpret_f32_s16, vreinterpret_f32_s32) + (vreinterpret_f32_s64, vreinterpret_f32_u8, vreinterpret_f32_u16) + (vreinterpret_f32_u32, vreinterpret_f32_u64, vreinterpret_f32_p8) + (vreinterpret_f32_p16, vreinterpret_f32_p64, vreinterpretq_f32_f16) + (vreinterpretq_f32_f64, vreinterpretq_f32_s8, vreinterpretq_f32_s16) + (vreinterpretq_f32_s32, vreinterpretq_f32_s64, vreinterpretq_f32_u8) + (vreinterpretq_f32_u16, vreinterpretq_f32_u32, vreinterpretq_f32_u64) + (vreinterpretq_f32_p8, vreinterpretq_f32_p16, vreinterpretq_f32_p64) + (vreinterpretq_f32_p128, vreinterpret_f64_f16, vreinterpret_f64_f32) + (vreinterpret_f64_p8, vreinterpret_f64_p16, vreinterpret_f64_p64) + (vreinterpret_f64_s8, vreinterpret_f64_s16, vreinterpret_f64_s32) + (vreinterpret_f64_s64, vreinterpret_f64_u8, vreinterpret_f64_u16) + (vreinterpret_f64_u32, vreinterpret_f64_u64, vreinterpretq_f64_f16) + (vreinterpretq_f64_f32, vreinterpretq_f64_p8, vreinterpretq_f64_p16) + (vreinterpretq_f64_p64, vreinterpretq_f64_s8, vreinterpretq_f64_s16) + (vreinterpretq_f64_s32, vreinterpretq_f64_s64, vreinterpretq_f64_u8) + (vreinterpretq_f64_u16, vreinterpretq_f64_u32, vreinterpretq_f64_u64) + (vreinterpret_s64_f16, vreinterpret_s64_f64, vreinterpret_s64_s8) + (vreinterpret_s64_s16, vreinterpret_s64_s32, vreinterpret_s64_f32) + (vreinterpret_s64_u8, vreinterpret_s64_u16, vreinterpret_s64_u32) + (vreinterpret_s64_u64, vreinterpret_s64_p8, vreinterpret_s64_p16) + (vreinterpret_s64_p64, vreinterpretq_s64_f64, vreinterpretq_s64_s8) + (vreinterpretq_s64_s16, vreinterpretq_s64_s32, vreinterpretq_s64_f16) + (vreinterpretq_s64_f32, vreinterpretq_s64_u8, vreinterpretq_s64_u16) + (vreinterpretq_s64_u32, vreinterpretq_s64_u64, vreinterpretq_s64_p8) + (vreinterpretq_s64_p16, vreinterpretq_s64_p64, vreinterpretq_s64_p128) + (vreinterpret_u64_f16, vreinterpret_u64_f64, vreinterpret_u64_s8) + (vreinterpret_u64_s16, vreinterpret_u64_s32, vreinterpret_u64_s64) + (vreinterpret_u64_f32, vreinterpret_u64_u8, vreinterpret_u64_u16) + (vreinterpret_u64_u32, vreinterpret_u64_p8, vreinterpret_u64_p16) + (vreinterpret_u64_p64, vreinterpretq_u64_f64, vreinterpretq_u64_s8) + (vreinterpretq_u64_s16, vreinterpretq_u64_s32, vreinterpretq_u64_s64) + (vreinterpretq_u64_f16, vreinterpretq_u64_f32, vreinterpretq_u64_u8) + (vreinterpretq_u64_u16, vreinterpretq_u64_u32, vreinterpretq_u64_p8) + (vreinterpretq_u64_p16, vreinterpretq_u64_p64, vreinterpretq_u64_p128) + (vreinterpret_s8_f16, vreinterpret_s8_f64, vreinterpret_s8_s16) + (vreinterpret_s8_s32, vreinterpret_s8_s64, vreinterpret_s8_f32) + (vreinterpret_s8_u8, vreinterpret_s8_u16, vreinterpret_s8_u32) + (vreinterpret_s8_u64, vreinterpret_s8_p8, vreinterpret_s8_p16) + (vreinterpret_s8_p64, vreinterpretq_s8_f64, vreinterpretq_s8_s16) + (vreinterpretq_s8_s32, vreinterpretq_s8_s64, vreinterpretq_s8_f16) + (vreinterpretq_s8_f32, vreinterpretq_s8_u8, vreinterpretq_s8_u16) + (vreinterpretq_s8_u32, vreinterpretq_s8_u64, vreinterpretq_s8_p8) + (vreinterpretq_s8_p16, vreinterpretq_s8_p64, vreinterpretq_s8_p128) + (vreinterpret_s16_f16, vreinterpret_s16_f64, vreinterpret_s16_s8) + (vreinterpret_s16_s32, vreinterpret_s16_s64, vreinterpret_s16_f32) + (vreinterpret_s16_u8, vreinterpret_s16_u16, vreinterpret_s16_u32) + (vreinterpret_s16_u64, vreinterpret_s16_p8, vreinterpret_s16_p16) + (vreinterpret_s16_p64, vreinterpretq_s16_f64, vreinterpretq_s16_s8) + (vreinterpretq_s16_s32, vreinterpretq_s16_s64, vreinterpretq_s16_f16) + (vreinterpretq_s16_f32, vreinterpretq_s16_u8, vreinterpretq_s16_u16) + (vreinterpretq_s16_u32, vreinterpretq_s16_u64, vreinterpretq_s16_p8) + (vreinterpretq_s16_p16, vreinterpretq_s16_p64, vreinterpretq_s16_p128) + (vreinterpret_s32_f16, vreinterpret_s32_f64, vreinterpret_s32_s8) + (vreinterpret_s32_s16, vreinterpret_s32_s64, vreinterpret_s32_f32) + (vreinterpret_s32_u8, vreinterpret_s32_u16, vreinterpret_s32_u32) + (vreinterpret_s32_u64, vreinterpret_s32_p8, vreinterpret_s32_p16) + (vreinterpret_s32_p64, vreinterpretq_s32_f64, vreinterpretq_s32_s8) + (vreinterpretq_s32_s16, vreinterpretq_s32_s64, vreinterpretq_s32_f16) + (vreinterpretq_s32_f32, vreinterpretq_s32_u8, vreinterpretq_s32_u16) + (vreinterpretq_s32_u32, vreinterpretq_s32_u64, vreinterpretq_s32_p8) + (vreinterpretq_s32_p16, vreinterpretq_s32_p64, vreinterpretq_s32_p128) + (vreinterpret_u8_f16, vreinterpret_u8_f64, vreinterpret_u8_s8) + (vreinterpret_u8_s16, vreinterpret_u8_s32, vreinterpret_u8_s64) + (vreinterpret_u8_f32, vreinterpret_u8_u16, vreinterpret_u8_u32) + (vreinterpret_u8_u64, vreinterpret_u8_p8, vreinterpret_u8_p16) + (vreinterpret_u8_p64, vreinterpretq_u8_f64, vreinterpretq_u8_s8) + (vreinterpretq_u8_s16, vreinterpretq_u8_s32, vreinterpretq_u8_s64) + (vreinterpretq_u8_f16, vreinterpretq_u8_f32, vreinterpretq_u8_u16) + (vreinterpretq_u8_u32, vreinterpretq_u8_u64, vreinterpretq_u8_p8) + (vreinterpretq_u8_p16, vreinterpretq_u8_p64, vreinterpretq_u8_p128) + (vreinterpret_u16_f16, vreinterpret_u16_f64, vreinterpret_u16_s8) + (vreinterpret_u16_s16, vreinterpret_u16_s32, vreinterpret_u16_s64) + (vreinterpret_u16_f32, vreinterpret_u16_u8, vreinterpret_u16_u32) + (vreinterpret_u16_u64, vreinterpret_u16_p8, vreinterpret_u16_p16) + (vreinterpret_u16_p64, vreinterpretq_u16_f64, vreinterpretq_u16_s8) + (vreinterpretq_u16_s16, vreinterpretq_u16_s32, vreinterpretq_u16_s64) + (vreinterpretq_u16_f16, vreinterpretq_u16_f32, vreinterpretq_u16_u8) + (vreinterpretq_u16_u32, vreinterpretq_u16_u64, vreinterpretq_u16_p8) + (vreinterpretq_u16_p16, vreinterpretq_u16_p64, vreinterpretq_u16_p128) + (vreinterpret_u32_f16, vreinterpret_u32_f64, vreinterpret_u32_s8) + (vreinterpret_u32_s16, vreinterpret_u32_s32, vreinterpret_u32_s64) + (vreinterpret_u32_f32, vreinterpret_u32_u8, vreinterpret_u32_u16) + (vreinterpret_u32_u64, vreinterpret_u32_p8, vreinterpret_u32_p16) + (vreinterpret_u32_p64, vreinterpretq_u32_f64, vreinterpretq_u32_s8) + (vreinterpretq_u32_s16, vreinterpretq_u32_s32, vreinterpretq_u32_s64) + (vreinterpretq_u32_f16, vreinterpretq_u32_f32, vreinterpretq_u32_u8) + (vreinterpretq_u32_u16, vreinterpretq_u32_u64, vreinterpretq_u32_p8) + (vreinterpretq_u32_p16, vreinterpretq_u32_p64, vreinterpretq_u32_p128) + (vreinterpretq_f64_p128, vreinterpretq_p128_f64, vreinterpret_bf16_u8) + (vreinterpret_bf16_u16, vreinterpret_bf16_u32, vreinterpret_bf16_u64) + (vreinterpret_bf16_s8, vreinterpret_bf16_s16, vreinterpret_bf16_s32) + (vreinterpret_bf16_s64, vreinterpret_bf16_p8, vreinterpret_bf16_p16) + (vreinterpret_bf16_p64, vreinterpret_bf16_f16, vreinterpret_bf16_f32) + (vreinterpret_bf16_f64, vreinterpretq_bf16_u8, vreinterpretq_bf16_u16) + (vreinterpretq_bf16_u32, vreinterpretq_bf16_u64, vreinterpretq_bf16_s8) + (vreinterpretq_bf16_s16, vreinterpretq_bf16_s32, vreinterpretq_bf16_s64) + (vreinterpretq_bf16_p8, vreinterpretq_bf16_p16, vreinterpretq_bf16_p64) + (vreinterpretq_bf16_p128, vreinterpretq_bf16_f16) + (vreinterpretq_bf16_f32, vreinterpretq_bf16_f64, vreinterpret_s8_bf16) + (vreinterpret_s16_bf16, vreinterpret_s32_bf16, vreinterpret_s64_bf16) + (vreinterpret_u8_bf16, vreinterpret_u16_bf16, vreinterpret_u32_bf16) + (vreinterpret_u64_bf16, vreinterpret_f16_bf16, vreinterpret_f32_bf16) + (vreinterpret_f64_bf16, vreinterpret_p8_bf16, vreinterpret_p16_bf16) + (vreinterpret_p64_bf16, vreinterpretq_s8_bf16, vreinterpretq_s16_bf16) + (vreinterpretq_s32_bf16, vreinterpretq_s64_bf16, vreinterpretq_u8_bf16) + (vreinterpretq_u16_bf16, vreinterpretq_u32_bf16, vreinterpretq_u64_bf16) + (vreinterpretq_f16_bf16, vreinterpretq_f32_bf16, vreinterpretq_f64_bf16) + (vreinterpretq_p8_bf16, vreinterpretq_p16_bf16, vreinterpretq_p64_bf16) + (vreinterpretq_p128_bf16): Delete + +2022-07-26 Andrew Carlotti <andrew.carlotti@arm.com> + + * config/aarch64/aarch64-builtins.cc + (aarch64_simd_builtin_std_type): Rename to... + (aarch64_int_or_fp_type): ...this, and allow irrelevant qualifiers. + (aarch64_lookup_simd_builtin_type): Rename to... + (aarch64_simd_builtin_type): ...this. Add const/pointer + support, and extract table lookup to... + (aarch64_lookup_simd_type_in_table): ...this function. + (aarch64_init_crc32_builtins): Update to use aarch64_simd_builtin_type. + (aarch64_init_fcmla_laneq_builtins): Ditto. + (aarch64_init_simd_builtin_functions): Ditto. + +2022-07-26 Andrew Carlotti <andrew.carlotti@arm.com> + + * config/aarch64/aarch64-builtins.cc + (aarch64_general_gimple_fold_builtin): Add combine. + +2022-07-26 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106189 + * gimple-array-bounds.cc (array_bounds_checker::check_mem_ref): + Divide using offset_ints. + +2022-07-26 Lulu Cheng <chenglulu@loongson.cn> + + * common/config/loongarch/loongarch-common.cc: + Enable '-fsection-anchors' when O1 and more advanced optimization. + * config/loongarch/genopts/loongarch.opt.in: Add new option + '-mexplicit-relocs', and enable by default. + * config/loongarch/loongarch-protos.h (loongarch_split_move_insn_p): + Delete function declaration. + (loongarch_split_move_insn): Delete function declaration. + (loongarch_split_symbol_type): Add function declaration. + * config/loongarch/loongarch.cc (enum loongarch_address_type): + Add new address type 'ADDRESS_LO_SUM'. + (loongarch_classify_symbolic_expression): New function definitions. + Classify the base of symbolic expression X, given that X appears in + context CONTEXT. + (loongarch_symbol_insns): Add a judgment condition TARGET_EXPLICIT_RELOCS. + (loongarch_split_symbol_type): New function definitions. + Determines whether the symbol load should be split into two instructions. + (loongarch_valid_lo_sum_p): New function definitions. + Return true if a LO_SUM can address a value of mode MODE when the LO_SUM + symbol has type SYMBOL_TYPE. + (loongarch_classify_address): Add handling of 'LO_SUM'. + (loongarch_address_insns): Add handling of 'ADDRESS_LO_SUM'. + (loongarch_signed_immediate_p): Sort code. + (loongarch_12bit_offset_address_p): Return true if address type is ADDRESS_LO_SUM. + (loongarch_const_insns): Add handling of 'HIGH'. + (loongarch_split_move_insn_p): Add the static attribute to the function. + (loongarch_emit_set): New function definitions. + (loongarch_call_tls_get_addr): Add symbol handling when defining TARGET_EXPLICIT_RELOCS. + (loongarch_legitimize_tls_address): Add symbol handling when defining the + TARGET_EXPLICIT_RELOCS macro. + (loongarch_split_symbol): New function definitions. Split symbol. + (loongarch_legitimize_address): Add codes see if the address can split into a high part + and a LO_SUM. + (loongarch_legitimize_const_move): Add codes split moves of symbolic constants into + high and low. + (loongarch_split_move_insn): Delete function definitions. + (loongarch_output_move): Add support for HIGH and LO_SUM. + (loongarch_print_operand_reloc): New function definitions. + Print symbolic operand OP, which is part of a HIGH or LO_SUM in context CONTEXT. + (loongarch_memmodel_needs_release_fence): Sort code. + (loongarch_print_operand): Rearrange alphabetical order and add H and L to support HIGH + and LOW output. + (loongarch_print_operand_address): Add handling of 'ADDRESS_LO_SUM'. + (TARGET_MIN_ANCHOR_OFFSET): Define macro to -IMM_REACH/2. + (TARGET_MAX_ANCHOR_OFFSET): Define macro to IMM_REACH/2-1. + * config/loongarch/loongarch.md (movti): Delete the template. + (*movti): Delete the template. + (movtf): Delete the template. + (*movtf): Delete the template. + (*low<mode>): New template of normal symbol low address. + (@tls_low<mode>): New template of tls symbol low address. + (@ld_from_got<mode>): New template load address from got table. + (@ori_l_lo12<mode>): New template. + * config/loongarch/loongarch.opt: Update from loongarch.opt.in. + * config/loongarch/predicates.md: Add support for symbol_type HIGH. + +2022-07-26 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/constraints.md (a): Delete the constraint. + (b): A constant call not local address. + (h): Delete the constraint. + (t): Delete the constraint. + * config/loongarch/loongarch-opts.cc (loongarch_config_target): + Remove cModel type support other than normal. + * config/loongarch/loongarch-protos.h (enum loongarch_symbol_type): + Add new symbol type 'SYMBOL_PCREL', 'SYMBOL_TLS_IE' and 'SYMBOL_TLS_LE'. + (loongarch_split_symbol): Delete useless function declarations. + (loongarch_split_symbol_type): Delete useless function declarations. + * config/loongarch/loongarch.cc (enum loongarch_address_type): + Delete unnecessary comment information. + (loongarch_symbol_binds_local_p): Modified the judgment order of label + and symbol. + (loongarch_classify_symbol): Return symbol type. If symbol is a label, + or symbol is a local symbol return SYMBOL_PCREL. If is a tls symbol, + return SYMBOL_TLS. If is a not local symbol return SYMBOL_GOT_DISP. + (loongarch_symbolic_constant_p): Add handling of 'SYMBOL_TLS_IE' + 'SYMBOL_TLS_LE' and 'SYMBOL_PCREL'. + (loongarch_symbol_insns): Add handling of 'SYMBOL_TLS_IE' 'SYMBOL_TLS_LE' + and 'SYMBOL_PCREL'. + (loongarch_address_insns): Sort code. + (loongarch_12bit_offset_address_p): Sort code. + (loongarch_14bit_shifted_offset_address_p): Sort code. + (loongarch_call_tls_get_addr): Sort code. + (loongarch_legitimize_tls_address): Sort code. + (loongarch_output_move): Remove schema support for cmodel other than normal. + (loongarch_memmodel_needs_release_fence): Sort code. + (loongarch_print_operand): Sort code. + * config/loongarch/loongarch.h (LARCH_U12BIT_OFFSET_P): + Rename to LARCH_12BIT_OFFSET_P. + (LARCH_12BIT_OFFSET_P): New macro. + * config/loongarch/loongarch.md: Reimplement the function call. Remove schema + support for cmodel other than normal. + * config/loongarch/predicates.md (is_const_call_weak_symbol): Delete this predicate. + (is_const_call_plt_symbol): Delete this predicate. + (is_const_call_global_noplt_symbol): Delete this predicate. + (is_const_call_no_local_symbol): New predicate, determines whether it is a local + symbol or label. + +2022-07-26 Kewen Lin <linkw@linux.ibm.com> + + PR target/106091 + * config/rs6000/rs6000-p8swap.cc (replace_swapped_aligned_store): Copy + REG_EH_REGION when replacing one store insn having it. + (replace_swapped_aligned_load): Likewise. + +2022-07-25 Aldy Hernandez <aldyh@redhat.com> + + * Makefile.in (OBJS): Add range-op-float.o. + * range-op.cc (get_float_handler): New. + (range_op_handler::range_op_handler): Save code and type for + delayed querying. + (range_op_handler::oeprator bool): Move from header file, and + add support for floats. + (range_op_handler::fold_range): Add support for floats. + (range_op_handler::op1_range): Same. + (range_op_handler::op2_range): Same. + (range_op_handler::lhs_op1_relation): Same. + (range_op_handler::lhs_op2_relation): Same. + (range_op_handler::op1_op2_relation): Same. + * range-op.h (class range_operator_float): New. + (class floating_op_table): New. + * value-query.cc (range_query::get_tree_range): Add case for + REAL_CST. + * range-op-float.cc: New file. + +2022-07-25 Roger Sayle <roger@nextmovesoftware.com> + Uroš Bizjak <ubizjak@gmail.com> + + PR target/91681 + * config/i386/i386-expand.cc (split_double_concat): A new helper + function for setting a double word value from two word values. + * config/i386/i386-protos.h (split_double_concat): Prototype here. + * config/i386/i386.md (zero_extendditi2): New define_insn_and_split. + (*add<dwi>3_doubleword_zext): New define_insn_and_split. + (*sub<dwi>3_doubleword_zext): New define_insn_and_split. + (*concat<mode><dwi>3_1): New define_insn_and_split replacing + previous define_split for implementing DST = (HI<<32)|LO as + pair of move instructions, setting lopart and hipart. + (*concat<mode><dwi>3_2): Likewise. + (*concat<mode><dwi>3_3): Likewise, where HI is zero_extended. + (*concat<mode><dwi>3_4): Likewise, where HI is zero_extended. + +2022-07-25 Aldy Hernandez <aldyh@redhat.com> + + PR middle-end/106432 + * gimple-range.cc (gimple_ranger::range_on_edge): Return false + when the result range type is unsupported. + +2022-07-25 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * config/rs6000/rtems.h (CPLUSPLUS_CPP_SPEC): Undef. + +2022-07-25 Richard Biener <rguenther@suse.de> + + PR middle-end/106414 + * match.pd (~(x ^ y) -> x == y): Restrict to single bit + precision types. + +2022-07-25 Andre Vieira <andre.simoesdiasvieira@arm.com> + + * config/aarch64/aarch64.md (rbit<mode>2): Rename this ... + (@aarch64_rbit<mode>): ... to this and change it in... + (ffs<mode>2,ctz<mode>2): ... here. + (@aarch64_rev16<mode>): New. + * config/aarch64/aarch64-builtins.cc: (aarch64_builtins): + Define the following enum AARCH64_REV16, AARCH64_REV16L, + AARCH64_REV16LL, AARCH64_RBIT, AARCH64_RBITL, AARCH64_RBITLL. + (aarch64_init_data_intrinsics): New. + (aarch64_general_init_builtins): Add call to + aarch64_init_data_intrinsics. + (aarch64_expand_builtin_data_intrinsic): New. + (aarch64_general_expand_builtin): Add call to + aarch64_expand_builtin_data_intrinsic. + * config/aarch64/arm_acle.h (__clz, __clzl, __clzll, __cls, __clsl, + __clsll, __rbit, __rbitl, __rbitll, __rev, __revl, __revll, __rev16, + __rev16l, __rev16ll, __ror, __rorl, __rorll, __revsh): New. + +2022-07-25 Martin Liska <mliska@suse.cz> + + * doc/extend.texi: Remove trailing whitespaces. + * doc/invoke.texi: Likewise. + +2022-07-25 Aldy Hernandez <aldyh@redhat.com> + + * value-range-pretty-print.cc (vrange_printer::visit): New. + (vrange_printer::print_frange_prop): New. + * value-range-pretty-print.h (class vrange_printer): Add visit and + print_frange_prop. + * value-range-storage.h (vrange_allocator::alloc_vrange): Handle frange. + (vrange_allocator::alloc_frange): New. + * value-range.cc (vrange::operator=): Handle frange. + (vrange::operator==): Same. + (frange::accept): New. + (frange::set): New. + (frange::normalize_kind): New. + (frange::union_): New. + (frange::intersect): New. + (frange::operator=): New. + (frange::operator==): New. + (frange::supports_type_p): New. + (frange::verify_range): New. + * value-range.h (enum value_range_discriminator): Handle frange. + (class fp_prop): New. + (FP_PROP_ACCESSOR): New. + (class frange_props): New. + (FRANGE_PROP_ACCESSOR): New. + (class frange): New. + (Value_Range::init): Handle frange. + (Value_Range::operator=): Same. + (Value_Range::supports_type_p): Same. + (frange_props::operator==): New. + (frange_props::union_): New. + (frange_props::intersect): New + (frange::frange): New. + (frange::type): New. + (frange::set_varying): New. + (frange::set_undefined): New. + +2022-07-25 Peter Bergner <bergner@linux.ibm.com> + Kewen Lin <linkw@linux.ibm.com> + + PR testsuite/106345 + * config/rs6000/rs6000.h (DRIVER_SELF_SPECS): Adjust -mdejagnu-cpu + to filter out all -mtune options. + +2022-07-24 Aldy Hernandez <aldyh@redhat.com> + + * value-query.cc (range_query::get_value_range): Add assert. + * vr-values.cc (vr_values::range_of_expr): Make sure we don't ICE + on unsupported types in vr_values. + (simplify_using_ranges::simplify): Same. + +2022-07-24 Aldy Hernandez <aldyh@redhat.com> + + * tree-ssanames.cc (get_nonzero_bits): Return -1 for unsupported + types. + * value-query.cc (get_ssa_name_range_info): Remove precision check. + +2022-07-24 Aldy Hernandez <aldyh@redhat.com> + + * value-relation.cc (value_relation::set_relation): Remove assert. + (path_oracle::register_relation): Exit when trying to register + same SSA name relations. + +2022-07-24 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-cache.cc (ranger_cache::edge_range): Convert to vrange. + (ranger_cache::range_from_dom): Same. + * tree-ssa-dom.cc + (dom_opt_dom_walker::set_global_ranges_from_unreachable_edges): Same. + +2022-07-24 Roger Sayle <roger@nextmovesoftware.com> + H.J. Lu <hjl.tools@gmail.com> + + PR target/106303 + PR target/106347 + * config/i386/i386-features.cc (make_vector_copies): Move from + general_scalar_chain to scalar_chain. + (convert_reg): Likewise. + (convert_insn_common): New scalar_chain method split out from + general_scalar_chain convert_insn. + (convert_registers): Move from general_scalar_chain to + scalar_chain. + (scalar_chain::convert): Call convert_insn_common before calling + convert_insn. + (timode_remove_non_convertible_regs): Iterate until there are + no further changes to the candidates. + * config/i386/i386-features.h (scalar_chain::hash_map): Move + from general_scalar_chain. + (scalar_chain::convert_reg): Likewise. + (scalar_chain::convert_insn_common): New shared method. + (scalar_chain::make_vector_copies): Move from general_scalar_chain. + (scalar_chain::convert_registers): Likewise. No longer virtual. + (general_scalar_chain::hash_map): Delete. Moved to scalar_chain. + (general_scalar_chain::convert_reg): Likewise. + (general_scalar_chain::make_vector_copies): Likewise. + (general_scalar_chain::convert_registers): Delete virtual method. + (timode_scalar_chain::convert_registers): Likewise. + +2022-07-23 Immad Mir <mirimmad@outlook.com> + + * doc/extend.texi: Add fd_arg, fd_arg_read and fd_arg_write under + "Common Function Attributes" section. + * doc/invoke.texi: Add docs to -Wanalyzer-fd-access-mode-mismatch, + -Wanalyzer-use-after-close, -Wanalyzer-fd-use-without-check that these + warnings may be emitted through usage of three function attributes used + for static analysis of file descriptors namely fd_arg, fd_arg_read and + fd_arg_write. + +2022-07-22 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md (*masktrue_const_bitcmpl): + Add a new insn_and_split pattern, and a few split patterns for + spacial cases. + +2022-07-22 Richard Sandiford <richard.sandiford@arm.com> + + * graphds.cc (graphds_scc): Fix algorithm attribution. + +2022-07-22 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106403 + * tree-ssa-sccvn.cc (vn_reference_lookup_3): Move stored + value valueization after check for IFN_MASKED_STORE or + IFN_LEN_STORE. + +2022-07-22 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106397 + * tree-ssa-loop-prefetch.cc (emit_mfence_after_loop): Do + not update SSA form here. + (mark_nontemporal_stores): Return whether we marked any + non-temporal stores and inserted mfence. + (loop_prefetch_arrays): Note when we need to update SSA. + (tree_ssa_prefetch_arrays): Perform required (LC) SSA update + at the end of the pass. + +2022-07-22 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106387 + * tree-vect-stmts.cc (vectorizable_load): Use make_ssa_name + if ptr is not an SSA name. + +2022-07-22 liuhongt <hongtao.liu@intel.com> + + PR target/106038 + * config/i386/mmx.md (<code><mode>3): New define_expand, it's + original "<code><mode>3". + (*<code><mode>3): New define_insn, it's original + "<code><mode>3" be extended to handle memory and immediate + operand with ix86_binary_operator_ok. Also adjust define_split + after it. + (mmxinsnmode): New mode attribute. + (*mov<mode>_imm): Refactor with mmxinsnmode. + * config/i386/predicates.md + (register_or_x86_64_const_vector_operand): New predicate. + +2022-07-22 Will Schmidt <will_schmidt@vnet.ibm.com> + + * config/rs6000/altivec.md: + (vstrir_code_<mode>): Rename to... + (vstrir_direct_<mode>): ... this. + (vstrir_p_code_<mode>): Rename to... + (vstrir_p_direct_<mode>): ... this. + (vstril_code_<mode>): Rename to... + (vstril_direct_<mode>): ... this. + (vstril_p_code_<mode>): Rename to... + (vstril_p_direct_<mode>): ... this. + +2022-07-22 Will Schmidt <will_schmidt@vnet.ibm.com> + + * config/rs6000/rs6000-c.cc: Update comments. + (rs6000_target_modify_macros): Remove bu_mask references. + (rs6000_define_or_undefine_macro): Replace bu_mask reference + with a rs6000_cpu value check. + (rs6000_cpu_cpp_builtins): Remove rs6000_builtin_mask_calculate() + parameter from call to rs6000_target_modify_macros. + * config/rs6000/rs6000-protos.h (rs6000_target_modify_macros, + rs6000_target_modify_macros_ptr): Remove parameter from extern + for the prototype. + * config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): Remove + parameter from prototype, update calls to this function. + (rs6000_print_builtin_options): Remove prototype, call and function. + (rs6000_builtin_mask_calculate): Remove function. + (rs6000_debug_reg_global): Remove call to rs6000_print_builtin_options. + (rs6000_option_override_internal): Remove rs6000_builtin_mask var + and builtin_mask debug output. + (rs6000_builtin_mask_names): Remove. + (rs6000_pragma_target_parse): Remove prev_bumask, cur_bumask, + diff_bumask references; Update calls to rs6000_target_modify_ptr. + * config/rs6000/rs6000.opt (rs6000_builtin_mask): Remove. + +2022-07-21 Sam Feifer <sfeifer@redhat.com> + + PR tree-optimization/94920 + * match.pd (x >= 0 ? x : 0) + (x <= 0 ? -x : 0): New simplification. + (x <= 0 ? -x : 0): New simplification. + +2022-07-21 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> + + Revert: + 2022-07-19 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> + + * tree-ssa-forwprop.cc (simplify_permutation): Use lhs type + instead of TREE_TYPE (arg0) as result type in folding VEC_PERM_EXPR. + +2022-07-21 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106379 + * match.pd (~(a ^ b) -> a == b): New pattern. + +2022-07-21 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106378 + * tree-ssa-dse.cc (initialize_ao_ref_for_dse): Handle + LEN_STORE, add mode to initialize a may-def and handle + MASK_STORE that way. + (dse_optimize_stmt): Query may-defs. Handle internal + functions LEN_STORE and MASK_STORE similar to how + we handle memory builtins but without byte tracking. + +2022-07-21 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106365 + * tree-ssa-sccvn.cc (pd_data::rhs_off): New field determining + the offset to start encoding of RHS from. + (vn_walk_cb_data::vn_walk_cb_data): Initialize it. + (vn_walk_cb_data::push_partial_def): Allow the first partial + definition to be fully providing the def. Offset RHS + before encoding if requested. + (vn_reference_lookup_3): Initialize def_rhs everywhere. + Add support for .MASK_STORE and .LEN_STORE (partial) definitions. + +2022-07-21 Richard Biener <rguenther@suse.de> + + * tree-ssa-alias.cc (ref_maybe_used_by_call_p_1): Special-case + store internal functions and IFN_MASK_LOAD, IFN_LEN_LOAD + and IFN_MASK_LOAD_LANES. + (call_may_clobber_ref_p_1): Special-case IFN_MASK_STORE, + IFN_LEN_STORE and IFN_MASK_STORE_LANES. + +2022-07-20 Alexander Monakov <amonakov@ispras.ru> + + PR rtl-optimization/101347 + * builtins.cc (expand_builtin) [BUILT_IN_SETJMP_SETUP]: Move + population of nonlocal_goto_handler_labels from here ... + (expand_builtin) [BUILT_IN_SETJMP_RECEIVER]: ... to here. + * rtlanal.cc (remove_node_from_insn_list): Verify that a + duplicate is not present in the remainder of the list. + +2022-07-20 Alexander Monakov <amonakov@ispras.ru> + + * rtl.h (remove_node_from_expr_list): Remove declaration. + * rtlanal.cc (remove_node_from_expr_list): Remove (no uses). + +2022-07-20 Richard Biener <rguenther@suse.de> + + * tree-vect-data-refs.cc (bump_vector_ptr): Return an + invariant updated address when the input was invariant. + +2022-07-20 liuhongt <hongtao.liu@intel.com> + + * passes.def: (Split pass_cse_sincos to pass_expand_powcabs + and pass_cse_sincos, and move pass_cse_sincos after vectorizer). + * timevar.def (TV_TREE_POWCABS): New timevar. + * tree-pass.h (make_pass_expand_powcabs): Split from pass_cse_sincos. + * tree-ssa-math-opts.cc (gimple_expand_builtin_cabs): Ditto. + (class pass_expand_powcabs): Ditto. + (pass_expand_powcabs::execute): Ditto. + (make_pass_expand_powcabs): Ditto. + (pass_cse_sincos::execute): Remove pow/cabs expand part. + (make_pass_cse_sincos): Ditto. + +2022-07-20 Richard Biener <richard.guenther@gmail.com> + Hongtao Liu <hongtao.liu@intel.com> + + PR tree-optimization/106010 + * tree-complex.cc (init_dont_simulate_again): Lower complex + type move. + (expand_complex_move): Also expand COMPLEX_CST for rhs. + +2022-07-19 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-cache.cc (ranger_cache::range_from_dom): Check + for incoming ranges on join nodes and add to worklist. + +2022-07-19 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-cache.cc (ranger_cache::resolve_dom): New. + (ranger_cache::range_from_dom): Put all nodes to be calculated + in the worklist and resolve after the dom walk. + * gimple-range-cache.h (resolve_dom): New prototype. + +2022-07-19 Alexander Monakov <amonakov@ispras.ru> + + * tree-cfg.cc (gimple_verify_flow_info): Check placement of + returns_twice calls. + +2022-07-19 Alexander Monakov <amonakov@ispras.ru> + + * cfghooks.cc (duplicate_block): Expand comment. + * tree-cfg.cc (gimple_can_duplicate_bb_p): Reject blocks with + calls that may return twice. + +2022-07-19 Alexander Monakov <amonakov@ispras.ru> + + * tree-ssa-sink.cc (select_best_block): Punt if selected block + has incoming abnormal edges. + +2022-07-19 Martin Liska <mliska@suse.cz> + + * doc/extend.texi: Remove trailing :. + +2022-07-19 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> + + * tree-ssa-forwprop.cc (simplify_permutation): Use lhs type + instead of TREE_TYPE (arg0) as result type in folding VEC_PERM_EXPR. + +2022-07-19 Richard Biener <rguenther@suse.de> + + PR middle-end/106331 + * builtins.cc (get_memory_rtx): Compute alignment from + the original address and set MEM_OFFSET to unknown when + we create a MEM_EXPR from the base object of the address. + +2022-07-19 Richard Biener <rguenther@suse.de> + + PR lto/106334 + * dwarf2out.cc (dwarf2out_register_external_die): Allow + map entry re-use during WPA. + +2022-07-19 Roger Sayle <roger@nextmovesoftware.com> + Richard Biener <rguenther@suse.de> + + PR c/106264 + * builtins.cc (fold_builtin_frexp): Call suppress_warning on + COMPOUND_EXPR to silence spurious warning if result isn't used. + (fold_builtin_modf): Likewise. + (do_mpfr_remquo): Likewise. + +2022-07-19 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.cc (xtensa_rtx_costs): + Change the relative cost of '(set (reg) (const_int N))' where + N fits into signed 12-bit from 4 to 0 if optimizing for size. + And use the appropriate macro instead of the bare number 4. + +2022-07-18 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/106280 + * value-relation.cc (dom_oracle::register_relation): Register + transitives only when it is possible for there to be one. + (dom_oracle::set_one_relation): Return NULL if this is an + existing relation. + +2022-07-18 Maciej W. Rozycki <macro@embecosm.com> + + * doc/invoke.texi (RISC-V Options): Add index references for + `mrelax' and `mriscv-attribute'. + +2022-07-18 Maciej W. Rozycki <macro@embecosm.com> + + * doc/invoke.texi (Option Summary): Add missing second space + around `-mstack-protector-guard-reg='. + +2022-07-18 Maciej W. Rozycki <macro@embecosm.com> + + * doc/invoke.texi (Option Summary): Fix `-mno-riscv-attribute'. + (RISC-V Options): Likewise, and `-mriscv-attribute'. + +2022-07-18 Claudiu Zissulescu <claziss@gmail.com> + + * config/arc/arc-arch.h (arc_tune_attr): Add + ARC_TUNE_ARCHS4X_REL31A variant. + * config/arc/arc.cc (arc_override_options): Tune options for + release 310a. + (arc_sched_issue_rate): Use correct enum. + (arc600_corereg_hazard): Textual change. + (arc_hazard): Add release 310a tunning. + * config/arc/arc.md (tune): Update and take into consideration new + tune option. + (tune_dspmpy): Likewise. + (tune_store): New attribute. + * config/arc/arc.opt (mtune): New tune option. + * config/arc/arcHS4x.md (hs4x_brcc0, hs4x_brcc1): New cpu units. + (hs4x_brcc_op): New instruction rezervation. + (hs4x_data_store_1_op): Likewise. + * config/arc/arc-cpus.def (hs4x_rel31): New cpu variant. + * config/arc/arc-tables.opt: Regenerate. + * config/arc/t-multilib: Likewise. + * doc/invoke.texi (ARC): Update mcpu and tune sections. + +2022-07-18 Richard Biener <rguenther@suse.de> + + * tree-loop-distribution.cc (loop_distribution::distribute_loop): + When computing cost-based merging do not disregard builtin + classified partitions in some cases. + +2022-07-18 Richard Sandiford <richard.sandiford@arm.com> + + PR target/106253 + * config/arm/arm-builtins.cc (arm_builtin_vectorized_function): + Delete. + * config/arm/arm-protos.h (arm_builtin_vectorized_function): Delete. + * config/arm/arm.cc (TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): + Delete. + * config/arm/arm_neon_builtins.def (copysignf): Delete. + * config/arm/iterators.md (nvrint_pattern): New attribute. + * config/arm/neon.md (<NEON_VRINT:nvrint_pattern><VCVTF:mode>2): + New pattern. + (l<NEON_VCVT:nvrint_pattern><su_optab><VCVTF:mode><v_cmp_result>2): + Likewise. + (neon_copysignf<mode>): Rename to... + (copysign<mode>3): ...this. + +2022-07-18 Claudiu Zissulescu <claziss@gmail.com> + + * config/arc/arc.cc (arc_expand_epilogue): Adjust the frame + pointer first when in interrupts. + +2022-07-18 Richard Biener <rguenther@suse.de> + + * tree-loop-distribution.cc (copy_loop_before): Add + the ability to replace the original LC PHI defs. + (generate_loops_for_partition): Pass through a flag + whether to redirect original LC PHI defs. + (generate_code_for_partition): Likewise. + (loop_distribution::distribute_loop): Compute the partition + that should provide the LC PHI defs for common reductions + and pass that down. + +2022-07-18 Richard Ball <richard.ball@arm.com> + + * config/aarch64/aarch64.cc (aarch64_evpc_trn): Use std:swap. + (aarch64_evpc_uzp): Likewise. + (aarch64_evpc_zip): Likewise. + +2022-07-18 Roger Sayle <roger@nextmovesoftware.com> + + PR target/106231 + * config/i386/i386.md (*ctzsidi2_<s>ext): New insn_and_split + to recognize any_extend:DI of ctz:SI which is implicitly extended. + (*ctzsidi2_<s>ext_falsedep): New define_insn to model a DImode + extended ctz:SI that has preceding xor to break false dependency. + +2022-07-18 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/predicates.md (x86_64_const_vector_operand): + Check the operand's mode matches the specified mode argument. + +2022-07-18 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/sse.md (kunpckhi): Add UNSPEC_MASKOP unspec. + (kunpcksi): Likewise, add UNSPEC_MASKOP unspec. + (kunpckdi): Likewise, add UNSPEC_MASKOP unspec. + (vec_pack_trunc_qi): Update to specify the now required + UNSPEC_MASKOP unspec. + (vec_pack_trunc_<mode>): Likewise. + +2022-07-16 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md + (*masktrue_const_pow2_minus_one, *masktrue_const_negative_pow2, + *masktrue_const_shifted_mask): If the immediate for bitwise AND is + represented as '-(1 << N)', decrease the lower bound of N from 12 + to 1. And the other immediate for conditional branch is now no + longer limited to zero, but also one of some positive integers. + Finally, remove the checks of some conditions, because the comparison + expressions that don't satisfy such checks are determined as + compile-time constants and thus will be optimized away before + RTL expansion. + +2022-07-16 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.cc (xtensa_emit_constantsynth): Remove. + (xtensa_constantsynth_2insn): Change to try all three synthetic + methods and to use the one that fits the immediate value of + the seed into a Narrow Move Immediate instruction "MOVI.N" + when the Code Density Option is configured. + +2022-07-15 H.J. Lu <hjl.tools@gmail.com> + + PR target/85620 + * config/i386/i386.cc (ix86_function_ok_for_sibcall): Return + false if callee has indirect_return attribute and caller + doesn't. + +2022-07-15 Roger Sayle <roger@nextmovesoftware.com> + + PR target/106273 + * config/i386/i386.md (*andn<dwi>3_doubleword_bmi): Update the + constraints to reflect the output is earlyclobber, unless it is + the same register (pair) as one of the operands. + +2022-07-15 David Malcolm <dmalcolm@redhat.com> + + * doc/invoke.texi (Static Analyzer Options): Add the new fd + warnings to the initial gccoptlist, and to the list of those + disabled by -fanalyzer-checker=taint. + +2022-07-15 Andrew Carlotti <andrew.carlotti@arm.com> + + * config/aarch64/aarch64-builtins.cc + (enum aarch64_type_qualifiers): Remove qualifier_internal. + (aarch64_init_simd_builtin_functions): Remove qualifier_internal check. + +2022-07-15 Andrew Carlotti <andrew.carlotti@arm.com> + + * config/aarch64/aarch64-builtins.cc + (v1di_UP): Add V1DI mode to _UP macros. + * config/aarch64/aarch64-modes.def (VECTOR_MODE): Add V1DI mode. + * config/aarch64/aarch64-simd-builtin-types.def: Use V1DI mode. + * config/aarch64/aarch64-simd.md + (vec_extractv2dfv1df): Replace with... + (vec_extract<mode><V1half>): ...this. + * config/aarch64/aarch64.cc + (aarch64_classify_vector_mode): Add V1DI mode. + * config/aarch64/iterators.md + (VQ_2E, V1HALF, V1half): New. + (nunits): Add V1DI mode. + +2022-07-15 Roger Sayle <roger@nextmovesoftware.com> + + PR target/106278 + * config/i386/i386-features.cc (general_scalar_chain::convert_insn): + Fix indentation whitespace. + (timode_scalar_chain::fix_debug_reg_uses): Likewise. + (timode_scalar_chain::convert_insn): Delete dead code. + Update TImode REG_EQUAL_NOTE even if the SET_DEST is already V1TI. + Fix indentation whitespace. + (convertible_comparison_p): Likewise. + (timode_scalar_to_vector_candidate_p): Likewise. + +2022-07-15 Aldy Hernandez <aldyh@redhat.com> + + * gimple-pretty-print.cc (dump_ssaname_info): Use pp_vrange. + +2022-07-15 Aldy Hernandez <aldyh@redhat.com> + + * Makefile.in (OBJS): Add value-range-pretty-print.o. + * pretty-print.h (pp_vrange): New. + * value-range.cc (vrange::dump): Call pp version. + (unsupported_range::dump): Move to its own file. + (dump_bound_with_infinite_markers): Same. + (irange::dump): Same. + (irange::dump_bitmasks): Same. + (vrange::debug): Remove. + * value-range.h: Remove virtual designation for dump methods. + Remove dump_bitmasks method. + * value-range-pretty-print.cc: New file. + * value-range-pretty-print.h: New file. + +2022-07-15 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (irange::accept): New. + (unsupported_range::accept): New. + * value-range.h (class vrange_visitor): New. + (class vrange): Add accept method. + (class unsupported_range): Same. + (class Value_Range): Same. + +2022-07-15 Jonathan Wakely <jwakely@redhat.com> + + * diagnostic-format-json.cc (json_from_location_range): Adjust + to new label_text API. + * diagnostic-format-sarif.cc (sarif_builder::make_location_object): + Likewise. + * diagnostic-show-locus.cc (struct pod_label_text): Likewise. + (layout::print_any_labels): Likewise. + * tree-diagnostic-path.cc (class path_label): Likewise. + (struct event_range): Likewise. + (default_tree_diagnostic_path_printer): Likewise. + (default_tree_make_json_for_path): Likewise. + +2022-07-15 konglin1 <lingling.kong@intel.com> + + PR target/106113 + * config/i386/i386-builtin.def (BDESC): Fix [u]comi{ss,sd} + comparison due to intrinsics changed over time. + * config/i386/i386-expand.cc (ix86_ssecom_setcc): + Add unordered check and mode for sse comi codegen. + (ix86_expand_sse_comi): Add unordered check and check a different + CCmode. + (ix86_expand_sse_comi_round):Extract unordered check and mode part + in ix86_ssecom_setcc. + +2022-07-15 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> + + * config/aarch64/aarch64.cc (aarch64_vectorize_vec_perm_const): Use + op_mode instead of vmode in calls to force_reg for op0 and op1. + +2022-07-14 H.J. Lu <hjl.tools@gmail.com> + + PR tree-optimization/103798 + * tree-ssa-forwprop.cc: Include "tree-ssa-strlen.h". + (simplify_builtin_call): Inline memchr with constant strings of + no more than the bytes of a word. + * tree-ssa-strlen.cc (use_in_zero_equality): Make it global. + * tree-ssa-strlen.h (use_in_zero_equality): New. + +2022-07-14 Eric Botcazou <ebotcazou@adacore.com> + + * gimplify.cc (lookup_tmp_var): Add NOT_GIMPLE_REG boolean parameter + and set DECL_NOT_GIMPLE_REG_P on the variable according to it. + (internal_get_tmp_var): Add NOT_GIMPLE_REG boolean parameter and + pass it in the call to lookup_tmp_var. + (get_formal_tmp_var): Pass false in the call to lookup_tmp_var. + (get_initialized_tmp_var): Likewise. + (prepare_gimple_addressable): Call internal_get_tmp_var instead of + get_initialized_tmp_var with NOT_GIMPLE_REG set to true. + +2022-07-14 Martin Liska <mliska@suse.cz> + + * doc/gimple.texi: Close properly a deftypefn. + +2022-07-14 Martin Liska <mliska@suse.cz> + + * doc/gimple.texi: Close properly a deftypefn. + +2022-07-14 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md: + In FP constant synthesis split pattern, subcontract to + avoid_constant_pool_reference() as in the case of integer, + because it can handle well too. And cast to int32_t before + calling xtensa_constantsynth() in order to ignore upper 32-bit. + +2022-07-13 Aldy Hernandez <aldyh@redhat.com> + + * range-op.cc (operator_lt::fold_range): Use nonzero bits. + +2022-07-13 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (irange::copy_to_legacy): Set nonzero mask. + (irange::legacy_intersect): Clear nonzero mask. + (irange::legacy_union): Same. + (irange::invert): Same. + +2022-07-13 Richard Biener <rguenther@suse.de> + + * tree-ssa-dom.h (record_temporary_equivalences): Remove. + * tree-ssa-dom.cc (dom_jt_state::m_blocks_on_stack): New. + (dom_jt_state::get_blocks_on_stack): Likewise. + (dom_opt_dom_walker::dom_opt_dom_walker): Take dom_jt_state. + (back_propagate_equivalences): Remove dominator bitmap + compute and instead use passed in m_blocks_on_stack. + (record_temporary_equivalences): Likewise. + (record_equivalences_from_incoming_edge): Likewise. + (dom_opt_dom_walker::before_dom_children): Maintain and + pass down blocks on stack. + (dom_opt_dom_walker::after_dom_children): Likewise. + +2022-07-13 Andrew Carlotti <andrew.carlotti@arm.com> + + * config/aarch64/aarch64-builtins.cc + (aarch64_general_gimple_fold_builtin): Add fixup for invalid GIMPLE. + +2022-07-13 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106249 + * tree-ssa-loop-manip.cc (tree_transform_and_unroll_loop): + Only verify LC SSA of the new_loop if we created it. + Use TODO_update_ssa_nophi for the SSA update after versioning + the loop. + +2022-07-12 Aldy Hernandez <aldyh@redhat.com> + + * range-op.cc (unsigned_singleton_p): Remove. + (operator_bitwise_and::remove_impossible_ranges): Remove. + (operator_bitwise_and::fold_range): Set nonzero bits. * + * value-range.cc (irange::get_nonzero_bits): Remove + legacy_mode_p assert. + (irange::dump_bitmasks): Remove legacy_mode_p check. + +2022-07-12 Richard Sandiford <richard.sandiford@arm.com> + + PR target/106253 + * predict.h (insn_optimization_type): Declare. + * predict.cc (insn_optimization_type): New function. + * internal-fn.def (IFN_ICEIL, IFN_IFLOOR, IFN_IRINT, IFN_IROUND) + (IFN_LCEIL, IFN_LFLOOR, IFN_LRINT, IFN_LROUND, IFN_LLCEIL) + (IFN_LLFLOOR, IFN_LLRINT, IFN_LLROUND): New internal functions. + * internal-fn.cc (unary_convert_direct): New macro. + (expand_convert_optab_fn): New function. + (expand_unary_convert_optab_fn): New macro. + (direct_unary_convert_optab_supported_p): Likewise. + * optabs.cc (expand_sfix_optab): Pass insn_optimization_type to + convert_optab_handler. + * config/aarch64/aarch64-protos.h + (aarch64_builtin_vectorized_function): Delete. + * config/aarch64/aarch64-builtins.cc + (aarch64_builtin_vectorized_function): Delete. + * config/aarch64/aarch64.cc + (TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Delete. + * config/i386/i386.cc (ix86_optab_supported_p): Handle lround_optab. + * config/i386/i386.md (lround<X87MODEF:mode><SWI248x:mode>2): Remove + optimize_insn_for_size_p test. + +2022-07-12 Richard Biener <rguenther@suse.de> + + * tree-vect-loop-manip.cc (create_lcssa_for_virtual_phi): + Remove. + (vect_do_peeling): Do not call it, adjust comment. + +2022-07-12 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-builtins.cc + (aarch64_builtin_vectorized_function): Remove handling of + floor, ceil, trunc, round, nearbyint, sqrt, clz and ctz. + +2022-07-11 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/106234 + * gimple-range-cache.cc (ranger_cache::range_from_dom): Check dominator + cache value before recursively resolving it. + +2022-07-11 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/i386-features.h (scalar_chain): Add fields + insns_conv, n_sse_to_integer and n_integer_to_sse to this + parent class, moved from general_scalar_chain. + (scalar_chain::convert_compare): Protected method moved + from general_scalar_chain. + (mark_dual_mode_def): Make protected, not private virtual. + (scalar_chain:convert_op): New private virtual method. + (general_scalar_chain::general_scalar_chain): Simplify constructor. + (general_scalar_chain::~general_scalar_chain): Delete destructor. + (general_scalar_chain): Move insns_conv, n_sse_to_integer and + n_integer_to_sse fields to parent class, scalar_chain. + (general_scalar_chain::mark_dual_mode_def): Delete prototype. + (general_scalar_chain::convert_compare): Delete prototype. + (timode_scalar_chain::compute_convert_gain): Remove simplistic + implementation, convert to a method prototype. + (timode_scalar_chain::mark_dual_mode_def): Delete prototype. + (timode_scalar_chain::convert_op): Prototype new virtual method. + * config/i386/i386-features.cc (scalar_chain::scalar_chain): + Allocate insns_conv and initialize n_sse_to_integer and + n_integer_to_sse fields in constructor. + (scalar_chain::scalar_chain): Free insns_conv in destructor. + (general_scalar_chain::general_scalar_chain): Delete + constructor, now defined in the class declaration. + (general_scalar_chain::~general_scalar_chain): Delete destructor. + (scalar_chain::mark_dual_mode_def): Renamed from + general_scalar_chain::mark_dual_mode_def. + (timode_scalar_chain::mark_dual_mode_def): Delete. + (scalar_chain::convert_compare): Renamed from + general_scalar_chain::convert_compare. + (timode_scalar_chain::compute_convert_gain): New method to + determine the gain from converting a TImode chain to V1TImode. + (timode_scalar_chain::convert_op): New method to convert an + operand from TImode to V1TImode. + (timode_scalar_chain::convert_insn) <case REG>: Only PUT_MODE + on REG_EQUAL notes that were originally TImode (not CONST_INT). + Handle AND, ANDN, XOR, IOR, NOT and COMPARE. + (timode_mem_p): Helper predicate to check where operand is + memory reference with sufficient alignment for TImode STV. + (timode_scalar_to_vector_candidate_p): Use convertible_comparison_p + to check whether COMPARE is convertible. Handle SET_DESTs that + that are REG_P or MEM_P and SET_SRCs that are REG, CONST_INT, + CONST_WIDE_INT, MEM, AND, ANDN, IOR, XOR or NOT. + +2022-07-11 Richard Sandiford <richard.sandiford@arm.com> + + PR tree-optimization/106250 + * tree-vect-loop.cc (vectorizable_reduction): Reinstate final + argument to directly_supported_p. + +2022-07-11 Richard Biener <rguenther@suse.de> + + * tree-into-ssa.cc (update_ssa): Do not forcefully + re-compute dominance fast queries for TODO_update_ssa_no_phi. + +2022-07-11 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106228 + * tree-vect-data-refs.cc (vect_setup_realignment): Adjust + VUSE compute for the non-loop case. + +2022-07-11 Richard Biener <rguenther@suse.de> + + * tree-into-ssa.cc (rewrite_mode::REWRITE_UPDATE_REGION): New. + (rewrite_update_dom_walker::rewrite_update_dom_walker): Update. + (rewrite_update_dom_walker::m_in_region_flag): New. + (rewrite_update_dom_walker::before_dom_children): If the region + to update is marked, STOP at exits. + (rewrite_blocks): For REWRITE_UPDATE_REGION mark the region + to be updated. + (dump_update_ssa): Use bitmap_empty_p. + (update_ssa): Likewise. Use REWRITE_UPDATE_REGION when + TODO_update_ssa_no_phi. + * tree-cfgcleanup.cc (cleanup_tree_cfg_noloop): Account + pending update_ssa to the caller. + +2022-07-11 Richard Biener <rguenthert@suse.de> + + PR target/105459 + * config/i386/i386-options.cc (ix86_set_current_function): + Rebuild the target optimization node whenever necessary, + not only when the optimization node didn't change. + +2022-07-11 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106228 + * tree-vect-data-refs.cc (vect_setup_realignment): Properly + set a VUSE operand on the emitted load. + +2022-07-11 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range.cc (gimple_ranger::export_global_ranges): Remove + verification against legacy value_range. + (gimple_ranger::register_inferred_ranges): Same. + (gimple_ranger::export_global_ranges): Rename update_global_range + to set_range_info. + * tree-core.h (struct range_info_def): Remove. + (struct irange_storage_slot): New. + (struct tree_base): Remove SSA_NAME_ANTI_RANGE_P documentation. + (struct tree_ssa_name): Add vrange_storage support. + * tree-ssanames.cc (range_info_p): New. + (range_info_fits_p): New. + (range_info_alloc): New. + (range_info_free): New. + (range_info_get_range): New. + (range_info_set_range): New. + (set_range_info_raw): Remove. + (set_range_info): Adjust to use vrange_storage. + (set_nonzero_bits): Same. + (get_nonzero_bits): Same. + (duplicate_ssa_name_range_info): Remove overload taking + value_range_kind. + Rewrite tree overload to use vrange_storage. + (duplicate_ssa_name_fn): Adjust to use vrange_storage. + * tree-ssanames.h (struct range_info_def): Remove. + (set_range_info): Adjust prototype to take vrange. + * tree-vrp.cc (vrp_asserts::remove_range_assertions): Call + duplicate_ssa_name_range_info. + * tree.h (SSA_NAME_ANTI_RANGE_P): Remove. + (SSA_NAME_RANGE_TYPE): Remove. + * value-query.cc (get_ssa_name_range_info): Adjust to use + vrange_storage. + (update_global_range): Remove. + (get_range_global): Remove as_a<irange>. + * value-query.h (update_global_range): Remove. + * tree-ssa-dom.cc (set_global_ranges_from_unreachable_edges): + Rename update_global_range to set_range_info. + * value-range-storage.cc (vrange_storage::alloc_slot): Remove + gcc_unreachable. + +2022-07-10 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (irange::operator=): Call verify_range. + (irange::irange_set): Normalize kind after everything else has + been set. + (irange::irange_set_anti_range): Same. + (irange::set): Same. + (irange::verify_range): Disallow nonzero masks for VARYING. + (irange::irange_union): Call verify_range. + Handle nonzero masks better. + (irange::irange_intersect): Same. + (irange::set_nonzero_bits): Calculate mask if either range has an + explicit mask. + (irange::intersect_nonzero_bits): Same. + (irange::union_nonzero_bits): Same. + (range_tests_nonzero_bits): New. + (range_tests): Call range_tests_nonzero_bits. + * value-range.h (class irange): Remove set_nonzero_bits method + with trees. + (irange::varying_compatible_p): Set nonzero mask. + +2022-07-10 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/loongarch.md (<any_div>di3_fake): Describe + the sign-extend of result in the RTL template. + (<any_div><mode>3): Adjust for <any_div>di3_fake change. + +2022-07-10 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/loongarch.cc (loongarch_check_zero_div_p): + Remove static, for use in the machine description file. + * config/loongarch/loongarch-protos.h: + (loongarch_check_zero_div_p): Add prototype. + * config/loongarch/loongarch.md (enabled): New attr. + (*<optab><mode>3): Add (=r,r,r) and (=&r,0,r) alternatives for + idiv. Conditionally enable the alternatives using + loongarch_check_zero_div_p. + (<optab>di3_fake): Likewise. + +2022-07-10 Xi Ruoyao <xry111@xry111.site> + + * config/loongarch/loongarch.md (mulsidi3_64bit): Use mulw.d.w + instead of mul.d. + +2022-07-09 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (irange::irange_single_pair_union): Set + VR_VARYING when appropriate. + +2022-07-09 Vit Kabele <vit.kabele@sysgo.com> + + * stor-layout.cc (finalize_record_size): Extend warning message. + +2022-07-09 Sam Feifer <sfeifer@redhat.com> + + PR tree-optimization/98304 + * match.pd (n - (((n > C1) ? n : C1) & -C2)): New simplification. + +2022-07-09 Jeff Law <jeffreyalaw@gmail.com> + + * expr.cc (store_expr): Identify trailing NULs in a STRING_CST + initializer and use clear_storage rather than copying the + NULs to the destination array. + +2022-07-09 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/i386.md (define_peephole2): Use match_operand of + flags_reg_operand to capture and preserve the mode of FLAGS_REG. + (define_peephole2): Likewise. + (define_peephole2): Likewise... + +2022-07-09 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/i386-features.cc (convert_compare): Add support + for *testdi_not_doubleword pattern, "(compare (and (not ...)))" + by generating a pandn followed by ptest. + (convertible_comparison_p): Recognize both *cmpdi_doubleword and + recent *testdi_not_doubleword comparison patterns. + +2022-07-09 Tamar Christina <tamar.christina@arm.com> + + * config/s390/s390.cc (s390_expand_atomic): Pass false to store_bit_field to + indicate that the value is not undefined. + +2022-07-09 Andrew Pinski <apinski@marvell.com> + + PR tree-optimization/106087 + * tree-ssa-dce.cc (simple_dce_from_worklist): Check + to make sure the statement is only defining one operand. + +2022-07-08 Lewis Hyatt <lhyatt@gmail.com> + + PR preprocessor/91733 + * input.cc (find_end_of_line): New helper function. + (file_cache_slot::get_next_line): Recognize \r as a line ending. + * diagnostic-show-locus.cc (test_escaping_bytes_1): Adapt selftest + since \r will now be interpreted as a line-ending. + +2022-07-08 Martin Liska <mliska@suse.cz> + + PR sanitizer/106132 + * opts.cc (finish_options): Use 2 calls to + report_conflicting_sanitizer_options. + +2022-07-08 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106226 + * tree-vect-loop-manip.cc (vect_do_peeling): Assert that + no SSA update is needed. Move virtual SSA update ... + * tree-vectorizer.cc (pass_vectorize::execute): ... here, + via forced virtual renaming when TODO_update_ssa_only_virtuals + is queued. + (vect_transform_loops): Return TODO_update_ssa_only_virtuals + when virtual SSA update is required. + (try_vectorize_loop_1): Adjust. + * tree-vect-stmts.cc (vectorizable_simd_clone_call): Allow + virtual renaming if the ABI forces an aggregate return + but the original call did not have a virtual definition. + +2022-07-08 Martin Liska <mliska@suse.cz> + + * toplev.cc (init_asm_output): Do not init asm_out_file. + +2022-07-08 Tamar Christina <tamar.christina@arm.com> + + PR tree-optimization/106063 + * match.pd: Do not apply pattern after veclower is not supported. + +2022-07-08 Thomas Schwinge <thomas@codesourcery.com> + + * lto-cgraph.cc (input_offload_tables) <LTO_symtab_edge>: Correct + 'fn2' computation. + +2022-07-08 Tamar Christina <tamar.christina@arm.com> + + * expmed.cc (store_bit_field_1): Add parameter that indicates if value is + still undefined and if so emit a subreg move instead. + (store_integral_bit_field): Likewise. + (store_bit_field): Likewise. + * expr.h (write_complex_part): Likewise. + * expmed.h (store_bit_field): Add new parameter. + * builtins.cc (expand_ifn_atomic_compare_exchange_into_call): Use new + parameter. + (expand_ifn_atomic_compare_exchange): Likewise. + * calls.cc (store_unaligned_arguments_into_pseudos): Likewise. + * emit-rtl.cc (validate_subreg): Likewise. + * expr.cc (emit_group_store): Likewise. + (copy_blkmode_from_reg): Likewise. + (copy_blkmode_to_reg): Likewise. + (clear_storage_hints): Likewise. + (write_complex_part): Likewise. + (emit_move_complex_parts): Likewise. + (expand_assignment): Likewise. + (store_expr): Likewise. + (store_field): Likewise. + (expand_expr_real_2): Likewise. + * ifcvt.cc (noce_emit_move_insn): Likewise. + * internal-fn.cc (expand_arith_set_overflow): Likewise. + (expand_arith_overflow_result_store): Likewise. + (expand_addsub_overflow): Likewise. + (expand_neg_overflow): Likewise. + (expand_mul_overflow): Likewise. + (expand_arith_overflow): Likewise. + +2022-07-08 Haochen Jiang <haochen.jiang@intel.com> + + PR target/106180 + * config/i386/sse.md (sse2_cvtps2pd<mask_name>_1): + Rename from *sse2_cvtps2pd<mask_name>_1. + (vec_unpacks_lo_v4sf): Add handler for memory operand. + +2022-07-08 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/loongarch.cc (loongarch_compute_frame_info): + Modify fp_sp_offset and gp_sp_offset's calculation method, + when frame->mask or frame->fmask is zero, don't minus UNITS_PER_WORD + or UNITS_PER_FP_REG. + +2022-07-07 David Malcolm <dmalcolm@redhat.com> + + * diagnostic-format-json.cc (json_from_location_range): Update for + removal of label_text::maybe_free in favor of automatic memory + management. + * diagnostic-format-sarif.cc + (sarif_builder::make_location_object): Likewise. + * diagnostic-show-locus.cc (struct pod_label_text): New. + (class line_label): Convert m_text from label_text to pod_label_text. + (layout::print_any_labels): Move "text" to the line_label. + * tree-diagnostic-path.cc (path_label::get_text): Update for + removal of label_text::maybe_free in favor of automatic memory + management. + (event_range::print): Likewise. + (default_tree_diagnostic_path_printer): Likewise. + (default_tree_make_json_for_path): Likewise. + +2022-07-07 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> + + * statistics.cc (get_function_name): Add check to see if fn is not NULL. + +2022-07-07 Richard Biener <rguenther@suse.de> + + * tree-into-ssa.cc (iterating_old_ssa_names): New. + (add_new_name_mapping): Grow {new,old}_ssa_names separately + and only when actually needed. Assert we are not growing + the old_ssa_names set when iterating over it. + (update_ssa): Remove old_ssa_names copying and empty_p + query, note we are iterating over it and expect no set changes. + +2022-07-07 Thomas Schwinge <thomas@codesourcery.com> + + * config/i386/intelmic-mkoffload.cc (generate_host_descr_file) + (prepare_target_image, main): Handle OpenMP 'requires'. + (generate_host_descr_file): Switch to 'GOMP_offload_register_ver', + 'GOMP_offload_unregister_ver'. + +2022-07-07 Richard Biener <rguenther@suse.de> + + PR target/106219 + * config/i386/i386-builtins.cc (ix86_add_new_builtins): Properly + set DECL_PURE_P. + +2022-07-07 Richard Biener <rguenther@suse.de> + + * tree-ssa-loop-manip.cc (add_exit_phis_var): Return the + number of LC PHIs inserted. + (add_exit_phis): Return whether any variable required + multiple LC PHI nodes. + (rewrite_into_loop_closed_ssa_1): Use TODO_update_ssa_no_phi + when possible. + +2022-07-07 Richard Biener <rguenther@suse.de> + + * tree-ssa-loop-manip.cc (compute_live_loop_exits): Take + the def loop exit block bitmap as argument instead of + re-computing it here. + (add_exit_phis_var): Adjust. + (loop_name_cmp): New function. + (add_exit_phis): Sort variables to insert LC PHI nodes + after definition loop, for each definition loop compute + the exit block bitmap once. + (get_loops_exit): Remove. + (rewrite_into_loop_closed_ssa_1): Do not pre-record + all loop exit blocks into bitmaps. Record loop exits + if required. + +2022-07-07 Dimitrije Milosevic <Dimitrije.Milosevic@Syrmia.com> + + * config/mips/mips.cc (mips_asan_shadow_offset): Reformat + to handle the N32 ABI. + * config/mips/mips.h (SUBTARGET_SHADOW_OFFSET): Remove + the macro, as it is not needed anymore. + +2022-07-06 Thomas Schwinge <thomas@codesourcery.com> + + * config/gcn/mkoffload.cc (process_obj): Clarify 'target_data' -> + '[...]_data'. + * config/nvptx/mkoffload.cc (process): Likewise. + +2022-07-06 Thomas Schwinge <thomas@codesourcery.com> + + * omp-general.h (enum omp_requires): Use 'GOMP_REQUIRES_[...]'. + +2022-07-05 Andrew MacLeod <amacleod@redhat.com> + + * value-relation.cc (relation_to_code): New vector. + (relation_oracle::validate_relation): New. + (set_relation): Allow ssa1 == ssa2 to be registered. + * value-relation.h (validate_relation): New prototype. + (query_relation): Make internal variant protected. + +2022-07-05 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/i386.cc (ix86_rtx_costs) <COMPARE>: Provide costs + for double word comparisons and tests (comparisons against zero). + * config/i386/i386.md (*test<mode>_not_doubleword): Split DWI + and;cmp into andn;cmp $0 as a pre-reload splitter. + (*andn<dwi>3_doubleword_bmi): Use <dwi> instead of <mode> in name. + (*<any_or><dwi>3_doubleword): Likewise. + +2022-07-05 Roger Sayle <roger@nextmovesoftware.com> + Hongtao Liu <hongtao.liu@intel.com> + + * config/i386/i386-builtin.def (__builtin_ia32_palignr128): Change + CODE_FOR_ssse3_palignrti to CODE_FOR_ssse3_palignrv1ti. + * config/i386/i386-expand.cc (expand_vec_perm_palignr): Use V1TImode + and gen_ssse3_palignv1ti instead of TImode. + * config/i386/sse.md (SSESCALARMODE): Delete. + (define_mode_attr ssse3_avx2): Handle V1TImode instead of TImode. + (<ssse3_avx2>_palignr<mode>): Use VIMAX_AVX2_AVX512BW as a mode + iterator instead of SSESCALARMODE. + (ssse3_palignrdi): Optimize cases where operands[3] is 0 or 64, + using a single move instruction (if required). + +2022-07-05 Roger Sayle <roger@nextmovesoftware.com> + Uroš Bizjak <ubizjak@gmail.com> + + PR rtl-optimization/96692 + * config/i386/i386.md (define_split): Split ((A | B) ^ C) ^ D + as (X & ~Y) ^ Z on target BMI when either C or D is A or B. + +2022-07-05 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106198 + * tree-cfgcleanup.cc (repair_loop_structures): Always do a + full LC SSA rewrite but only if any blocks changed loop + depth. + +2022-07-05 Richard Biener <rguenther@suse.de> + + * tree-ssa-loop-manip.cc (find_uses_to_rename_def): Remove. + (find_uses_to_rename_in_loop): Likewise. + (rewrite_into_loop_closed_ssa_1): Remove loop parameter and + uses. + (rewrite_into_loop_closed_ssa): Adjust. + +2022-07-05 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106186 + * tree-ssa-propagate.cc (clean_up_loop_closed_phi): + Properly handle virtual PHI nodes. + +2022-07-05 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106196 + * tree-vect-stmts.cc (vect_finish_stmt_generation): Properly + handle aggregate returns of calls for VDEF updates. + +2022-07-05 Richard Biener <rguenther@suse.de> + + * tree-vect-loop-manip.cc (vect_set_loop_condition_normal): + Maintain LC SSA. + +2022-07-05 Richard Sandiford <richard.sandiford@arm.com> + + * tree-vect-patterns.cc (vect_convert_input): Expect the input + type to be signed for optab_vector_mixed_sign. Update the vectype + at the same time as type. + (vect_recog_dot_prod_pattern): Update accordingly. If usdot isn't + available, try sdot instead. + * tree-vect-loop.cc (vect_is_emulated_mixed_dot_prod): New function. + (vect_model_reduction_cost): Model the cost of implementing usdot + using sdot. + (vectorizable_reduction): Likewise. Skip target support test + for lane reductions. + (vect_emulate_mixed_dot_prod): New function. + (vect_transform_reduction): Use it to emulate usdot via sdot. + +2022-07-05 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106182 + * loop-init.cc (fix_loop_structure): Return the number + of newly discovered plus the number of deleted loops. + * tree-cfgcleanup.cc (repair_loop_structures): Adjust + variable name. + +2022-07-04 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-fold.cc + (fold_using_range::range_of_ssa_name_with_loop_info): Restrict the + call to SCEV for irange supported types. + (fold_using_range::range_of_builtin_int_call): Convert to vrange. + * gimple-range.cc (gimple_ranger::prefill_stmt_dependencies): Same. + * tree-ssa-dom.cc (cprop_operand): Same. + +2022-07-04 Roger Sayle <roger@nextmovesoftware.com> + + PR target/104489 + * calls.cc (precompute_register_parameters): Allow promotion + of floating point values to be passed in wider integer modes + by calling new convert_float_to_wider_int. + (expand_call): Allow floating point results to be returned in + wider integer modes by calling new convert wider_int_to_float. + * cfgexpand.cc (expand_value_return): Allow backends to promote + a scalar floating point return value to a wider integer mode + by calling new convert_float_to_wider_int. + * expr.cc (convert_float_to_wider_int): New function. + (convert_wider_int_to_float): Likewise. + (expand_expr_real_1) <expand_decl_rtl>: Allow backends to promote + scalar FP PARM_DECLs to wider integer modes, by calling new + convert_wider_int_to_float. + * expr.h (convert_modes): Name arguments for improved documentation. + (convert_float_to_wider_int): Prototype new function here. + (convert_wider_int_to_float): Likewise. + * function.cc (assign_parm_setup_stack): Allow floating point + values to be passed on the stack as wider integer modes by + calling new convert_wider_int_to_float. + +2022-07-04 Martin Jambor <mjambor@suse.cz> + + PR tree-optimization/105860 + * tree-sra.cc (build_reconstructed_reference): Start expr + traversal only just below the outermost union. + +2022-07-04 Richard Biener <rguenther@suse.de> + + * tree-vect-loop-manip.cc (vect_do_peeling): Revert assert + and update virtual SSA form again. Assert we do so for + a known set of transforms only. + * tree-vectorizer.h (vec_info::any_known_not_updated_vssa): New. + * tree-vect-stmts.cc (vectorizable_load): When vectorizing + using load-lanes allow virtual SSA update. + +2022-07-04 Tobias Burnus <tobias@codesourcery.com> + Chung-Lin Tang <cltang@codesourcery.com> + Thomas Schwinge <thomas@codesourcery.com> + + * config/gcn/mkoffload.cc (process_asm): Write '#include <stdint.h>'. + (process_obj): Pass omp_requires_mask to GOMP_offload_register_ver. + (main): Ask lto1 to obtain omp_requires_mask and pass it on. + * config/nvptx/mkoffload.cc (process, main): Likewise. + * lto-cgraph.cc (omp_requires_to_name): New. + (input_offload_tables): Save omp_requires_mask. + (output_offload_tables): Read it, check for consistency, + save value for mkoffload. + * omp-low.cc (lower_omp_target): Force output_offloadtables + call for OMP_REQUIRES_TARGET_USED. + +2022-07-04 Richard Biener <rguenther@suse.de> + + * tree-vect-loop-manip.cc (vect_do_peeling): Assert that + no SSA update is needed instead of updating virtual SSA + form. + * tree-vect-stmts.cc (vectorizable_load): For hoisted + invariant load use the loop entry virtual use. + For emulated gather loads use the virtual use of the + original stmt like vect_finish_stmt_generation would do. + +2022-07-04 Eric Botcazou <ebotcazou@adacore.com> + + * tree-pretty-print.cc (dump_generic_node) <ARRAY_TYPE>: Add guard + for direct circularity. + +2022-07-04 Eric Botcazou <ebotcazou@adacore.com> + + * dwarf2out.cc (gen_array_type_die): Use the default lower bound of + the language for vector types. + +2022-07-04 Aldy Hernandez <aldyh@redhat.com> + + * value-range-storage.cc (irange_storage_slot::set_irange): Set + nonzero bits in irange. + (irange_storage_slot::get_irange): Get nonzero bits from irange. + * value-range.cc (irange::operator=): Set nonzero bits. + (irange::irange_set): Same. + (irange::irange_set_anti_range): Same. + (irange::set): Same. + (irange::verify_range): Same. + (irange::legacy_equal_p): Check nonzero bits. + (irange::equal_p): Same. + (irange::contains_p): Handle nonzero bits. + (irange::irange_union): Same. + (irange::irange_intersect): Same. + (irange::dump): Same. + (irange::set_nonzero_bits): New. + (irange::get_nonzero_bits): New. + (irange::intersect_nonzero_bits): New. + (irange::union_nonzero_bits): New. + (irange::dump_bitmasks): New. + * value-range.h (class irange): Add m_nonzero_mask. + (gt_ggc_mx): Handle nonzero bits. + (gt_pch_nx): Same. + (irange::set_undefined): Set nonzero bits. + (irange::set_varying): Same. + (irange::normalize_kind): Call set_undefined. + +2022-07-04 Richard Biener <rguenther@suse.de> + + * tree-ssa-loop-manip.h + (rewrite_virtuals_into_loop_closed_ssa): Remove. + (rewrite_into_loop_closed_ssa_1): Likewise. + * tree-ssa-loop-manip.cc (rewrite_into_loop_closed_ssa_1): + Make static. + (rewrite_into_loop_closed_ssa): Remove loop overload, + always rewrite virtuals into LC SSA. + (check_loop_closed_ssa_bb): Also check virtuals. + * tree-ssa-dce.cc (remove_dead_phis): Preserve virtual + LC PHIs when in LC SSA. + * gimple-loop-jam.cc (fuse_loops): Do not rewrite into + loop-closed SSA here, but ... + (tree_loop_unroll_and_jam): ... here once. + * tree-if-conv.cc (version_loop_for_if_conversion): Use + the cheaper TODO_update_ssa_no_phi. + * tree-loop-distribution.cc (version_loop_by_alias_check): + Likewise. + * tree-ssa-loop-unswitch.cc (tree_unswitch_single_loop): + Likewise. + * tree-vect-loop-manip.cc (vect_loop_versioning): Likewise. + (tree_unswitch_outer_loop): Do not rewrite virtuals into + LC ssa. + * tree-parloops.cc (transform_to_exit_first_loop_alt): + Likewise. + (pass_parallelize_loops::execute): After finishing rewrite + into LC SSA again because we do not maintain it properly. + +2022-07-04 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106055 + * graphite.cc (canonicalize_loop_closed_ssa): Check whether + we can propagate. + +2022-07-04 Haochen Jiang <haochen.jiang@intel.com> + + PR target/43618 + * config/i386/sse.md (extendv2sfv2df2): New define_expand. + (sse2_cvtps2pd_<mask_name>): Change constraint of operands[1]. + (*sse2_cvtps2pd_<mask_name>_1): Rename from extendvsdfv2df2. + +2022-07-04 Aldy Hernandez <aldyh@redhat.com> + + * ipa-cp.cc (ipcp_vr_lattice::meet_with_1): Use operator!=. + * ipa-prop.cc (struct ipa_vr_ggc_hash_traits): Same. + * tree-ssa-loop-unswitch.cc (struct unswitch_predicate): Use set + with two arguments. + (find_unswitching_predicates_for_bb): Same. + * tree-vrp.cc (range_fold_unary_symbolics_p): Same. + * value-range-equiv.cc (value_range_equiv::equal_p): Use operator==. + * value-range.cc (irange::equal_p): Rename to... + (irange::operator==): ...this. + * value-range.h (irange::set): Remove. + (irange::operator==): Remove. + (irange::set_zero): Use set with two arguments. + * vr-values.cc (vr_values::extract_range_from_binary_expr): Same. + (vr_values::extract_range_from_unary_expr): Same. + (check_for_binary_op_overflow): Same. + (bounds_of_var_in_loop): Same. + +2022-07-03 H.J. Lu <hjl.tools@gmail.com> + + PR target/106022 + * config/i386/i386-protos.h (ix86_convert_const_vector_to_integer): + New. + * config/i386/i386.cc (ix86_convert_const_vector_to_integer): + New. + * config/i386/mmx.md (V_16_32_64): New. + (*mov<mode>_imm): New patterns for stores with 16-bit, 32-bit + and 64-bit constant vector. + * config/i386/predicates.md (x86_64_const_vector_operand): New. + +2022-07-03 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-cache.cc: Include value-range-storage.h. + * gimple-range-cache.h (class block_range_cache): Add "class" to + m_range_allocator. + * gimple-range-edge.cc + (gimple_outgoing_range::gimple_outgoing_range): Allocate allocator. + (gimple_outgoing_range::~gimple_outgoing_range): Free allocator. + (gimple_outgoing_range::calc_switch_ranges): Dereference allocator. + * gimple-range-edge.h: Add "class" to m_range_allocator. + * gimple-range-infer.cc + (infer_range_manager::infer_range_manager): Allocate allocator. + (infer_range_manager::~infer_range_manager): Free allocator. + (infer_range_manager::get_nonzero): Dereference allocator. + (infer_range_manager::add_range): Same. + * gimple-range-infer.h (class vrange_allocator): Add "class" to + m_range_allocator. + * value-range-storage.h (class vrange_allocator): Move from + value-range.h. + (class obstack_vrange_allocator): Same. + (class ggc_vrange_allocator): Same. + (vrange_allocator::alloc_vrange): Same. + (vrange_allocator::alloc_irange): Same. + * value-range.h (class vrange_allocator): Move to value-range-storage.h. + (class obstack_vrange_allocator): Same. + (class ggc_vrange_allocator): Same. + +2022-07-03 Aldy Hernandez <aldyh@redhat.com> + + * Makefile.in (OBJS): Add value-range-storage.o. + (GTFILES): Add value-range-storage.h. + * gengtype.cc (open_base_files): Add value-range-storage.h. + * value-range-storage.cc: New file. + * value-range-storage.h: New file. + +2022-07-03 Xi Ruoyao <xry111@xry111.site> + Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/loongarch.cc (loongarch_check_zero_div_p): + New static function. + (loongarch_idiv_insns): Use loongarch_check_zero_div_p instead + of TARGET_CHECK_ZERO_DIV. + (loongarch_output_division): Likewise. + * common/config/loongarch/loongarch-common.cc + (TARGET_DEFAULT_TARGET_FLAGS): Remove unneeded hook. + * doc/invoke.texi: Update to match the new behavior. + +2022-07-03 Ian Lance Taylor <iant@golang.org> + + * tree-ssa-dse.cc (dse_optimize_stmt): Only delete a trapping + statement if -fdelete-dead-exceptions. + +2022-07-02 Tim Lange <mail@tim-lange.me> + + PR analyzer/105900 + * doc/invoke.texi: Added Wanalyzer-allocation-size. + +2022-07-02 Immad Mir <mirimmad17@gmail.com> + + PR analyzer/106003 + * Makefile.in (ANALYZER_OBJS): Add sm-fd.o. + * doc/invoke.texi: Add -Wanalyzer-fd-double-close, -Wanalyzer-fd-leak, + -Wanalyzer-fd-access-mode-mismatch, -Wanalyzer-fd-use-without-check, + -Wanalyzer-fd-use-after-close. + +2022-07-01 Aldy Hernandez <aldyh@redhat.com> + + * wide-int.h (struct trailing_wide_ints): Add m_num_elements. + (trailing_wide_ints::set_precision): Add num_elements argument. + (trailing_wide_ints::extra_size): Same. + +2022-07-01 Uroš Bizjak <ubizjak@gmail.com> + + * config/i386/i386.md (*andn<mode>3_doubleword_bmi): + Use "r" constraint for operand 1. + +2022-07-01 Richard Biener <rguenther@suse.de> + + * tree-into-ssa.cc (rewrite_update_dom_walker::before_dom_children): + Do not look at interesting_blocks which is a copy of + blocks_to_update. + (update_ssa): Do not initialize it. + (pass_build_ssa::execute): Set interesting_blocks to NULL + after releasing it. + +2022-07-01 Richard Biener <rguenther@suse.de> + + * tree-ssa-sccvn.cc (vn_reference_lookup_3): Revert + back to using maybe_ne (off, -1). + +2022-07-01 Richard Biener <rguenther@suse.de> + + * tree-ssa-sccvn.cc (vn_nary_op_insert_into): Make + checking dominance check conditional on flag_checking. + +2022-07-01 Tobias Burnus <tobias@codesourcery.com> + + * config/gcn/gcn-protos.h (print_operand_address): Remove register + keyword on 'rtx addr' argument. + +2022-07-01 Roger Sayle <roger@nextmovesoftware.com> + Uroš Bizjak <ubizjak@gmail.com> + + * config/i386/i386.md (*andn<mode>3_doubleword_bmi): Add constraints + to post-reload define_insn_and_split. + +2022-07-01 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/106144 + * wide-int.cc (wi::shifted_mask): If end >= prec, return right after + emitting element for shift or if shift is 0 first element after start. + (wide_int_cc_tests): Add tests for equivalency of wi::mask and + wi::shifted_mask with 0 start. + +2022-07-01 Roger Sayle <roger@nextmovesoftware.com> + + PR target/106122 + * config/i386/i386.md (peephole2): Avoid generating pop %esp + when optimizing for size. + +2022-07-01 Roger Sayle <roger@nextmovesoftware.com> + Uroš Bizjak <ubizjak@gmail.com> + + * config/i386/i386.md (general_szext_operand): Add TImode + support using x86_64_hilo_general_operand predicate. + (*cmp<dwi>_doubleword): Use x86_64_hilo_general_operand predicate. + (*add<dwi>3_doubleword): Improved optimization of zero addition. + (and<mode>3): Use SDWIM mode iterator to add support for double + word bit-wise AND in TImode. Use force_reg when double word + immediate operand isn't x86_64_hilo_general_operand. + (and<dwi>3_doubleword): Generalized from anddi3_doubleword and + converted into a post-reload splitter. + (*andndi3_doubleword): Previous define_insn deleted. + (*andn<mode>3_doubleword_bmi): New define_insn_and_split for + TARGET_BMI that splits post-reload. + (*andn<mode>3_doubleword): New define_insn_and_split for + !TARGET_BMI, that lowers/splits before reload. + (<any_or><mode>3): Use SDWIM mode iterator to add suppport for + double word bit-wise XOR and bit-wise IOR in TImode. Use + force_reg when double word immediate operand isn't + x86_64_hilo_general_operand. + (*<any_or>di3_doubleword): Generalized from <any_or>di3_doubleword. + (one_cmpl<mode>2): Use SDWIM mode iterator to add support for + double word bit-wise NOT in TImode. + (one_cmpl<dwi>2_doubleword): Generalize from one_cmpldi2_doubleword + and converted into a post-reload splitter. + +2022-07-01 Eric Botcazou <ebotcazou@adacore.com> + + PR middle-end/105874 + * expr.cc (expand_expr_real_1) <normal_inner_ref>: Force + EXPAND_MEMORY for the expansion of the inner reference only + in the usual cases where a memory reference is required. + +2022-07-01 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106131 + * tree-ssa-sccvn.cc (vn_reference_lookup_3): Force alias-set + zero when offsetting the read looking through an aggregate + copy. + +2022-07-01 Martin Liska <mliska@suse.cz> + + PR tree-optimization/106126 + * gimple-if-to-switch.cc (struct condition_info): Save + has_side_effect. + (find_conditions): Parse all BBs. + (pass_if_to_switch::execute): Allow only side effects for first + BB. + +2022-07-01 Haochen Jiang <haochen.jiang@intel.com> + + * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX512F_UNSET): + Add OPTION_MASK_ISA2_AVX512BW_UNSET, remove + OPTION_MASK_ISA2_AVX512BF16_UNSET and + OPTION_MASK_ISA2_AVX512FP16_UNSET. + +2022-06-30 Joseph Myers <joseph@codesourcery.com> + + PR lto/106129 + * lto-wrapper.cc (find_option): Add argument start. + (merge_and_complain): Loop over existing_opt_index and + existing_opt2_index for Xassembler check. Update calls to + find_option. + (find_and_merge_options): Add argument first to determine whether + to merge options with those passed in *opts. + (run_gcc): Update calls to find_and_merge_options. + +2022-06-30 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-cache.cc (block_range_cache::block_range_cache): + Rename vrange_allocator to obstack_vrange_allocator. + (ssa_global_cache::ssa_global_cache): Same. + * gimple-range-edge.h (class gimple_outgoing_range): Same. + * gimple-range-infer.h (class infer_range_manager): Same. + * value-range.h (class vrange_allocator): Make abstract. + (class obstack_vrange_allocator): Inherit from vrange_allocator. + (class ggc_vrange_allocator): New. + +2022-06-30 Roger Sayle <roger@nextmovesoftware.com> + Uroš Bizjak <ubizjak@gmail.com> + + * config/i386/i386.md (swap_mode): Rename from *swap<mode> to + provide gen_swapsi. + (<any_rotate>di3): Handle !TARGET_64BIT rotations by 32 bits + via new gen_<insn>32di2_doubleword below. + (<anyrotate>32di2_doubleword): New define_insn_and_split + that splits after reload as either a pair of move instructions + or an xchgl (using gen_swapsi). + +2022-06-30 Richard Biener <rguenther@suse.de> + + * domwalk.h (dom_walker::dom_walker): Update comment to + reflect reality and new special argument value for + bb_index_to_rpo. + * domwalk.cc (dom_walker::dom_walker): Recognize -1 + bb_index_to_rpo. + * tree-into-ssa.cc + (rewrite_update_dom_walker::rewrite_update_dom_walker): Tell + dom_walker to not use RPO. + +2022-06-30 Martin Liska <mliska@suse.cz> + + * tree-ssa-dom.cc (pass_dominator::execute): Remove m_ranger as + it is unused. + +2022-06-30 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/106114 + * gimple-range-fold.cc (fold_using_range::relation_fold_and_or): Check + statement operands instead of GORI cache. + +2022-06-30 Antoni Boucher <bouanto@zoho.com> + + PR target/106095 + * config/i386/sse.md: Fix asm generation. + +2022-06-29 Sergei Trofimovich <siarheit@google.com> + + PR c++/106102 + * system.h: Introduce INCLUDE_PTHREAD_H macros to include <pthread.h>. + +2022-06-29 Joseph Myers <joseph@codesourcery.com> + + * config/nios2/nios2.cc (nios2_load_pic_address): Use gen_rtx_MEM + not gen_const_mem for UNSPEC_PIC_CALL_SYM. + +2022-06-29 Richard Biener <rguenther@suse.de> + + PR rtl-optimization/106082 + * combine.cc (distribute_notes): Preserve notes when + they indicate a call doesn't perform a non-local goto. + +2022-06-29 Richard Biener <rguenther@suse.de> + + PR tree-optimization/106112 + * tree-ssa-sccvn.cc (valueized_wider_op): Properly extend + a constant operand according to its type. + +2022-06-29 Martin Liska <mliska@suse.cz> + + * doc/invoke.texi: Remove removed evrp-mode. + +2022-06-29 Lulu Cheng <chenglulu@loongson.cn> + + PR target/106097 + * config/loongarch/loongarch.cc (loongarch_build_integer): + Remove undefined behavior from code. + +2022-06-28 Dimitar Dimitrov <dimitar@dinux.eu> + + * doc/sourcebuild.texi: Document new no_alignment_constraints + effective target check. + +2022-06-28 Aldy Hernandez <aldyh@redhat.com> + + * Makefile.in: Remove gimple-ssa-evrp.o and gimple-ssa-evrp-analyze.o. + * flag-types.h (enum evrp_mode): Remove. + * params.opt: Remove --param=evrp-mode. + * tree-vrp.cc (make_pass_early_vrp): New. + (pass_vrp::execute): Call early VRP instance. + * gimple-ssa-evrp-analyze.cc: Removed. + * gimple-ssa-evrp-analyze.h: Removed. + * gimple-ssa-evrp.cc: Removed. + +2022-06-28 Alexandre Oliva <oliva@adacore.com> + + * Makefile.in (TFLAGS): New. + (GCC_FOR_TARGET): Add TFLAGS. + (FLAGS_TO_PASS): Pass TFLAGS down. + +2022-06-28 Richard Biener <rguenther@suse.de> + + * tree-ssa-loop-split.cc (fix_loop_bb_probability): Do not + call update_ssa. + +2022-06-28 Richard Biener <rguenther@suse.de> + + * tree-into-ssa.cc (insert_updated_phi_nodes_for): Use + mark_block_for_update. + (update_ssa): Adjust. + +2022-06-28 Xi Ruoyao <xry111@xry111.site> + + PR target/106096 + * config/loongarch/loongarch.h (REG_CLASS_CONTENTS): Exclude + $r13 from SIBCALL_REGS. + * config/loongarch/loongarch.cc (loongarch_regno_to_class): + Change $r13 to JIRL_REGS. + +2022-06-28 Aldy Hernandez <aldyh@redhat.com> + + * tree-ssa-loop-ch.cc (entry_loop_condition_is_static): Remove + irange::supports_p. + +2022-06-28 Richard Biener <rguenther@suse.de> + + PR middle-end/106053 + * match.pd ((T)a == (T)b): Avoid folding away sign + changes in a comparison if we'd truncate to a boolean. + +2022-06-28 Kewen Lin <linkw@linux.ibm.com> + + * config/rs6000/rs6000.md (*rotl<mode>3_insert_4): Replace mode + iterator GPR with SImode, adjust the condition and output template, + rename to ... + (*rotlsi3_insert_4): ... this. + +2022-06-27 David Malcolm <dmalcolm@redhat.com> + + * genmatch.cc: Add "final" and "override" to various vfunc + implementations, removing redundant "virtual" as appropriate. + * gensupport.cc: Likewise. + * gimple-range-cache.h: Likewise. + * ipa-icf-gimple.h: Likewise. + * ipa-icf.h: Likewise. + * read-md.h: Likewise. + * read-rtl-function.cc: Likewise. + * tree-ssa-loop-ch.cc: Likewise. + * tree-ssa-sccvn.cc: Likewise. + +2022-06-27 David Malcolm <dmalcolm@redhat.com> + + * config/i386/i386-features.h: Add "final" and "override" to + scalar_chain vfunc implementations as appropriate. + +2022-06-27 David Malcolm <dmalcolm@redhat.com> + + * tree-switch-conversion.h: Add "final" and "override" to cluster + vfunc implementations as appropriate. + +2022-06-27 David Malcolm <dmalcolm@redhat.com> + + * expr.cc: Add "final" and "override" to op_by_pieces_d vfunc + implementations as appropriate. + +2022-06-27 David Malcolm <dmalcolm@redhat.com> + + * compare-elim.cc: Add "final" and "override" to dom_walker vfunc + implementations, removing redundant "virtual" as appropriate. + * gimple-ssa-strength-reduction.cc: Likewise. + * ipa-prop.cc: Likewise. + * rtl-ssa/blocks.cc: Likewise. + * tree-into-ssa.cc: Likewise. + * tree-ssa-dom.cc: Likewise. + * tree-ssa-math-opts.cc: Likewise. + * tree-ssa-phiopt.cc: Likewise. + * tree-ssa-propagate.cc: Likewise. + * tree-ssa-sccvn.cc: Likewise. + * tree-ssa-strlen.cc: Likewise. + * tree-ssa-uncprop.cc: Likewise. + +2022-06-27 David Malcolm <dmalcolm@redhat.com> + + * adjust-alignment.cc: Add "final" and "override" to opt_pass + vfunc implementations, removing redundant "virtual" as + appropriate. + * asan.cc: Likewise. + * auto-inc-dec.cc: Likewise. + * auto-profile.cc: Likewise. + * bb-reorder.cc: Likewise. + * cfgcleanup.cc: Likewise. + * cfgexpand.cc: Likewise. + * cfgrtl.cc: Likewise. + * cgraphbuild.cc: Likewise. + * combine-stack-adj.cc: Likewise. + * combine.cc: Likewise. + * compare-elim.cc: Likewise. + * config/i386/i386-features.cc: Likewise. + * coroutine-passes.cc: Likewise. + * cprop.cc: Likewise. + * cse.cc: Likewise. + * dce.cc: Likewise. + * df-core.cc: Likewise. + * dse.cc: Likewise. + * dwarf2cfi.cc: Likewise. + * early-remat.cc: Likewise. + * except.cc: Likewise. + * final.cc: Likewise. + * function.cc: Likewise. + * fwprop.cc: Likewise. + * gcse.cc: Likewise. + * gimple-harden-conditionals.cc: Likewise. + * gimple-if-to-switch.cc: Likewise. + * gimple-isel.cc: Likewise. + * gimple-laddress.cc: Likewise. + * gimple-loop-interchange.cc: Likewise. + * gimple-loop-jam.cc: Likewise. + * gimple-loop-versioning.cc: Likewise. + * gimple-low.cc: Likewise. + * gimple-ssa-backprop.cc: Likewise. + * gimple-ssa-evrp.cc: Likewise. + * gimple-ssa-isolate-paths.cc: Likewise. + * gimple-ssa-nonnull-compare.cc: Likewise. + * gimple-ssa-split-paths.cc: Likewise. + * gimple-ssa-store-merging.cc: Likewise. + * gimple-ssa-strength-reduction.cc: Likewise. + * gimple-ssa-warn-access.cc: Likewise. + * gimple-ssa-warn-alloca.cc: Likewise. + * gimple-ssa-warn-restrict.cc: Likewise. + * gimple-warn-recursion.cc: Likewise. + * graphite.cc: Likewise. + * ifcvt.cc: Likewise. + * init-regs.cc: Likewise. + * ipa-comdats.cc: Likewise. + * ipa-cp.cc: Likewise. + * ipa-devirt.cc: Likewise. + * ipa-fnsummary.cc: Likewise. + * ipa-free-lang-data.cc: Likewise. + * ipa-icf.cc: Likewise. + * ipa-inline.cc: Likewise. + * ipa-modref.cc: Likewise. + * ipa-profile.cc: Likewise. + * ipa-pure-const.cc: Likewise. + * ipa-reference.cc: Likewise. + * ipa-split.cc: Likewise. + * ipa-sra.cc: Likewise. + * ipa-visibility.cc: Likewise. + * ipa.cc: Likewise. + * ira.cc: Likewise. + * jump.cc: Likewise. + * loop-init.cc: Likewise. + * lower-subreg.cc: Likewise. + * mode-switching.cc: Likewise. + * modulo-sched.cc: Likewise. + * multiple_target.cc: Likewise. + * omp-expand.cc: Likewise. + * omp-low.cc: Likewise. + * omp-oacc-kernels-decompose.cc: Likewise. + * omp-oacc-neuter-broadcast.cc: Likewise. + * omp-offload.cc: Likewise. + * omp-simd-clone.cc: Likewise. + * passes.cc: Likewise. + * postreload-gcse.cc: Likewise. + * postreload.cc: Likewise. + * predict.cc: Likewise. + * recog.cc: Likewise. + * ree.cc: Likewise. + * reg-stack.cc: Likewise. + * regcprop.cc: Likewise. + * reginfo.cc: Likewise. + * regrename.cc: Likewise. + * reorg.cc: Likewise. + * sancov.cc: Likewise. + * sanopt.cc: Likewise. + * sched-rgn.cc: Likewise. + * stack-ptr-mod.cc: Likewise. + * store-motion.cc: Likewise. + * tracer.cc: Likewise. + * trans-mem.cc: Likewise. + * tree-call-cdce.cc: Likewise. + * tree-cfg.cc: Likewise. + * tree-cfgcleanup.cc: Likewise. + * tree-complex.cc: Likewise. + * tree-eh.cc: Likewise. + * tree-emutls.cc: Likewise. + * tree-if-conv.cc: Likewise. + * tree-into-ssa.cc: Likewise. + * tree-loop-distribution.cc: Likewise. + * tree-nrv.cc: Likewise. + * tree-object-size.cc: Likewise. + * tree-parloops.cc: Likewise. + * tree-predcom.cc: Likewise. + * tree-profile.cc: Likewise. + * tree-sra.cc: Likewise. + * tree-ssa-ccp.cc: Likewise. + * tree-ssa-copy.cc: Likewise. + * tree-ssa-dce.cc: Likewise. + * tree-ssa-dom.cc: Likewise. + * tree-ssa-dse.cc: Likewise. + * tree-ssa-forwprop.cc: Likewise. + * tree-ssa-ifcombine.cc: Likewise. + * tree-ssa-loop-ch.cc: Likewise. + * tree-ssa-loop-im.cc: Likewise. + * tree-ssa-loop-ivcanon.cc: Likewise. + * tree-ssa-loop-prefetch.cc: Likewise. + * tree-ssa-loop-split.cc: Likewise. + * tree-ssa-loop-unswitch.cc: Likewise. + * tree-ssa-loop.cc: Likewise. + * tree-ssa-math-opts.cc: Likewise. + * tree-ssa-phiopt.cc: Likewise. + * tree-ssa-phiprop.cc: Likewise. + * tree-ssa-pre.cc: Likewise. + * tree-ssa-reassoc.cc: Likewise. + * tree-ssa-sccvn.cc: Likewise. + * tree-ssa-sink.cc: Likewise. + * tree-ssa-strlen.cc: Likewise. + * tree-ssa-structalias.cc: Likewise. + * tree-ssa-uncprop.cc: Likewise. + * tree-ssa-uninit.cc: Likewise. + * tree-ssanames.cc: Likewise. + * tree-stdarg.cc: Likewise. + * tree-switch-conversion.cc: Likewise. + * tree-tailcall.cc: Likewise. + * tree-vect-generic.cc: Likewise. + * tree-vectorizer.cc: Likewise. + * tree-vrp.cc: Likewise. + * tsan.cc: Likewise. + * ubsan.cc: Likewise. + * var-tracking.cc: Likewise. + * vtable-verify.cc: Likewise. + * web.cc: Likewise. + +2022-06-27 Andrew Stubbs <ams@codesourcery.com> + + * config/gcn/gcn.md (*movbi): Remove assembler bug workarounds. + (jump): Likewise. + (movdi_symbol_save_scc): Likewise. + +2022-06-27 Roger Sayle <roger@nextmovesoftware.com> + + PR rtl-optimization/7061 + * config/i386/i386.md (*highpartdisi2): New define_insn_and_split. + +2022-06-27 Roger Sayle <roger@nextmovesoftware.com> + + PR tree-optimization/94026 + * match.pd (((X << C1) & C2) eq/ne C3): New simplification. + (((X >> C1) & C2) eq/ne C3): Likewise. + +2022-06-27 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> + + * statistics.cc: Include tree.h. + (get_function_name): New function. + (statistics_fini_pass_2): Call get_function_name instead of + current_function_name. + (statistics_counter_event): Call get_function_name instead of + function_name. + (statistics_histogram_event): Likewise. + +2022-06-27 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md: + Suppress unnecessary emitting nop insn in the split patterns for + integer/FP constant synthesis, and add new peephole2 pattern that + folds such synthesized additions. + +2022-06-25 Aldy Hernandez <aldyh@redhat.com> + + * tree-ssa-dom.cc (dom_jt_state): Pass ranger to constructor + instead of evrp. + (dom_jt_state::push): Remove m_evrp. + (dom_jt_state::pop): Same. + (dom_jt_state::record_ranges_from_stmt): Remove. + (dom_jt_state::register_equiv): Remove updating of evrp ranges. + (class dom_jt_simplifier): Pass ranger to constructor. + Inherit from hybrid_jt_simplifier. + (dom_jt_simplifier::simplify): Convert to ranger. + (pass_dominator::execute): Same. + (all_uses_feed_or_dominated_by_stmt): New. + (dom_opt_dom_walker::set_global_ranges_from_unreachable_edges): New. + (dom_opt_dom_walker::before_dom_children): Call + set_global_ranges_from_unreachable_edges. + Do not call record_ranges_from_stmt. + (dom_opt_dom_walker::after_dom_children): Remove evrp use. + (cprop_operand): Use int_range<> instead of value_range. + (dom_opt_dom_walker::fold_cond): New. + (dom_opt_dom_walker::optimize_stmt): Pass ranger to + cprop_into_stmt. + Use fold_cond() instead of vrp_visit_cond_stmt(). + * tree-ssa-threadedge.cc (jt_state::register_equivs_stmt): Do not + pass state to simplifier. + * vr-values.h (class vr_values): Make fold_cond public. + +2022-06-25 Jeff Law <jeffreyalaw@gmail.com> + + * common/config/tilegx/tilegx-common.cc: Removed. + * common/config/tilepro/tilepro-common.cc: Removed. + * config.gcc: Remove tilegx and tilepro entries. + * config/tilegx/constraints.md: Removed. + * config/tilegx/feedback.h: Removed. + * config/tilegx/linux.h: Removed. + * config/tilegx/mul-tables.cc: Removed. + * config/tilegx/predicates.md: Removed. + * config/tilegx/sync.md: Removed. + * config/tilegx/t-tilegx: Removed. + * config/tilegx/tilegx-builtins.h: Removed. + * config/tilegx/tilegx-c.cc: Removed. + * config/tilegx/tilegx-generic.md: Removed. + * config/tilegx/tilegx-modes.def: Removed. + * config/tilegx/tilegx-multiply.h: Removed. + * config/tilegx/tilegx-opts.h: Removed. + * config/tilegx/tilegx-protos.h: Removed. + * config/tilegx/tilegx.cc: Removed. + * config/tilegx/tilegx.h: Removed. + * config/tilegx/tilegx.md: Removed. + * config/tilegx/tilegx.opt: Removed. + * config/tilepro/constraints.md: Removed. + * config/tilepro/feedback.h: Removed. + * config/tilepro/gen-mul-tables.cc: Removed. + * config/tilepro/linux.h: Removed. + * config/tilepro/mul-tables.cc: Removed. + * config/tilepro/predicates.md: Removed. + * config/tilepro/t-tilepro: Removed. + * config/tilepro/tilepro-builtins.h: Removed. + * config/tilepro/tilepro-c.cc: Removed. + * config/tilepro/tilepro-generic.md: Removed. + * config/tilepro/tilepro-modes.def: Removed. + * config/tilepro/tilepro-multiply.h: Removed. + * config/tilepro/tilepro-protos.h: Removed. + * config/tilepro/tilepro.cc: Removed. + * config/tilepro/tilepro.h: Removed. + * config/tilepro/tilepro.md: Removed. + * config/tilepro/tilepro.opt: Removed. + * configure.ac: Remove tilegx and tilepro entries. + * configure: Rebuilt. + * doc/extend.texi: Remove tilegx and tilepro entries. + * doc/install.texi: Remove tilegx and tilepro entries. + * doc/invoke.texi: Remove tilegx and tilepro entries. + * doc/md.texi: Remove tilegx and tilepro entries. + +2022-06-25 Roger Sayle <roger@nextmovesoftware.com> + Richard Biener <rguenther@suse.de> + + * regcprop.cc (pass_cprop_hardreg::execute): Perform a third + iteration over each basic block that was updated by the second + iteration. + +2022-06-24 Jason Merrill <jason@redhat.com> + + PR c++/87729 + PR c++/20423 + * doc/invoke.texi: Document changes. + +2022-06-24 Iain Buclaw <ibuclaw@gdcproject.org> + + * config/tilepro/gen-mul-tables.cc (tilegx_emit): Adjust loop + condition to avoid overflow. + +2022-06-24 Will Schmidt <will_schmidt@vnet.ibm.com> + + * config/rs6000/aix71.h (MASK_PPC_GPOPT, MASK_PPC_GFXOPT): Replace with + OPTION_MASK_PPC_GPOPT, OPTION_MASK_PPC_GFXOPT. + * config/rs6000/darwin.h (MASK_PPC_GFXOPT): Replace with + OPTION_MASK_PPC_GFXOPT. + * config/rs6000/darwin64-biarch.h (MASK_PPC_GFXOPT): Same. + * config/rs6000/default64.h (MASK_PPC_GPOPT, MASK_PPC_GFXOPT): Replace with + OPTION_MASK_PPC_GPOPT, OPTION_MASK_PPC_GFXOPT. + * config/rs6000/rs6000-c.cc: Update comment. + * config/rs6000/rs6000-cpus.def: Update RS6000_CPU macro calls. + * config/rs6000/rs6000.cc (rs6000_darwin_file_start): Replace + MASK_PPC_GPOPT with OPTION_MASK_PPC_GPOPT. + (rs6000_builtin_mask_names): Replace MASK_PPC_GFXOPT, MASK_POPCNTB + with OPTION_MASK_PPC_GFXOPT, OPTION_MASK_POPCNTB. + * config/rs6000/rs6000.h: (MASK_P8_VECTOR, MASK_P9_VECTOR, + MASK_P9_MISC, MASK_POPCNTB, MASK_POPCNTD, MASK_PPC_GFXOPT, + MASK_PPC_GPOPT, MASK_RECIP_PRECISION, MASK_SOFT_FLOAT, + MASK_VSX, MASK_POWER10, MASK_P10_FUSION): Delete. + +2022-06-24 Will Schmidt <will_schmidt@vnet.ibm.com> + + * config/rs6000/aix71.h (TARGET_DEFAULT): Replace MASK_MFCRF with + OPTION_MASK_MFCRF. + * config/rs6000/darwin.h (TARGET_DEFAULT): Replace MASK_MULTIPLE with + OPTION_MASK_MULTIPLE. + * config/rs6000/darwin64-biarch.h (TARGET_DEFAULT): Same. + * config/rs6000/default64.h (TARGET_DEFAULT): Replace MASK_MFCRF with + OPTION_MASK_MFCRF. + * config/rs6000/eabi.h (TARGET_DEFAULT): Replace MASK_EABI with + OPTION_MASK_EABI. + * config/rs6000/eabialtivec.h (TARGET_DEFAULT): Same. + * config/rs6000/linuxaltivec.h (TARGET_DEFAULT): Replace + MASK_ALTIVEC with OPTION_MASK_ALTIVEC. + * config/rs6000/rs6000-cpus.def (MASK_ALTIVEC, MASK_CMPB, + MASK_CRYPTO, MASK_DFP, MASK_DIRECT_MOVE, MASK_DLMZB, MASK_EABI, + MASK_FLOAT128_KEYWORD, MASK_FLOAT128_HW, MASK_FPRND, + MASK_P8_FUSION, MASK_HARD_FLOAT, MASK_HTM, MASK_ISEL, MASK_MFCRF, + MASK_MMA, MASK_MULHW, MASK_MULTIPLE, MASK_NO_UPDATE): + Replace with + OPTION_MASK_ALTIVEC, OPTION_MASK_CMPB, OPTION_MASK_CRYPTO, + OPTION_MASK_DFP, OPTION_MASK_DIRECT_MOVE, OPTION_MASK_DLMZB, + OPTION_MASK_EABI, OPTION_MASK_FLOAT128_KEYWORD, + OPTION_MASK_FLOAT128_HW, OPTION_MASK_FPRND, OPTION_MASK_P8_FUSION, + OPTION_MASK_HARD_FLOAT, OPTION_MASK_HTM, OPTION_MASK_ISEL, + OPTION_MASK_MFCRF, OPTION_MASK_MMA, OPTION_MASK_MULHW, + OPTION_MASK_MULTIPLE, OPTION_MASK_NO_UPDATE. + * config/rs6000/rs6000.cc (rs6000_darwin_file_start): Replace + MASK_MFCRF, MASK_ALTIVEC with OPTION_MASK_MFCRF, OPTION_MASK_ALTIVEC. + * config/rs6000/rs6000.h (TARGET_DEFAULT): Replace MASK_MULTIPLE + with OPTION_MASK_MULTIPLE. + (MASK_ALTIVEC, MASK_CMPB, MASK_CRYPTO, MASK_DFP, + MASK_DIRECT_MOVE, MASK_DLMZB, MASK_EABI, MASK_FLOAT128_KEYWORD, + MASK_FLOAT128_HW, MASK_FPRND, MASK_P8_FUSION, MASK_HARD_FLOAT, + MASK_HTM, MASK_ISEL, MASK_MFCRF, MASK_MMA, MASK_MULHW, + MASK_MULTIPLE, MASK_NO_UPDATE): Delete. + * config/rs6000/vxworks.h (TARGET_DEFAULT): Replace MASK_EABI + with OPTION_MASK_EABI. + +2022-06-24 Will Schmidt <will_schmidt@vnet.ibm.com> + + * config/rs6000/rs6000.cc (RS6000_BTM_ALTIVEC, RS6000_BTM_CMPB, + RS6000_BTM_VSX, RS6000_BTM_FRE, RS6000_BTM_P8_VECTOR, + RS6000_BTM_P9_VECTOR, RS6000_BTM_P9_MISC, RS6000_BTM_MODULO, + RS6000_BTM_CRYPTO, RS6000_BTM_HTM): Replace with OPTION_MASK_ALTIVEC, + OPTION_MASK_CMPB, OPTION_MASK_VSX, OPTION_MASK_POPCNTB, + OPTION_MASK_P8_VECTOR, OPTION_MASK_P9_VECTOR, OPTION_MASK_P9_MISC, + OPTION_MASK_MODULO, OPTION_MASK_CRYPTO, OPTION_MASK_HTM. + * config/rs6000/rs6000.h (RS6000_BTM_MODULO, RS6000_BTM_ALTIVEC, + RS6000_BTM_CMPB, RS6000_BTM_VSX, RS6000_BTM_P8_VECTOR, + RS6000_BTM_P9_VECTOR, RS6000_BTM_P9_MISC, RS6000_BTM_CRYPTO, + RS6000_BTM_HTM, RS6000_BTM_FRE): Remove. + +2022-06-24 Will Schmidt <will_schmidt@vnet.ibm.com> + + * config/rs6000/rs6000-c.cc: Update comments. + * config/rs6000/rs6000.cc (RS6000_BTM_FRES, RS6000_BTM_FRSQRTE, + RS6000_BTM_FRSQRTES, RS6000_BTM_POPCNTD, RS6000_BTM_CELL, + RS6000_BTM_64BIT, RS6000_BTM_POWERPC64, RS6000_BTM_DFP, + RS6000_BTM_HARD_FLOAT,RS6000_BTM_LDBL128, RS6000_BTM_FLOAT128, + RS6000_BTM_FLOAT128_HW, RS6000_BTM_MMA, RS6000_BTM_P10): Replace + with OPTION_MASK_PPC_GFXOPT, OPTION_MASK_PPC_GFXOPT, + OPTION_MASK_POPCNTB, OPTION_MASK_POPCNTD, + OPTION_MASK_FPRND, MASK_64BIT, MASK_POWERPC64, + OPTION_MASK_DFP, OPTION_MASK_SOFT_FLOAT, OPTION_MASK_MULTIPLE, + OPTION_MASK_FLOAT128_KEYWORD, OPTION_MASK_FLOAT128_HW, + OPTION_MASK_MMA, OPTION_MASK_POWER10. + * config/rs6000/rs6000.h (RS6000_BTM_FRES, RS6000_BTM_FRSQRTE, + RS6000_BTM_FRSQRTES, RS6000_BTM_POPCNTD, RS6000_BTM_CELL, + RS6000_BTM_DFP, RS6000_BTM_HARD_FLOAT, RS6000_BTM_LDBL128, + RS6000_BTM_64BIT, RS6000_BTM_POWERPC64, RS6000_BTM_FLOAT128, + RS6000_BTM_FLOAT128_HW, RS6000_BTM_MMA, RS6000_BTM_P10): Delete. + +2022-06-24 Will Schmidt <will_schmidt@vnet.ibm.com> + + * config/rs6000/rs6000.h (RS6000_BTM_COMMON, RS6000_BTM_ALWAYS, + MASK_REGNAMES, OPTION_MASK_REGNAMES, MASK_PROTOTYPE, + OPTION_MASK_PROTOTYPE, MASK_UPDATE, OPTION_MASK_UPDATE): Remove. + +2022-06-24 Richard Biener <rguenther@suse.de> + + PR middle-end/106070 + * match.pd (a != b ? a : b): Fix translation of + operand_equal_for_comparison_p. + +2022-06-24 Jan Hubicka <jh@suse.cz> + + PR ipa/106057 + * tree-ssa-alias.cc (stmt_kills_ref_p): Check for external throw. + +2022-06-24 Martin Liska <mliska@suse.cz> + + PR middle-end/106059 + * profile-count.h: *= and /= operators need to modify this + object. + +2022-06-24 Roger Sayle <roger@nextmovesoftware.com> + Uroš Bizjak <ubizjak@gmail.com> + + PR target/105930 + * config/i386/i386.md (*<any_or>di3_doubleword): Split after + reload. Use rtx_equal_p to avoid creating memory-to-memory moves, + and emit NOTE_INSN_DELETED if operand[2] is zero (i.e. with -O0). + +2022-06-24 Alexandre Oliva <oliva@adacore.com> + + * common.opt (nostdlib++): New. + * doc/invoke.texi (-nostdlib++): Document it. + +2022-06-24 Alexandre Oliva <oliva@adacore.com> + + * doc/sourcebuild.texi (Environment attributes): Document + two_plus_gigs. + +2022-06-23 David Malcolm <dmalcolm@redhat.com> + + * common.opt (fdiagnostics-show-rules): New option. + * diagnostic-format-json.cc (diagnostic_output_format_init_json): + Fix up context->show_rules. + * diagnostic-format-sarif.cc + (diagnostic_output_format_init_sarif): Likewise. + * diagnostic-metadata.h (diagnostic_metadata::rule): New class. + (diagnostic_metadata::precanned_rule): New class. + (diagnostic_metadata::add_rule): New. + (diagnostic_metadata::get_num_rules): New. + (diagnostic_metadata::get_rule): New. + (diagnostic_metadata::m_rules): New field. + * diagnostic.cc (diagnostic_initialize): Initialize show_rules. + (print_any_rules): New. + (diagnostic_report_diagnostic): Call it. + * diagnostic.h (diagnostic_context::show_rules): New field. + * doc/invoke.texi (-fno-diagnostics-show-rules): New option. + * opts.cc (common_handle_option): Handle + OPT_fdiagnostics_show_rules. + * toplev.cc (general_init): Set up global_dc->show_rules. + +2022-06-23 Martin Liska <mliska@suse.cz> + + PR c++/106062 + * ubsan.cc (sanitize_unreachable_fn): Change order of calls + in order to initialize UBSAN built-ins. + +2022-06-23 Martin Liska <mliska@suse.cz> + + PR ipa/105600 + * ipa-icf.cc (sem_item_optimizer::filter_removed_items): + Skip variables with body_removed. + +2022-06-23 liuhongt <hongtao.liu@intel.com> + + * config/i386/sse.md:(sse4_2_pcmpestr): Replace REGNO with + reg_or_subregno. + (sse4_2_pcmpistr): Ditto. + +2022-06-23 Xionghu Luo <xionghuluo@tencent.com> + + * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): Fix + typo. + * tree-ssa-loop-ivopts.cc (struct iv_cand): Likewise. + * tree-switch-conversion.h: Likewise. + +2022-06-22 Jason Merrill <jason@redhat.com> + + PR c++/104642 + * common.opt: Add -funreachable-traps. + * doc/invoke.texi (-funreachable-traps): Document it. + * opts.cc (finish_options): Enable at -O0 or -Og. + * tree.cc (build_common_builtin_nodes): Add __builtin_trap. + (builtin_decl_unreachable, build_builtin_unreachable): New. + * tree.h: Declare them. + * ubsan.cc (sanitize_unreachable_fn): Factor out. + (ubsan_instrument_unreachable): Use + gimple_build_builtin_unreachable. + * ubsan.h (sanitize_unreachable_fn): Declare. + * gimple.cc (gimple_build_builtin_unreachable): New. + * gimple.h: Declare it. + * builtins.cc (expand_builtin_unreachable): Add assert. + (fold_builtin_0): Call build_builtin_unreachable. + * sanopt.cc: Don't run for just SANITIZE_RETURN + or SANITIZE_UNREACHABLE when trapping. + * cgraphunit.cc (walk_polymorphic_call_targets): Use new + unreachable functions. + * gimple-fold.cc (gimple_fold_call) + (gimple_get_virt_method_for_vtable) + * ipa-fnsummary.cc (redirect_to_unreachable) + * ipa-prop.cc (ipa_make_edge_direct_to_target) + (ipa_impossible_devirt_target) + * ipa.cc (walk_polymorphic_call_targets) + * tree-cfg.cc (pass_warn_function_return::execute) + (execute_fixup_cfg) + * tree-ssa-loop-ivcanon.cc (remove_exits_and_undefined_stmts) + (unloop_loops) + * tree-ssa-sccvn.cc (eliminate_dom_walker::eliminate_stmt): + Likewise. + +2022-06-22 Richard Sandiford <richard.sandiford@arm.com> + + PR tree-optimization/106019 + * tree-data-ref.cc (dr_may_alias_p): Try using the + innermost_loop_behavior to disambiguate non-loop queries. + +2022-06-22 Palmer Dabbelt <palmer@rivosinc.com> + + * doc/invoke.texi (RISC-V): Document -mtune=thead-c906. + +2022-06-22 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md (bswapsi2_internal): + Enlarge the buffer that is obviously smaller than the template + string given to sprintf(). + +2022-06-21 Roger Sayle <roger@nextmovesoftware.com> + Marek Polacek <polacek@redhat.com> + Segher Boessenkool <segher@kernel.crashing.org> + Kewen Lin <linkw@linux.ibm.com> + + PR target/105991 + * config/rs6000/rs6000.md (rotl<mode>3_insert_3): Check that + exact_log2 doesn't return -1 (or zero). + (plus_xor): New code iterator. + (*rotl<mode>3_insert_3_<code>): New define_insn_and_split. + +2022-06-21 Nathan Sidwell <nathan@acm.org> + + * doc/invoke.texi (C++ Modules): Remove language-linkage + as missing feature. + +2022-06-21 Arjun Shankar <arjun@redhat.com> + + PR tree-optimization/94899 + * match.pd (X + C < Y + C -> (signed) X < (signed) Y, if C is + 0x80000000): New simplification. + +2022-06-21 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/106032 + * ifcvt.cc (noce_try_sign_mask): Punt if !t_unconditional, and + t may_trap_or_fault_p, even if it is cheap. + +2022-06-21 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/106030 + * expr.cc (expand_cond_expr_using_cmove): Pass NULL_RTX instead of + temp to expand_operands if mode has been promoted. + +2022-06-21 Xionghu Luo <xionghuluo@tencent.com> + + PR target/105740 + * gimple-if-to-switch.cc (find_conditions): Don't skip the first + condition bb. + +2022-06-21 Siddhesh Poyarekar <siddhesh@gotplt.org> + + PR tree-optimization/105736 + * tree-object-size.cc (addr_object_size): Return size_unknown + when object offset computation returns an error. + +2022-06-20 H.J. Lu <hjl.tools@gmail.com> + + PR target/105960 + * config/i386/i386.cc (ix86_function_ok_for_sibcall): Return + false if PIC register is used when calling ifunc functions. + +2022-06-20 Richard Biener <rguenther@suse.de> + + PR middle-end/106027 + * fold-const.cc (fold_to_nonsharp_ineq_using_bound): Use the + type of the prevailing comparison for the new comparison type. + (fold_binary_loc): Use proper types for the A < X && A + 1 > Y + to A < X && A >= Y folding. + +2022-06-20 Kewen Lin <linkw@linux.ibm.com> + + PR tree-optimization/105940 + * tree-vect-loop.cc (vect_analyze_loop_2): Add new parameter + slp_done_for_suggested_uf and adjust with it accordingly. + (vect_analyze_loop_1): Add new variable slp_done_for_suggested_uf, + pass it down to vect_analyze_loop_2 for the initial analysis and + applying suggested unroll factor. + (vect_is_simple_reduction): Add parameter slp and adjust with it. + (vect_analyze_scalar_cycles_1): Add parameter slp and pass down. + (vect_analyze_scalar_cycles): Likewise. + +2022-06-20 Martin Liska <mliska@suse.cz> + + * bb-reorder.cc (find_traces_1_round): Add operators / and * and + use them. + (better_edge_p): Likewise. + * cfgloop.cc (find_subloop_latch_edge_by_profile): Likewise. + * cfgloopmanip.cc (scale_loop_profile): Likewise. + * cfgrtl.cc (force_nonfallthru_and_redirect): Likewise. + * cgraph.cc (cgraph_edge::maybe_hot_p): Likewise. + * config/sh/sh.cc (expand_cbranchdi4): Likewise. + * dojump.cc (do_compare_rtx_and_jump): Likewise. + * final.cc (compute_alignments): Likewise. + * ipa-cp.cc (update_counts_for_self_gen_clones): Likewise. + (decide_about_value): Likewise. + * ipa-inline-analysis.cc (do_estimate_edge_time): Likewise. + * loop-unroll.cc (unroll_loop_runtime_iterations): Likewise. + * modulo-sched.cc (sms_schedule): Likewise. + * omp-expand.cc (extract_omp_for_update_vars): Likewise. + (expand_omp_ordered_sink): Likewise. + (expand_omp_for_ordered_loops): Likewise. + (expand_omp_for_static_nochunk): Likewise. + * predict.cc (maybe_hot_count_p): Likewise. + (probably_never_executed): Likewise. + (set_even_probabilities): Likewise. + (handle_missing_profiles): Likewise. + (expensive_function_p): Likewise. + * profile-count.h: Likewise. + * profile.cc (compute_branch_probabilities): Likewise. + * stmt.cc (emit_case_dispatch_table): Likewise. + * symtab-thunks.cc (expand_thunk): Likewise. + * tree-ssa-loop-manip.cc (tree_transform_and_unroll_loop): Likewise. + * tree-ssa-sink.cc (select_best_block): Likewise. + * tree-switch-conversion.cc (switch_decision_tree::analyze_switch_statement): Likewise. + (switch_decision_tree::balance_case_nodes): Likewise. + (switch_decision_tree::emit_case_nodes): Likewise. + * tree-vect-loop.cc (scale_profile_for_vect_loop): Likewise. + +2022-06-20 yulong <shiyulong@iscas.ac.cn> + + * config/riscv/riscv-builtins.cc (RISCV_ATYPE_VOID_PTR): New. + * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Changed the FUNCTION_TYPE + of RISCV_BUILTIN. + * config/riscv/riscv-ftypes.def (0): Remove unused. + (1): New. + +2022-06-19 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.cc (xtensa_is_insn_L32R_p): + Consider relaxed MOVI instructions as L32R. + +2022-06-19 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.cc (xtensa_emit_move_sequence): + Use can_create_pseudo_p(), instead of using individual + reload_in_progress and reload_completed. + (xtensa_expand_block_set_small_loop): Use xtensa_simm8x256(), + the existing predicate function. + (xtensa_is_insn_L32R_p, gen_int_relational, xtensa_emit_sibcall): + Use the standard RTX code predicate macros such as MEM_P, + SYMBOL_REF_P and/or CONST_INT_P. + * config/xtensa/xtensa.md: Avoid using numeric literals to determine + if callee-saved register, at the split patterns for indirect sibcall + fixups. + +2022-06-18 Jakub Jelinek <jakub@redhat.com> + + * common.opt (flag_sanitize_trap): New variable. + (fsanitize-trap=, fsanitize-trap): New options. + (fsanitize-undefined-trap-on-error): Change into deprecated alias + for -fsanitize-trap=all. + * opts.h (struct sanitizer_opts_s): Add can_trap member. + * opts.cc (finish_options): Complain about unsupported + -fsanitize-trap= options. + (sanitizer_opts): Add can_trap values to all entries. + (get_closest_sanitizer_option): Ignore -fsanitize-trap= + options which have can_trap false. + (parse_sanitizer_options): Add support for -fsanitize-trap=. + For -fsanitize-trap=all, enable + SANITIZE_UNDEFINED | SANITIZE_UNDEFINED_NONDEFAULT. Disallow + -fsanitize-trap=vptr here. + (common_handle_option): Handle OPT_fsanitize_trap_ and + OPT_fsanitize_trap. + * sanopt.cc (maybe_optimize_ubsan_null_ifn): Check + flag_sanitize_trap & SANITIZE_{NULL,ALIGNMENT} instead of + flag_sanitize_undefined_trap_on_error. + * gcc.cc (sanitize_spec_function): Use + flag_sanitize & ~flag_sanitize_trap instead of flag_sanitize + and drop use of flag_sanitize_undefined_trap_on_error in + "undefined" handling. + * ubsan.cc (ubsan_instrument_unreachable): Use + flag_sanitize_trap & SANITIZE_??? instead of + flag_sanitize_undefined_trap_on_error. + (ubsan_expand_bounds_ifn, ubsan_expand_null_ifn, + ubsan_expand_objsize_ifn, ubsan_expand_ptr_ifn, + ubsan_build_overflow_builtin, instrument_bool_enum_load, + ubsan_instrument_float_cast, instrument_nonnull_arg, + instrument_nonnull_return, instrument_builtin): Likewise. + * doc/invoke.texi (-fsanitize-trap=, -fsanitize-trap): Document. + (-fsanitize-undefined-trap-on-error): Document as deprecated + alias of -fsanitize-trap. + +2022-06-18 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/105998 + * varasm.cc (narrowing_initializer_constant_valid_p): Check + SCALAR_INT_MODE_P instead of INTEGRAL_MODE_P, also break on + ! INTEGRAL_TYPE_P and do the same check also on op{0,1}'s type. + +2022-06-18 Roger Sayle <roger@nextmovesoftware.com> + + PR tree-optimization/105835 + * match.pd (convert (mult zero_one_valued_p@1 INTEGER_CST@2)): + Narrow integer multiplication by a zero_one_valued_p operand. + (convert (cond @1 INTEGER_CST@2 INTEGER_CST@3)): Push integer + conversions inside COND_EXPR where both data operands are + integer constants. + +2022-06-18 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/constraints.md (Y): + Change to include integer constants until reload begins. + * config/xtensa/predicates.md (move_operand): Ditto. + * config/xtensa/xtensa.cc (xtensa_emit_move_sequence): + Change to allow storing integer constants into litpool only after + reload begins. + +2022-06-17 Uroš Bizjak <ubizjak@gmail.com> + + PR target/105209 + * config/alpha/alpha-protos.h (alpha_store_data_bypass_p): New. + * config/alpha/alpha.cc (alpha_store_data_bypass_p): New function. + (alpha_store_data_bypass_p_1): Ditto. + * config/alpha/ev4.md: Use alpha_store_data_bypass_p instead + of generic store_data_bypass_p. + (ev4_ist_c): Remove insn reservation. + +2022-06-17 Uroš Bizjak <ubizjak@gmail.com> + + PR target/105970 + * config/i386/i386.cc (ix86_function_arg): Assert that + the mode of pointer argumet is equal to ptr_mode, not Pmode. + +2022-06-17 Uroš Bizjak <ubizjak@gmail.com> + + PR target/105993 + * config/i386/sse.md (vpmov splitter): Use (match_dup ...) + instead of REGNO comparisons in combine splitter. + +2022-06-17 Segher Boessenkool <segher@kernel.crashing.org> + + * config/rs6000/rs6000.cc (rs6000_invalid_conversion): Correct some + types. + +2022-06-17 Kito Cheng <kito.cheng@sifive.com> + + * config/riscv/bitmanip.md: Supress warning. + +2022-06-17 Richard Earnshaw <rearnsha@arm.com> + + PR target/106004 + * config/arm/arm.cc (arm_print_operand, case 'V'): Use UINTVAL. + Clear bits in the mask above bit 31. + +2022-06-17 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/mve.md (*mve_mov<mode>): Re-order constraints + to avoid spilling trivial literals to the constant pool. + +2022-06-16 David Malcolm <dmalcolm@redhat.com> + + * gimple-ssa-warn-access.cc (warn_string_no_nul): Add + auto_diagnostic_group to group any warning with its note. + (maybe_warn_for_bound): Likewise. + (check_access): Likewise. + (warn_dealloc_offset): Likewise. + (pass_waccess::maybe_warn_memmodel): Likewise. + (pass_waccess::maybe_check_dealloc_call): Likewise. + (pass_waccess::warn_invalid_pointer): Likewise. + (pass_waccess::check_dangling_stores): Likewise. + +2022-06-16 Jason Merrill <jason@redhat.com> + + * opts.cc (common_handle_option) [OPT_fsanitize_]: Set + opts_set->x_flag_sanitize. + +2022-06-16 Jason Merrill <jason@redhat.com> + + * flags.h (issue_strict_overflow_warning): Comment #endif. + +2022-06-16 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-cache.cc (ranger_cache::apply_inferred_ranges): If name + was invaraint before, clear the invariant bit. + * gimple-range-gori.cc (gori_map::set_range_invariant): Add a flag. + * gimple-range-gori.h (gori_map::set_range_invariant): Adjust prototype. + +2022-06-16 Andrew MacLeod <amacleod@redhat.com> + + * tree-ssa-propagate.cc (before_dom_children): Call value_of_stmt. + +2022-06-16 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/105983 + * match.pd (y == XXX_MIN || x < y -> x <= y - 1, + y != XXX_MIN && x >= y -> x > y - 1): Use :cs instead of :s + on non-equality comparisons. + +2022-06-16 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/105984 + * match.pd (__builtin_mul_overflow_p (x, cst, (stype) 0) -> + x > stype_max / cst || x < stype_min / cst): fold_convert @1 + to TREE_TYPE (@0) just once and test for negative divisor + also on that folded constant instead of on @1. + +2022-06-16 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/105951 + * tree-ssa-ccp.cc (optimize_atomic_bit_test_and, + optimize_atomic_op_fetch_cmp_0): Remember gimple_call_fn (call) + as last argument to the internal functions. + * builtins.cc (expand_ifn_atomic_bit_test_and): Adjust for the + extra call argument to ifns. If expand_atomic_fetch_op fails for the + lhs == NULL_TREE case, fall through into the optab code with + gen_reg_rtx (mode) as target. If second expand_atomic_fetch_op + fails, construct a CALL_EXPR and expand that. + (expand_ifn_atomic_op_fetch_cmp_0): Adjust for the extra call argument + to ifns. If expand_atomic_fetch_op fails, construct a CALL_EXPR and + expand that. + +2022-06-16 Haochen Gui <guihaoc@gcc.gnu.org> + + PR target/103316 + * config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_builtin): Enable + gimple folding for RS6000_BIF_VCMPEQUT, RS6000_BIF_VCMPNET, + RS6000_BIF_CMPGE_1TI, RS6000_BIF_CMPGE_U1TI, RS6000_BIF_VCMPGTUT, + RS6000_BIF_VCMPGTST, RS6000_BIF_CMPLE_1TI, RS6000_BIF_CMPLE_U1TI. + * config/rs6000/vector.md (VEC_IC): New mode iterator. Add support + for new Power10 V1TI instructions. + (vec_cmp<mode><mode>): Set mode iterator to VEC_IC. + (vec_cmpu<mode><mode>): Likewise. + (vector_nlt<mode>): Set mode iterator to VEC_IC. + (vector_nltv1ti): Remove. + (vector_gtu<mode>): Set mode iterator to VEC_IC. + (vector_gtuv1ti): Remove. + (vector_nltu<mode>): Set mode iterator to VEC_IC. + (vector_nltuv1ti): Remove. + (vector_geu<mode>): Set mode iterator to VEC_IC. + (vector_ngt<mode>): Likewise. + (vector_ngtv1ti): Remove. + (vector_ngtu<mode>): Set mode iterator to VEC_IC. + (vector_ngtuv1ti): Remove. + (vector_gtu_<mode>_p): Set mode iterator to VEC_IC. + (vector_gtu_v1ti_p): Remove. + (vrotl<mode>3): Set mode iterator to VEC_IC. Emit insns for V1TI. + (vrotlv1ti3): Remove. + (vashr<mode>3): Set mode iterator to VEC_IC. Emit insns for V1TI. + (vashrv1ti3): Remove. + +2022-06-16 Martin Liska <mliska@suse.cz> + + * gengtype-state.cc (read_a_state_token): Do not skip extra + character after escaped sequence. + +2022-06-16 Martin Liska <mliska@suse.cz> + + PR driver/105564 + * spellcheck.cc (test_find_closest_string): Add new test. + * spellcheck.h (class best_match): Prefer a difference in + trailing sign symbol. + +2022-06-16 liuhongt <hongtao.liu@intel.com> + + PR tree-optimization/53533 + * match.pd: Simplify (B * v + C) * D -> BD * v + CD and + (v + B) * C + D -> C * v + BCD when B,C,D are all INTEGER_CST, + and there's no overflow or !TYPE_OVERFLOW_UNDEFINED. + +2022-06-15 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md (DSC): New split pattern and mode iterator. + +2022-06-15 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/predicates.md (reload_operand): + New predicate. + * config/xtensa/xtensa.md: New peephole2 pattern. + +2022-06-15 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md (*round_up_to_even): + New insn-and-split pattern. + (*signed_ge_zero): Ditto. + +2022-06-15 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa-protos.h (xtensa_prepare_expand_call, + xtensa_emit_sibcall): New prototypes. + (xtensa_expand_epilogue): Add new argument that specifies whether + or not sibling call. + * config/xtensa/xtensa.cc (TARGET_FUNCTION_OK_FOR_SIBCALL): + New macro definition. + (xtensa_prepare_expand_call): New function in order to share + the common code. + (xtensa_emit_sibcall, xtensa_function_ok_for_sibcall): + New functions. + (xtensa_expand_epilogue): Add new argument sibcall_p and use it + for sibling call handling. + * config/xtensa/xtensa.md (call, call_value): + Use xtensa_prepare_expand_call. + (call_internal, call_value_internal): + Add the condition in order to be disabled if sibling call. + (sibcall, sibcall_value, sibcall_epilogue): New expansions. + (sibcall_internal, sibcall_value_internal): New insn patterns, + and split ones in order to take care of the indirect sibcalls. + +2022-06-15 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * doc/invoke.texi: Document -mextra-l32r-costs= option. + +2022-06-15 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/105962 + * doc/invoke.texi: Add -fno-analyzer-undo-inlining. + * tree-diagnostic-path.cc (default_tree_diagnostic_path_printer): + Extend -fdiagnostics-path-format=separate-events so that with + -fdiagnostics-show-path-depths it prints fndecls as well as stack + depths. + +2022-06-15 David Malcolm <dmalcolm@redhat.com> + + * value-relation.h: Add "final" and "override" to relation_oracle + vfunc implementations as appropriate. + +2022-06-15 Richard Sandiford <richard.sandiford@arm.com> + + PR middle-end/105975 + Revert everything apart from the expand_fn_using_insn and + expand_direct_optab_fn changes from: + * internal-fn.def (DEF_INTERNAL_INSN_FN): New macro. + (GOMP_SIMT_ENTER_ALLOC, GOMP_SIMT_EXIT, GOMP_SIMT_LANE) + (GOMP_SIMT_LAST_LANE, GOMP_SIMT_ORDERED_PRED, GOMP_SIMT_VOTE_ANY) + (GOMP_SIMT_XCHG_BFLY, GOMP_SIMT_XCHG_IDX): Use it. + * internal-fn.h (direct_internal_fn_info::directly_mapped): New + member variable. + (direct_internal_fn_info::vectorizable): Reduce to 1 bit. + (direct_internal_fn_p): Also return true for internal functions + that map directly to instructions defined target-insns.def. + (direct_internal_fn): Adjust comment accordingly. + * internal-fn.cc (direct_insn, optab1, optab2, vectorizable_optab1) + (vectorizable_optab2): New local macros. + (not_direct): Initialize directly_mapped. + (mask_load_direct, load_lanes_direct, mask_load_lanes_direct) + (gather_load_direct, len_load_direct, mask_store_direct) + (store_lanes_direct, mask_store_lanes_direct, vec_cond_mask_direct) + (vec_cond_direct, scatter_store_direct, len_store_direct) + (vec_set_direct, unary_direct, binary_direct, ternary_direct) + (cond_unary_direct, cond_binary_direct, cond_ternary_direct) + (while_direct, fold_extract_direct, fold_left_direct) + (mask_fold_left_direct, check_ptrs_direct): Use the macros above. + (expand_GOMP_SIMT_ENTER_ALLOC, expand_GOMP_SIMT_EXIT): Delete + (expand_GOMP_SIMT_LANE, expand_GOMP_SIMT_LAST_LANE): Likewise; + (expand_GOMP_SIMT_ORDERED_PRED, expand_GOMP_SIMT_VOTE_ANY): Likewise. + (expand_GOMP_SIMT_XCHG_BFLY, expand_GOMP_SIMT_XCHG_IDX): Likewise. + (direct_internal_fn_types): Handle functions that map to instructions + defined in target-insns.def. + (direct_internal_fn_types): Likewise. + (direct_internal_fn_supported_p): Likewise. + (internal_fn_expanders): Likewise. + (expand_fn_using_insn): New function, + split out and adapted from... + (expand_direct_optab_fn): ...here. + (expand_GOMP_SIMT_ENTER_ALLOC): Use it. + (expand_GOMP_SIMT_EXIT): Likewise. + (expand_GOMP_SIMT_LANE): Likewise. + (expand_GOMP_SIMT_LAST_LANE): Likewise. + (expand_GOMP_SIMT_ORDERED_PRED): Likewise. + (expand_GOMP_SIMT_VOTE_ANY): Likewise. + (expand_GOMP_SIMT_XCHG_BFLY): Likewise. + (expand_GOMP_SIMT_XCHG_IDX): Likewise. + +2022-06-15 Richard Earnshaw <rearnsha@arm.com> + + PR target/105981 + * config/arm/arm.cc (gen_cpymem_ldrd_strd): Rename low_reg and hi_reg + to first_reg and second_reg respectively. Initialize them correctly + when generating big-endian code. + +2022-06-15 Richard Earnshaw <rearnsha@arm.com> + + PR target/105974 + * config/arm/arm.cc (arm_bfi_1_p): Use UINTVAL instead of XUINT. + +2022-06-15 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105971 + * tree-ssa-alias.cc (refs_may_alias_p_2): Put bail-out for + FUNCTION_DECL and LABEL_DECL refs after decl-decl disambiguation + to leak less surprising alias results. + +2022-06-15 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105969 + * gimple-ssa-sprintf.cc (get_origin_and_offset_r): Avoid division + by zero in overflow check. + +2022-06-15 Richard Sandiford <richard.sandiford@arm.com> + + PR tree-optimization/105254 + PR tree-optimization/105940 + Revert: + * config/aarch64/aarch64.cc + (aarch64_vector_costs::determine_suggested_unroll_factor): Take a + loop_vec_info as argument. Restrict the unroll factor to values + that divide the VF. + (aarch64_vector_costs::finish_cost): Update call accordingly. + +2022-06-15 Richard Sandiford <richard.sandiford@arm.com> + + * read-rtl.cc (find_int): Substitute symbolic constants + before converting the string to an integer. + +2022-06-15 Roger Sayle <roger@nextmovesoftware.com> + Richard Biener <rguenther@suse.de> + + * match.pd (convert (lshift @1 INTEGER_CST@2)): Narrow integer + left shifts by a constant when the result is truncated, and the + shift constant is well-defined. + * tree-vect-patterns.cc (vect_recog_rotate_pattern): Add + support for rotations of signed integer types, by lowering + using unsigned vector shifts. + +2022-06-15 liuhongt <hongtao.liu@intel.com> + + PR target/105953 + * config/i386/sse.md (*avx_cmp<mode>3_ltint_not): Force_reg + operands[3]. + +2022-06-14 Surya Kumari Jangala <jskumari@linux.ibm.com> + + PR rtl-optimization/105041 + * regrename.cc (check_new_reg_p): Use nregs value from du chain. + +2022-06-14 Segher Boessenkool <segher@kernel.crashing.org> + + * config/rs6000/vsx.md (VS_scalar): Delete. + (rest of file): Adjust. + +2022-06-14 Jan Hubicka <hubicka@ucw.cz> + + PR ipa/105739 + * ipa-prop.cc (ipa_load_from_parm_agg): Punt on volatile loads. + +2022-06-14 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/bitmanip.md: Add split to handle opportunities + for slli + sh[123]add.uw + +2022-06-14 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/predicates.md (consecutive_bits_operand): + Implement new predicate. + +2022-06-14 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105946 + * tree-ssa-uninit.cc (maybe_warn_pass_by_reference): + Do not look at arguments not specified in the function call. + +2022-06-14 Richard Biener <rguenther@suse.de> + + PR middle-end/105965 + * match.pd (view_convert CONSTRUCTOR): Handle single-element + CTOR case. + +2022-06-14 Eric Botcazou <ebotcazou@adacore.com> + + * warning-control.cc (copy_warning) [generic version]: Do not erase + the warning data of the destination location when the no-warning + bit is not set on the source. + (copy_warning) [tree version]: Return early if TO is equal to FROM. + (copy_warning) [gimple version]: Likewise. + +2022-06-14 Kewen Lin <linkw@linux.ibm.com> + + PR tree-optimization/105940 + * tree-vect-loop.cc (vect_analyze_loop_2): Move the place of + applying suggested_unroll_factor after start_over. + +2022-06-14 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/predicates.md (shifted_mask_operand): + New predicate. + * config/xtensa/xtensa.md (*andsi3_const_pow2_minus_one): + New insn-and-split pattern. + (*andsi3_const_negative_pow2, *andsi3_const_shifted_mask, + *masktrue_const_pow2_minus_one, *masktrue_const_negative_pow2, + *masktrue_const_shifted_mask): Ditto. + +2022-06-14 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md (*masktrue_bitcmpl): New insn pattern. + +2022-06-14 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa-protos.h (xtensa_emit_branch): + Remove the first argument. + (xtensa_emit_bit_branch): Remove it because now called only from the + output statement of *bittrue insn pattern. + * config/xtensa/xtensa.cc (gen_int_relational): Remove the last + argument 'p_invert', and make so that the condition is reversed by + itself as needed. + (xtensa_expand_conditional_branch): Share the common path, and remove + condition inversion code. + (xtensa_emit_branch, xtensa_emit_movcc): Simplify by removing the + "false side" pattern. + (xtensa_emit_bit_branch): Remove it because of the abovementioned + reason, and move the function body to *bittrue insn pattern. + * config/xtensa/xtensa.md (*bittrue): Transplant the output + statement from removed xtensa_emit_bit_branch(). + (*bfalse, *ubfalse, *bitfalse, *maskfalse): Remove the "false side" + insn patterns. + +2022-06-14 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/predicates.md (logical_shift_operator, + xtensa_shift_per_byte_operator): New predicates. + * config/xtensa/xtensa-protos.h (xtensa_shlrd_which_direction): + New prototype. + * config/xtensa/xtensa.cc (xtensa_shlrd_which_direction): + New helper function for funnel shift patterns. + * config/xtensa/xtensa.md (ior_op): New code iterator. + (*ashlsi3_1): Replace with new split pattern. + (*shift_per_byte): Unify *ashlsi3_3x, *ashrsi3_3x and *lshrsi3_3x. + (*shift_per_byte_omit_AND_0, *shift_per_byte_omit_AND_1): + New insn-and-split patterns that redirect to *xtensa_shift_per_byte, + in order to omit unnecessary bitwise AND operation. + (*shlrd_reg_<code>, *shlrd_const_<code>, *shlrd_per_byte_<code>, + *shlrd_per_byte_<code>_omit_AND): + New insn patterns for funnel shifts. + +2022-06-13 Jason Merrill <jason@redhat.com> + + * tree-cfg.cc (pass_warn_function_return::execute): Also check + BUILT_IN_TRAP. + +2022-06-13 Maciej W. Rozycki <macro@embecosm.com> + + * config/riscv/riscv.md (length): Remove the explicit setting + for "fcmp". + +2022-06-13 H.J. Lu <hjl.tools@gmail.com> + + * common/config/i386/cpuinfo.h (get_available_features): Require + AVX for F16C and VAES. + +2022-06-13 Uroš Bizjak <ubizjak@gmail.com> + + PR target/105927 + * config/i386/predicates.md (register_no_elim_operand): + Return true for subreg of a memory operand. + +2022-06-13 Richard Sandiford <richard.sandiford@arm.com> + + * internal-fn.def (DEF_INTERNAL_INSN_FN): New macro. + (GOMP_SIMT_ENTER_ALLOC, GOMP_SIMT_EXIT, GOMP_SIMT_LANE) + (GOMP_SIMT_LAST_LANE, GOMP_SIMT_ORDERED_PRED, GOMP_SIMT_VOTE_ANY) + (GOMP_SIMT_XCHG_BFLY, GOMP_SIMT_XCHG_IDX): Use it. + * internal-fn.h (direct_internal_fn_info::directly_mapped): New + member variable. + (direct_internal_fn_info::vectorizable): Reduce to 1 bit. + (direct_internal_fn_p): Also return true for internal functions + that map directly to instructions defined target-insns.def. + (direct_internal_fn): Adjust comment accordingly. + * internal-fn.cc (direct_insn, optab1, optab2, vectorizable_optab1) + (vectorizable_optab2): New local macros. + (not_direct): Initialize directly_mapped. + (mask_load_direct, load_lanes_direct, mask_load_lanes_direct) + (gather_load_direct, len_load_direct, mask_store_direct) + (store_lanes_direct, mask_store_lanes_direct, vec_cond_mask_direct) + (vec_cond_direct, scatter_store_direct, len_store_direct) + (vec_set_direct, unary_direct, binary_direct, ternary_direct) + (cond_unary_direct, cond_binary_direct, cond_ternary_direct) + (while_direct, fold_extract_direct, fold_left_direct) + (mask_fold_left_direct, check_ptrs_direct): Use the macros above. + (expand_GOMP_SIMT_ENTER_ALLOC, expand_GOMP_SIMT_EXIT): Delete + (expand_GOMP_SIMT_LANE, expand_GOMP_SIMT_LAST_LANE): Likewise; + (expand_GOMP_SIMT_ORDERED_PRED, expand_GOMP_SIMT_VOTE_ANY): Likewise. + (expand_GOMP_SIMT_XCHG_BFLY, expand_GOMP_SIMT_XCHG_IDX): Likewise. + (direct_internal_fn_types): Handle functions that map to instructions + defined in target-insns.def. + (direct_internal_fn_types): Likewise. + (direct_internal_fn_supported_p): Likewise. + (internal_fn_expanders): Likewise. + +2022-06-13 Richard Sandiford <richard.sandiford@arm.com> + + * internal-fn.cc (expand_fn_using_insn): New function, + split out and adapted from... + (expand_direct_optab_fn): ...here. + (expand_GOMP_SIMT_ENTER_ALLOC): Use it. + (expand_GOMP_SIMT_EXIT): Likewise. + (expand_GOMP_SIMT_LANE): Likewise. + (expand_GOMP_SIMT_LAST_LANE): Likewise. + (expand_GOMP_SIMT_ORDERED_PRED): Likewise. + (expand_GOMP_SIMT_VOTE_ANY): Likewise. + (expand_GOMP_SIMT_XCHG_BFLY): Likewise. + (expand_GOMP_SIMT_XCHG_IDX): Likewise. + +2022-06-13 Jakub Jelinek <jakub@redhat.com> + + * omp-expand.cc (expand_omp_target): Remap user provided + device clause arguments, -1 to -2 and -2 to -3, either + at compile time if constant, or at runtime. + +2022-06-13 Eric Botcazou <ebotcazou@adacore.com> + + * common.opt (finstrument-functions): Set explicit value. + (-finstrument-functions-once): New option. + * doc/invoke.texi (Program Instrumentation Options): Document it. + * gimplify.cc (build_instrumentation_call): New static function. + (gimplify_function_tree): Call it to emit the instrumentation calls + if -finstrument-functions[-once] is specified. + +2022-06-13 Eric Botcazou <ebotcazou@adacore.com> + + * dwarf2out.cc (output_one_line_info_table): Initialize prev_addr. + * gimple.h (gimple_set_location): Do not copy warning data from + the previous location when it is UNKNOWN_LOCATION. + * optabs.cc (expand_widen_pattern_expr): Always set oprnd{1,2}. + +2022-06-13 Jakub Jelinek <jakub@redhat.com> + + PR target/105911 + * config/i386/i386.md (*ashl<dwi>3_doubleword_mask, + *<insn><dwi>3_doubleword_mask): Use operands[3] masked with + (<MODE_SIZE> * BITS_PER_UNIT) - 1 as AND operand instead of + operands[3] unmodified. + +2022-06-12 Simon Wright <simon@pushface.org> + + PR target/104871 + * config/darwin-driver.cc (darwin_find_version_from_kernel): If the OS + version is darwin20 (macOS 11) or greater, truncate the version to the + major number. + +2022-06-12 Mark Mentovai <mark@mentovai.com> + + * config/darwin-c.cc: Make -mmacosx-version-min more future-proof. + +2022-06-12 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> + + PR target/96463 + * config/aarch64/aarch64-sve-builtins-base.cc: Include ssa.h. + (svld1rq_impl::fold): Define. + * config/aarch64/aarch64.cc (expand_vec_perm_d): Define new members + op_mode and op_vec_flags. + (aarch64_evpc_reencode): Initialize newd.op_mode and + newd.op_vec_flags. + (aarch64_evpc_sve_dup): New function. + (aarch64_expand_vec_perm_const_1): Gate existing calls to + aarch64_evpc_* functions under d->vmode == d->op_mode, + and call aarch64_evpc_sve_dup. + (aarch64_vectorize_vec_perm_const): Remove assert + d->vmode != d->op_mode, and initialize d.op_mode and d.op_vec_flags. + * tree-cfg.cc (verify_gimple_assign_ternary): Allow different + vector types for lhs and rhs in VEC_PERM_EXPR if rhs3 is + constant. + +2022-06-11 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa-protos.h (xtensa_constantsynth): + New prototype. + * config/xtensa/xtensa.cc (xtensa_emit_constantsynth, + xtensa_constantsynth_2insn, xtensa_constantsynth_rtx_SLLI, + xtensa_constantsynth_rtx_ADDSUBX, xtensa_constantsynth): + New backend functions that process the abovementioned logic. + (xtensa_emit_move_sequence): Revert the previous changes. + * config/xtensa/xtensa.md: New split patterns for integer + and floating-point, as the frontend part. + +2022-06-11 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.cc (xtensa_rtx_costs): Correct wrong case + for ABS and NEG, add missing case for BSWAP and CLRSB, and + double the costs for integer divisions using libfuncs if + optimizing for speed, in order to take advantage of fast constant + division by multiplication. + (TARGET_INSN_COST): New macro definition. + (xtensa_is_insn_L32R_p, xtensa_insn_cost): New functions for + calculating relative costs of a RTL insns, for both of speed and + size. + * config/xtensa/xtensa.md (return, nop, trap): Correct values of + the attribute "length" that depends on TARGET_DENSITY. + (define_asm_attributes, blockage, frame_blockage): Add missing + attributes. + * config/xtensa/xtensa.opt (-mextra-l32r-costs=): New machine- + dependent option, however, preparatory work for now. + +2022-06-11 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.cc (xtensa_expand_block_set_small_loop): + Pass through the block length / loop count conditions if + zero-overhead looping is configured and active, + +2022-06-11 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md (mulsidi3, umulsidi3): + Split into individual signedness, in order to use libcall + "__umulsidi3" but not the other. + (<u>mulhisi3): Merge into one by using code iterator. + (<u>mulsidi3, mulhisi3, umulhisi3): Remove. + +2022-06-11 Michael Meissner <meissner@linux.ibm.com> + + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Do + not generate block copies with vector pair instructions if we are + tuning for power10. + +2022-06-10 Roger Sayle <roger@nextmovesoftware.com> + + PR rtl-optimization/7061 + * expr.cc (emit_group_store): For groups that consist of a single + scalar integer register that hold a complex mode value, use + gen_lowpart to generate a SUBREG to "view_convert" to the complex + mode. For modes of different sizes, first convert to an integer + mode of the appropriate size. + +2022-06-09 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md (clrsbsi2): New insn pattern. + +2022-06-09 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md (*andsi3_bitcmpl): + New insn_and_split pattern. + +2022-06-09 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md (one_cmplsi2): + Rearrange as an insn_and_split pattern. + +2022-06-09 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md (bswaphi2): New insn pattern. + +2022-06-09 Segher Boessenkool <segher@kernel.crashing.org> + + * config/rs6000/rs6000.md (FP_ISA3): Delete. + (float<QHI:mode><FP_ISA3:mode>2): Rename to... + (float<QHI:mode><SFDF:mode>2): ... this. Adjust. + (*float<QHI:mode><FP_ISA3:mode>2_internal): Rename to... + (*float<QHI:mode><SFDF:mode>2_internal): ... this. Adjust. + (floatuns<QHI:mode><FP_ISA3:mode>2): Rename to... + (floatuns<QHI:mode><SFDF:mode>2): ... this. Adjust. + (*floatuns<QHI:mode><FP_ISA3:mode>2_internal): Rename to... + (*floatuns<QHI:mode><SFDF:mode>2_internal): ... this. Adjust. + +2022-06-09 Maciej W. Rozycki <macro@embecosm.com> + + * config/riscv/riscv.md + (*f<quiet_pattern>_quiet<ANYF:mode><X:mode>4_default) + (*f<quiet_pattern>_quiet<ANYF:mode><X:mode>4_snan): Emit a tab + rather than space with FSFLAGS. + +2022-06-09 Tobias Burnus <tobias@codesourcery.com> + + * omp-offload.cc (omp_discover_declare_target_tgt_fn_r, + omp_discover_declare_target_fn_r): Don't walk reverse-offload + target regions. + +2022-06-09 Jakub Jelinek <jakub@redhat.com> + + * doc/invoke.texi (-Waddress): Fix a typo in small example. + Fix typos inptr_t -> intptr_t and uinptr_t -> uintptr_t. + +2022-06-09 Cui,Lili <lili.cui@intel.com> + + PR target/105493 + * config/i386/x86-tune-costs.h (skylake_cost): Raise the gpr load cost + from 4 to 6 and gpr store cost from 6 to 8. Change SSE loads and + unaligned loads cost from {6, 6, 6, 10, 20} to {8, 8, 8, 8, 16}. + (icelake_cost): Ditto. + (alderlake_cost): Raise the gpr store cost from 6 to 8 and SSE loads, + stores and unaligned stores cost from {6, 6, 6, 10, 15} to + {8, 8, 8, 10, 15}. + +2022-06-09 Haochen Gui <guihaoc@gcc.gnu.org> + + * config/rs6000/rs6000.md (define_split for bswapdi load): Merge shift + and ior insns to one rotate and mask insn. + (define_split for bswapdi register): Likewise. + +2022-06-08 Roger Sayle <roger@nextmovesoftware.com> + + PR middle-end/105874 + * expr.cc (expand_expr_real_1) <normal_inner_ref>: New local + variable tem_modifier for calculating the expand_modifier enum to + use for expanding tem. If tem is a VAR_DECL, use EXPAND_MEMORY. + +2022-06-08 Max Filippov <jcmvbkbc@gmail.com> + + PR target/105879 + * config/xtensa/xtensa.md (movdi): Rename 'first' and 'second' + to 'lowpart' and 'highpart' so that they match 'gen_lowpart' and + 'gen_highpart' bitwise semantics and fix order of highpart and + lowpart depending on target endianness. + +2022-06-08 Chung-Ju Wu <jasonwucj@gmail.com> + + * config/arm/arm-cpus.in (star-mc1): New cpu. + * config/arm/arm-tables.opt: Regenerate. + * config/arm/arm-tune.md: Regenerate. + * doc/invoke.texi: Update docs. + +2022-06-08 liuhongt <hongtao.liu@intel.com> + + PR target/105513 + PR target/105504 + * config/i386/i386.md (*movsi_internal): Change alternative + from *v to ?v. + (*movdi_internal): Ditto. + * config/i386/sse.md (vec_set<mode>_0): Change alternative *r + to ?r. + (*vec_extractv4sf_mem): Ditto. + (*vec_extracthf): Ditto. + +2022-06-07 Richard Earnshaw <rearnsha@arm.com> + + PR target/105090 + * config/arm/arm.cc (arm_bfi_1_p): New function. + (arm_bfi_p): New function. + (arm_rtx_costs_internal): Add costs for BFI idioms. + (arm_print_operand [case 'V']): Format output for BFI/BFC masks. + * config/arm/constraints.md (Dj): New constraint. + * config/arm/arm.md (arm_andsi3_insn): Add alternative to use BFC. + (insv_zero): Convert to an insn with a split. + (*bfi, *bfi_alt1, *bfi_alt2, *bfi_alt3): New patterns. + +2022-06-07 liuhongt <hongtao.liu@intel.com> + + PR target/105854 + * config/i386/sse.md (ssse3_palignrdi): Change alternative 2 + from Yv to Yw. + +2022-06-07 Roger Sayle <roger@nextmovesoftware.com> + + PR middle-end/105853 + PR target/105856 + * calls.cc (load_register_parameters): Call store_constructor + and int_expr_size directly instead of expanding via expand_expr. + * expr.cc (static void store_constructor): Don't prototype here. + (static HOST_WIDE_INT int_expr_size): Likewise. + (store_constructor): No longer static. + (int_expr_size): Likewise, no longer static. + * expr.h (store_constructor): Prototype here. + (int_expr_size): Prototype here. + +2022-06-07 Jan Beulich <jbeulich@suse.com> + + Revert: + 2022-06-03 Jan Beulich <jbeulich@suse.com> + + * Makefile.in (ORIGINAL_OBJCOPY_FOR_TARGET): New. + * configure.ac: Check for objcopy, producing + ORIGINAL_OBJCOPY_FOR_TARGET. + * configure: Update accordingly. + * exec-tool.in (ORIGINAL_OBJCOPY_FOR_TARGET): New. + Handle objcopy. + +2022-06-07 Jakub Jelinek <jakub@redhat.com> + + * tree.h (OMP_CLAUSE_LINEAR_OLD_LINEAR_MODIFIER): Define. + * tree-pretty-print.cc (dump_omp_clause) <case OMP_CLAUSE_LINEAR>: + Adjust clause printing style depending on + OMP_CLAUSE_LINEAR_OLD_LINEAR_MODIFIER. + +2022-06-07 Jan Beulich <jbeulich@suse.com> + + * config/i386/i386-builtin.def (__builtin_ia32_psadbw256): + Change type. + * config/i386/i386-builtin-types.def: New function type + (V4DI, V32QI, V32QI). + * config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle + V4DI_FTYPE_V32QI_V32QI. + +2022-06-07 Jan Beulich <jbeulich@suse.com> + + * config/i386/i386.cc (ix86_attr_length_vex_default): Take REX.B + into account for reg-only insns. + +2022-06-07 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/i386.cc (ix86_rtx_costs): Add a new case for + IF_THEN_ELSE, and provide costs for TARGET_XOP's vpcmov and + TARGET_CMOVE's (scalar integer) conditional moves. + * config/i386/sse.md (define_split): Recognize XOP's vpcmov + from its equivalent (canonical) pxor;pand;pxor sequence. + +2022-06-07 Kewen Lin <linkw@linux.ibm.com> + + * machmode.def (VECTOR_MODES_WITH_PREFIX): Update document for + parameter ORDER. + +2022-06-06 Andrew Stubbs <ams@codesourcery.com> + + * config.in: Regenerate. + * configure: Regenerate. + * configure.ac: Reinstate HAVE_GAS_ARM_EXTENDED_ARCH test. + +2022-06-04 Roger Sayle <roger@nextmovesoftware.com> + + PR middle-end/95126 + * calls.cc (load_register_parameters): When loading a suitable + immediate_const_ctor_p VAR_DECL into a single word_mode register, + construct it directly in a pseudo rather than read it (by parts) + from memory. + * expr.cc (int_expr_size): Make tree argument a const_tree. + (immediate_const_ctor_p): Helper predicate. Return true for + simple constructors that may be materialized in a register. + (expand_expr_real_1) [VAR_DECL]: When expanding a constant + VAR_DECL with a suitable immediate_const_ctor_p constructor + use store_constructor to materialize it directly in a pseudo. + * expr.h (immediate_const_ctor_p): Prototype here. + * varasm.cc (initializer_constant_valid_for_bitfield_p): Change + VALUE argument from tree to const_tree. + * varasm.h (initializer_constant_valid_for_bitfield_p): Update + prototype. + +2022-06-04 Jakub Jelinek <jakub@redhat.com> + + PR target/105825 + * config/i386/i386.md (*ashl<dwi>3_doubleword_mask, + *<insn><dwi>3_doubleword_mask): If top bit of mask is clear, but lower + bits of mask aren't all set, use operands[2] mode for the AND + operation instead of always SImode. + +2022-06-03 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/30314 + PR middle-end/105777 + * match.pd (__builtin_mul_overflow_p (x, cst, (stype) 0) -> + x > stype_max / cst || x < stype_min / cst): New simplification. + +2022-06-03 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-cache.cc (ranger_cache::range_from_dom): Use + Value_Range. + * gimple-range.cc (gimple_ranger::register_inferred_ranges): Same. + * value-range.h (Value_Range::Value_Range): Implement copy + constructor for Value_Range. + +2022-06-03 Aldy Hernandez <aldyh@redhat.com> + + * value-range.h (struct vrange_traits): Remove. + (is_a): Rewrite without vrange_traits. + (as_a): Same. + +2022-06-03 Aldy Hernandez <aldyh@redhat.com> + + * value-range.cc (vrange::contains_p): Implement. + (vrange::type): Return void. + (vrange::supports_type_p): Implement. + (irange::fits_p): Same. + (vrange::set_undefined): Same. + (irange::set_nonnegative): Same. + (vrange::set_varying): Same. + (vrange::union_): Same. + (unsupported_range::set): Move to vrange. + (unsupported_range::type): Move to vrange. + (vrange::intersect): Implement for varying and undefined. + (vrange::zero_p): Implement. + (unsupported_range::supports_type_p): Move to vrange. + (vrange::nonzero_p): Implement. + (unsupported_range::set_undefined): Move to vrange. + (unsupported_range::set_varying): Same. + (unsupported_range::dump): Same. + (unsupported_range::union_): Same. Implement for varying and + undefined. + (unsupported_range::intersect): Move to vrange. + (unsupported_range::zero_p): Same. + (unsupported_range::nonzero_p): Same. + (unsupported_range::set_nonzero): Same. + (unsupported_range::set_zero): Same. + (unsupported_range::set_nonnegative): Same. + (unsupported_range::fits_p): Same. + * value-range.h (class vrange): Remove abstract markers for most + methods. + (class unsupported_range): Remove most methods as they will now be + inherited from vrange. + +2022-06-03 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-edge.cc (gimple_outgoing_range_stmt_p): Adjust for + an object level supports_type_p for irange and a static + Value_Range::supports_type_p. + * gimple-range-fold.cc (fold_using_range::range_of_range_op): Same. + (fold_using_range::range_of_address): Same. + (fold_using_range::range_of_builtin_call): Same. + * gimple-range-fold.h (gimple_range_type): Same. + (gimple_range_ssa_p): Same. + * gimple-range-path.cc (path_range_query::internal_range_of_expr): + Same. + (path_range_query::range_of_stmt): Same. + (path_range_query::add_to_imports): Same. + * gimple-range.cc (gimple_ranger::range_on_edge): Same. + (gimple_ranger::export_global_ranges): Same. + * gimple-ssa-evrp-analyze.cc + (evrp_range_analyzer::record_ranges_from_phis): Same. + * range-op.cc (range_operator::wi_fold): Same. + (range_operator::fold_range): Same. + * tree-ssa-loop-ch.cc (entry_loop_condition_is_static): Same. + * tree-ssa-loop-unswitch.cc (struct unswitch_predicate): Same. + (evaluate_control_stmt_using_entry_checks): Same. + * tree-ssa-threadedge.cc + (hybrid_jt_simplifier::compute_ranges_from_state): Same. + * tree-vrp.cc (supported_types_p): Same. + * value-query.cc (range_query::value_of_expr): Same. + (range_query::value_on_edge): Same. + (range_query::value_of_stmt): Same. + (range_query::get_tree_range): Same. + (get_range_global): Same. + (global_range_query::range_of_expr): Same. + * value-range-equiv.h (class value_range_equiv): Same. + * value-range.cc (irange::supports_type_p): Same. + (unsupported_range::supports_type_p): Same. + * value-range.h (enum value_range_discriminator): Same. + (Value_Range::init): Same. + (Value_Range::supports_type_p): Same. + (irange::supports_type_p): Same. + (irange::supports_p): Same. + (vrange::supports_type_p): Same. + (vrange_allocator::alloc_vrange): Same. + +2022-06-03 Jan Beulich <jbeulich@suse.com> + + * Makefile.in (ORIGINAL_OBJCOPY_FOR_TARGET): New. + * configure.ac: Check for objcopy, producing + ORIGINAL_OBJCOPY_FOR_TARGET. + * configure: Update accordingly. + * exec-tool.in (ORIGINAL_OBJCOPY_FOR_TARGET): New. + Handle objcopy. + +2022-06-03 Jan Beulich <jbeulich@suse.com> + + * config/i386/mmx.md (mmx_psadbw): Convert to expander. + (*mmx_psadbw): New. Mark as commutative. + * config/i386/sse.md (<sse2_avx2>_psadbw): Convert to expander. + (*<sse2_avx2>_psadbw): New. Mark as commutative. + +2022-06-03 Alexandre Oliva <oliva@adacore.com> + + PR tree-optimization/105665 + PR tree-optimization/100810 + * tree-ssa-loop-ivopts.cc + (ssa_name_maybe_undef_p, ssa_name_set_maybe_undef): New. + (ssa_name_any_use_dominates_bb_p, mark_ssa_maybe_undefs): New. + (find_ssa_undef): Check precomputed flag and intervening uses. + (tree_ssa_iv_optimize): Call mark_ssa_maybe_undefs. + +2022-06-02 David Malcolm <dmalcolm@redhat.com> + + * Makefile.in (OBJS): Add tree-diagnostic-client-data-hooks.o and + tree-logical-location.o. + (OBJS-libcommon): Add diagnostic-format-sarif.o; reorder. + (CFLAGS-tree-diagnostic-client-data-hooks.o): Add TARGET_NAME. + * common.opt (fdiagnostics-format=): Add sarif-stderr and sarif-file. + (sarif-stderr, sarif-file): New enum values. + * diagnostic-client-data-hooks.h: New file. + * diagnostic-format-sarif.cc: New file. + * diagnostic-path.h (enum diagnostic_event::verb): New enum. + (enum diagnostic_event::noun): New enum. + (enum diagnostic_event::property): New enum. + (struct diagnostic_event::meaning): New struct. + (diagnostic_event::get_logical_location): New vfunc. + (diagnostic_event::get_meaning): New vfunc. + (simple_diagnostic_event::get_logical_location): New vfunc impl. + (simple_diagnostic_event::get_meaning): New vfunc impl. + * diagnostic.cc: Include "diagnostic-client-data-hooks.h". + (diagnostic_initialize): Initialize m_client_data_hooks. + (diagnostic_finish): Clean up m_client_data_hooks. + (diagnostic_event::meaning::dump_to_pp): New. + (diagnostic_event::meaning::maybe_get_verb_str): New. + (diagnostic_event::meaning::maybe_get_noun_str): New. + (diagnostic_event::meaning::maybe_get_property_str): New. + (get_cwe_url): Make non-static. + (diagnostic_output_format_init): Handle + DIAGNOSTICS_OUTPUT_FORMAT_SARIF_STDERR and + DIAGNOSTICS_OUTPUT_FORMAT_SARIF_FILE. + * diagnostic.h (enum diagnostics_output_format): Add + DIAGNOSTICS_OUTPUT_FORMAT_SARIF_STDERR and + DIAGNOSTICS_OUTPUT_FORMAT_SARIF_FILE. + (class diagnostic_client_data_hooks): New forward decl. + (class logical_location): New forward decl. + (diagnostic_context::m_client_data_hooks): New field. + (diagnostic_output_format_init_sarif_stderr): New decl. + (diagnostic_output_format_init_sarif_file): New decl. + (get_cwe_url): New decl. + * doc/invoke.texi (-fdiagnostics-format=): Add sarif-stderr and + sarif-file. + * doc/sourcebuild.texi (Scan a particular file): Add + scan-sarif-file and scan-sarif-file-not. + * langhooks-def.h (lhd_get_sarif_source_language): New decl. + (LANG_HOOKS_GET_SARIF_SOURCE_LANGUAGE): New macro. + (LANG_HOOKS_INITIALIZER): Add + LANG_HOOKS_GET_SARIF_SOURCE_LANGUAGE. + * langhooks.cc (lhd_get_sarif_source_language): New. + * langhooks.h (lang_hooks::get_sarif_source_language): New field. + * logical-location.h: New file. + * plugin.cc (struct for_each_plugin_closure): New. + (for_each_plugin_cb): New. + (for_each_plugin): New. + * plugin.h (for_each_plugin): New decl. + * tree-diagnostic-client-data-hooks.cc: New file. + * tree-diagnostic.cc: Include "diagnostic-client-data-hooks.h". + (tree_diagnostics_defaults): Populate m_client_data_hooks. + * tree-logical-location.cc: New file. + * tree-logical-location.h: New file. + +2022-06-02 David Malcolm <dmalcolm@redhat.com> + + * common.opt (fdiagnostics-format=): Add json-stderr and json-file + to description. + (DIAGNOSTICS_OUTPUT_FORMAT_JSON): Rename to... + (DIAGNOSTICS_OUTPUT_FORMAT_JSON_STDERR): ...this. + (diagnostics_output_format): Add json-stderr and json-file. + * diagnostic-format-json.cc (json_flush_to_file): New. + (json_final_cb): Convert to... + (json_flush_to_file): ...this, ... + (json_stderr_final_cb): ...this, and... + (json_file_final_cb): ...this. + (diagnostic_output_format_init): Move to diagnostic.cc. + (json_output_base_file_name): New. + (diagnostic_output_format_init_json): New. + (diagnostic_output_format_init_json_stderr): New. + (diagnostic_output_format_init_json_file): New. + * diagnostic.cc (diagnostic_output_format_init): Move here from + diagnostic-format-json.cc; update for changes to enum. + * diagnostic.h (enum diagnostics_output_format): Rename + DIAGNOSTICS_OUTPUT_FORMAT_JSON to + DIAGNOSTICS_OUTPUT_FORMAT_JSON_STDERR, and add + DIAGNOSTICS_OUTPUT_FORMAT_JSON_FILE. + (diagnostic_output_format_init): Add base_file_name param. + (diagnostic_output_format_init_json_stderr): New decl. + (diagnostic_output_format_init_json_file): New dec. + * doc/invoke.texi (-fdiagnostics-format=): Add "json-stderr" and + "json-file". Rewrite so that the existing "json" is a synonym of + "json-stderr". + * gcc.cc (driver_handle_option): Pass dump_base_name to + diagnostic_output_format_init. + * opts.cc (common_handle_option): Likewise. + +2022-06-02 David Malcolm <dmalcolm@redhat.com> + + * json.cc (string::print): Fix escaping of '\'. + +2022-06-02 Philipp Tomsich <philipp.tomsich@vrull.eu> + + * config/riscv/riscv.cc (riscv_build_integer_1): Rewrite value as + (-1 << 31) for the single-bit case, when operating on (1 << 31) + in SImode. + * config/riscv/riscv.h (SINGLE_BIT_MASK_OPERAND): Allow for + any single-bit value, moving the special case for (1 << 31) to + riscv_build_integer_1 (in riscv.c). + +2022-06-02 Roger Sayle <roger@nextmovesoftware.com> + + PR target/105791 + * config/i386/sse.md (V_128_256):Add V1TI and V2TI. + (define_mode_attr avxsizesuffix): Add support for V1TI and V2TI. + +2022-06-02 Jakub Jelinek <jakub@redhat.com> + + PR target/105778 + * config/i386/i386.md (*ashl<dwi>3_doubleword_mask): Remove :SI + from AND and its operands and just verify operands[2] has HImode, + SImode or for TARGET_64BIT DImode. Allow operands[3] to be a mask + with all low 6 (64-bit) or 5 (32-bit) bits set and in that case + just throw away the masking. Use force_reg before calling + gen_lowpart. + (*ashl<dwi>3_doubleword_mask_1): Allow operands[3] to be a mask + with all low 6 (64-bit) or 5 (32-bit) bits set and in that case + just throw away the masking. + (*ashl<mode>3_doubleword): Rename to ... + (ashl<mode>3_doubleword): ... this. + (*ashl<mode>3_mask): Remove :SI from AND and its operands and just + verify operands[2] has HImode, SImode or for TARGET_64BIT DImode. + Use force_reg before calling gen_lowpart. + (*<insn><mode>3_mask): Likewise. + (*<insn><dwi>3_doubleword_mask): Likewise. Allow operands[3] to be + a mask with all low 6 (64-bit) or 5 (32-bit) bits set and in that + case just throw away the masking. Use force_reg before calling + gen_lowpart. + (*<insn><dwi>3_doubleword_mask_1): Allow operands[3] to be a mask + with all low 6 (64-bit) or 5 (32-bit) bits set and in that case just + throw away the masking. + (*<insn><mode>3_doubleword): Rename to ... + (<insn><mode>3_doubleword): ... this. + (*<insn><mode>3_mask): Remove :SI from AND and its operands and just + verify operands[2] has HImode, SImode or for TARGET_64BIT DImode. + Use force_reg before calling gen_lowpart. + (splitter after it): Remove :SI from AND and its operands and just + verify operands[2] has HImode, SImode or for TARGET_64BIT DImode. + (*<btsc><mode>_mask, *<btsc><mode>_mask): Remove :SI from AND and its + operands and just verify operands[1] has HImode, SImode or for + TARGET_64BIT DImode. Use force_reg before calling gen_lowpart. + (*jcc_bt<mode>_mask_1): New define_insn_and_split pattern. + * config/i386/i386.cc (ix86_rtx_costs): For ZERO_EXTRACT with + ZERO_EXTEND QI->SI in last operand ignore the cost of the ZERO_EXTEND. + +2022-06-02 Richard Biener <rguenther@suse.de> + + PR tree-optimization/101668 + * tree-vect-slp.cc (vect_build_slp_tree_1): Allow BIT_FIELD_REFs + for vector types with compatible lane types. + (vect_build_slp_tree_2): Deal with this. + (vect_add_slp_permutation): Adjust. Emit lowpart/concat + special cases without VEC_PERM. + (vectorizable_slp_permutation): Select the operand vector + type and relax requirements. Handle identity permutes + with mismatching operand types. + * optabs-query.cc (can_vec_perm_const_p): Only allow variable + permutes for op_mode == mode. + +2022-06-02 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105802 + * tree-ssa-loop-unswitch.cc (find_unswitching_predicates_for_bb): + Make sure to also compute the range in the type of the switch index. + +2022-06-01 David Seifert <soap@gentoo.org> + + PR plugins/95648 + * configure: Regenerate. + +2022-06-01 H.J. Lu <hjl.tools@gmail.com> + + PR rtl-optimization/105638 + * df-core.cc (df_find_single_def_src): Moved and renamed from + find_single_def_src in loop-iv.cc. Change the argument to rtx + and use rtx_equal_p. Return null for partial or conditional + defs. + * df.h (df_find_single_def_src): New prototype. + * dse.cc (record_store): Use the constant source if the source + register is set only once. + * loop-iv.cc (find_single_def_src): Moved to df-core.cc. + (replace_single_def_regs): Replace find_single_def_src with + df_find_single_def_src. + +2022-06-01 Wilco Dijkstra <wilco.dijkstra@arm.com> + + * config/aarch64/aarch64.opt (explicit_tune_core): Rename to + selected_tune. + (explicit_arch): Rename to selected_arch. + (x_aarch64_override_tune_string): Remove. + (aarch64_ra_sign_key): Add as TargetVariable so it gets saved/restored. + (aarch64_override_tune_string): Add Save so it gets saved/restored. + * config/aarch64/aarch64.h (aarch64_architecture_version): Remove. + * config/aarch64/aarch64.cc (aarch64_architecture_version): Remove. + (processor): Remove archtecture_version field. + (selected_arch): Remove global. + (selected_cpu): Remove global. + (selected_tune): Remove global. + (aarch64_ra_sign_key): Move global to aarch64.opt so it is saved. + (aarch64_override_options_internal): Use aarch64_get_tune_cpu. + (aarch64_override_options): Further simplify code to only set + selected_arch and selected_tune globals. + (aarch64_option_save): Remove now that target options are saved. + (aarch64_option_restore): Remove redundant target option restores. + * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Use + AARCH64_ISA_V9. + * config/aarch64/aarch64-opts.h (aarch64_key_type): Add, moved from... + * config/aarch64/aarch64-protos.h (aarch64_key_type): Remove. + (aarch64_ra_sign_key): Remove. + +2022-06-01 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/30314 + * match.pd (__builtin_mul_overflow_p (x, cst, (utype) 0) -> + x > ~(utype)0 / cst): New simplification. + +2022-06-01 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105786 + * tree-loop-distribution.cc + (loop_distribution::transform_reduction_loop): Only do strlen + replacement for integer type reductions. + +2022-06-01 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/105770 + * tree-ssa-loop-unswitch.cc (find_unswitching_predicates_for_bb): Cast + CASE_LOW and CASE_HIGH to TREE_TYPE (idx) before comparisons with idx. + +2022-06-01 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-cache.cc (ssa_block_ranges::dump): Convert to vrange. + (sbr_vector::sbr_vector): Same. + (sbr_vector::grow): Same. + (sbr_vector::set_bb_range): Same. + (sbr_vector::get_bb_range): Same. + (sbr_sparse_bitmap::sbr_sparse_bitmap): Same. + (sbr_sparse_bitmap::set_bb_range): Same. + (sbr_sparse_bitmap::get_bb_range): Same. + (block_range_cache::set_bb_range): Same. + (block_range_cache::get_bb_range): Same. + (block_range_cache::dump): Same. + (ssa_global_cache::get_global_range): Same. + (ssa_global_cache::set_global_range): Same. + (ssa_global_cache::clear): Same. + (ssa_global_cache::dump): Same. + (ranger_cache::get_global_range): Same. + (ranger_cache::set_global_range): Same. + (ranger_cache::range_of_def): Same. + (ranger_cache::entry_range): Same. + (ranger_cache::exit_range): Same. + (ranger_cache::edge_range): Same. + (ranger_cache::range_of_expr): Same. + (ranger_cache::range_on_edge): Same. + (ranger_cache::block_range): Same. + (ranger_cache::propagate_cache): Same. + (ranger_cache::fill_block_cache): Same. + (ranger_cache::range_from_dom): Same. + * gimple-range-cache.h: Same. + * gimple-range-edge.cc (gimple_outgoing_range::get_edge_range): + Same. + (gimple_outgoing_range::switch_edge_range): Same. + (gimple_outgoing_range::edge_range_p): Same. + * gimple-range-edge.h: Same. + * gimple-range-fold.cc (fur_source::get_operand): Same. + (fur_source::get_phi_operand): Same. + (fur_edge::get_operand): Same. + (fur_edge::get_phi_operand): Same. + (fur_stmt::get_operand): Same. + (fur_stmt::get_phi_operand): Same. + (fur_list::fur_list): Same. + (fur_list::get_operand): Same. + (fur_list::get_phi_operand): Same. + (fold_range): Same. + (adjust_imagpart_expr): Same. + (adjust_realpart_expr): Same. + (gimple_range_adjustment): Same. + (fold_using_range::fold_stmt): Same. + (fold_using_range::range_of_range_op): Same. + (fold_using_range::range_of_address): Same. + (fold_using_range::range_of_phi): Same. + (fold_using_range::range_of_call): Same. + (fold_using_range::range_of_builtin_call): Same. + (fold_using_range::range_of_builtin_int_call): Same. + (fold_using_range::range_of_cond_expr): Same. + (fur_source::register_outgoing_edges): Same. + * gimple-range-fold.h (fold_range): Same. + (gimple_range_type): Same. + (gimple_range_ssa_p): Same. + * gimple-range-gori.cc (gimple_range_calc_op1): Same. + (gimple_range_calc_op2): Same. + (gori_compute::compute_operand_range_switch): Same. + (gori_compute::compute_operand_range): Same. + (gori_compute::logical_combine): Same. + (gori_compute::compute_logical_operands): Same. + (gori_compute::compute_operand1_range): Same. + (gori_compute::compute_operand2_range): Same. + (gori_compute::compute_operand1_and_operand2_range): Same. + (gori_compute::outgoing_edge_range_p): Same. + (gori_compute::condexpr_adjust): Same. + * gimple-range-gori.h (gimple_range_calc_op1): Same. + (gimple_range_calc_op2): Same. + * gimple-range-path.cc (path_range_query::get_cache): Same. + (path_range_query::set_cache): Same. + (path_range_query::range_on_path_entry): Same. + (path_range_query::internal_range_of_expr): Same. + (path_range_query::range_of_expr): Same. + (path_range_query::ssa_range_in_phi): Same. + (path_range_query::range_defined_in_block): Same. + (path_range_query::compute_ranges_in_phis): Same. + (path_range_query::compute_ranges_in_block): Same. + (path_range_query::add_to_imports): Same. + (path_range_query::range_of_stmt): Same. + * gimple-range-path.h: Same. + * gimple-range-infer.cc (gimple_infer_range::add_range): Same. + (gimple_infer_range::~side_effect_manager): Same. + (gimple_infer_range::get_nonzero): Same. + (gimple_infer_range::maybe_adjust_range): Same. + (gimple_infer_range::add_range): Same. + * gimple-range-infer.h: Same. + * gimple-range-tests.cc: Same. + * gimple-range-trace.cc (range_tracer::trailer): Same. + (debug_seed_ranger): Same. + * gimple-range-trace.h: Same. + * gimple-range.cc (gimple_ranger::range_of_expr): Same. + (gimple_ranger::range_on_entry): Same. + (gimple_ranger::range_on_exit): Same. + (gimple_ranger::range_on_edge): Same. + (gimple_ranger::fold_range_internal): Same. + (gimple_ranger::range_of_stmt): Same. + (gimple_ranger::prefill_name): Same. + (gimple_ranger::prefill_stmt_dependencies): Same. + (gimple_ranger::export_global_ranges): Same. + (gimple_ranger::dump_bb): Same. + * gimple-range.h: Same. + * gimple-ssa-warn-access.cc (check_nul_terminated_array): Same. + (memmodel_to_uhwi): Same. + * tree-ssa-loop-niter.cc (refine_value_range_using_guard): Same. + (determine_value_range): Same. + (record_nonwrapping_iv): Same. + (infer_loop_bounds_from_signedness): Same. + (scev_var_range_cant_overflow): Same. + * tree-ssa-threadedge.cc (hybrid_jt_simplifier::simplify): Same. + * value-query.cc (range_query::range_on_edge): Same. + (range_query::range_of_stmt): Same. + (range_query::value_of_expr): Same. + (range_query::value_on_edge): Same. + (range_query::value_of_stmt): Same. + (range_query::get_tree_range): Same. + (update_global_range): Same. + (get_range_global): Same. + (gimple_range_global): Same. + (global_range_query::range_of_expr): Same. + (range_query::query_relation): Same. + * value-query.h (gimple_range_global): Same. + (update_global_range): Same. + * vr-values.cc (vr_values::range_of_expr): Same. + (bounds_of_var_in_loop): Same. + (simplify_using_ranges::vrp_visit_cond_stmt): Same. + * vr-values.h (class vr_values): Same. + * tree-ssa-loop-unswitch.cc (unswitch_predicate): Same. + +2022-06-01 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-cache.cc (sbr_vector::sbr_vector): Adjust for + vrange allocator. + (sbr_vector::grow): Same. + (sbr_vector::set_bb_range): Same. + (sbr_sparse_bitmap::sbr_sparse_bitmap): Same. + (sbr_sparse_bitmap::set_bb_range): Same. + (block_range_cache::~block_range_cache): Same. + (block_range_cache::set_bb_range): Same. + (ssa_global_cache::ssa_global_cache): Same. + (ssa_global_cache::~ssa_global_cache): Same. + (ssa_global_cache::set_global_range): Same. + * gimple-range-cache.h (block_range_cache): Same. + (ssa_global_cache): Same. + * gimple-range-edge.cc + (gimple_outgoing_range::calc_switch_ranges): Same. + * gimple-range-edge.h (gimple_outgoing_range): Same. + * gimple-range-infer.cc (infer_range_manager::get_nonzero): + Same. + (infer_range_manager::add_range): Same. + * gimple-range-infer.h (class infer_range_manager): Same. + * value-range.h (class irange_allocator): Rename to... + (class vrange_allocator): ...this. + (irange_allocator::irange_allocator): New. + (vrange_allocator::vrange_allocator): New. + (irange_allocator::~irange_allocator): New. + (vrange_allocator::~vrange_allocator): New. + (irange_allocator::get_memory): Rename to... + (vrange_allocator::alloc): ...this. + (vrange_allocator::alloc_vrange): Rename from... + (irange_allocator::allocate): ...this. + (vrange_allocator::alloc_irange): New. + +2022-06-01 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-edge.cc (gimple_outgoing_range_stmt_p): Adjust for + vrange and convert range_op_handler function calls to use the + identically named object. + * gimple-range-fold.cc (gimple_range_operand1): Same. + (gimple_range_operand2): Same. + (fold_using_range::fold_stmt): Same. + (fold_using_range::range_of_range_op): Same. + (fold_using_range::range_of_builtin_ubsan_call): Same. + (fold_using_range::relation_fold_and_or): Same. + (fur_source::register_outgoing_edges): Same. + * gimple-range-fold.h (gimple_range_handler): Remove. + * gimple-range-gori.cc (gimple_range_calc_op1): Adjust for vrange. + (gimple_range_calc_op2): Same. + (range_def_chain::get_def_chain): Same. + (gori_compute::compute_operand_range): Same. + (gori_compute::condexpr_adjust): Same. + * gimple-range.cc (gimple_ranger::prefill_name): Same. + (gimple_ranger::prefill_stmt_dependencies): Same. + * range-op.cc (get_bool_state): Same. + (class operator_equal): Add using clause. + (class operator_not_equal): Same. + (class operator_lt): Same. + (class operator_le): Same. + (class operator_gt): Same. + (class operator_ge): Same. + (class operator_plus): Same. + (class operator_minus): Same. + (class operator_mult): Same. + (class operator_exact_divide): Same. + (class operator_lshift): Same. + (class operator_rshift): Same. + (class operator_cast): Same. + (class operator_logical_and): Same. + (class operator_bitwise_and): Same. + (class operator_logical_or): Same. + (class operator_bitwise_or): Same. + (class operator_bitwise_xor): Same. + (class operator_trunc_mod): Same. + (class operator_logical_not): Same. + (class operator_bitwise_not): Same. + (class operator_cst): Same. + (class operator_identity): Same. + (class operator_unknown): Same. + (class operator_abs): Same. + (class operator_negate): Same. + (class operator_addr_expr): Same. + (class pointer_or_operator): Same. + (operator_plus::op1_range): Adjust for vrange. + (operator_minus::op1_range): Same. + (operator_mult::op1_range): Same. + (operator_cast::op1_range): Same. + (operator_bitwise_not::fold_range): Same. + (operator_negate::fold_range): Same. + (range_op_handler): Rename to... + (get_handler): ...this. + (range_op_handler::range_op_handler): New. + (range_op_handler::fold_range): New. + (range_op_handler::op1_range): New. + (range_op_handler::op2_range): New. + (range_op_handler::lhs_op1_relation): New. + (range_op_handler::lhs_op2_relation): New. + (range_op_handler::op1_op2_relation): New. + (range_cast): Adjust for vrange. + * range-op.h (range_op_handler): Remove function. + (range_cast): Adjust for vrange. + (class range_op_handler): New. + (get_bool_state): Adjust for vrange. + (empty_range_varying): Same. + (relop_early_resolve): Same. + * tree-data-ref.cc (compute_distributive_range): Same. + * tree-vrp.cc (get_range_op_handler): Remove. + (range_fold_binary_symbolics_p): Use range_op_handler class + instead of get_range_op_handler. + (range_fold_unary_symbolics_p): Same. + (range_fold_binary_expr): Same. + (range_fold_unary_expr): Same. + * value-query.cc (range_query::get_tree_range): Adjust for vrange. + +2022-06-01 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-fold.h (gimple_range_type): Check type before + calling supports_type_p. + * gimple-range-path.cc (path_range_query::range_of_stmt): Same. + * value-query.cc (range_query::get_tree_range): Same. + * value-range.cc (Value_Range::lower_bound): New. + (Value_Range::upper_bound): New. + (Value_Range::dump): New. + * value-range.h (class Value_Range): New. + (irange::supports_type_p): Do not check if type is non-zero. + +2022-06-01 Aldy Hernandez <aldyh@redhat.com> + + * value-range-equiv.cc (value_range_equiv::set): New. + * value-range-equiv.h (class value_range_equiv): Make set method + virtual. + Remove default bitmap argument from set method. + * value-range.cc (vrange::contains_p): New. + (vrange::singleton_p): New. + (vrange::operator=): New. + (vrange::operator==): New. + (irange::fits_p): Move to .cc file. + (irange::set_nonnegative): New. + (unsupported_range::unsupported_range): New. + (unsupported_range::set): New. + (unsupported_range::type): New. + (unsupported_range::set_undefined): New. + (unsupported_range::set_varying): New. + (unsupported_range::dump): New. + (unsupported_range::union_): New. + (unsupported_range::intersect): New. + (unsupported_range::zero_p): New. + (unsupported_range::nonzero_p): New. + (unsupported_range::set_nonzero): New. + (unsupported_range::set_zero): New. + (unsupported_range::set_nonnegative): New. + (unsupported_range::fits_p): New. + (irange::set): Call irange::set_undefined. + (irange::verify_range): Check discriminator field. + (irange::dump): Dump [irange] marker. + (irange::debug): Move to... + (vrange::debug): ...here. + (dump_value_range): Accept vrange. + (debug): Same. + * value-range.h (enum value_range_discriminator): New. + (class vrange): New. + (class unsupported_range): New. + (struct vrange_traits): New. + (is_a): New. + (as_a): New. + (class irange): Inherit from vrange. + (dump_value_range): Adjust for vrange. + (irange::kind): Rename to... + (vrange::kind): ...this. + (irange::varying_p): Rename to... + (vrange::varying_p): ...this. + (irange::undefined_p): Rename to... + (vrange::undefined_p): ...this. + (irange::irange): Set discriminator. + (irange::union_): Convert to irange before passing to irange + method. + (irange::intersect): Same. + (vrange::supports_type_p): New. + * vr-values.cc (vr_values::extract_range_from_binary_expr): Pass + NULL bitmap argument to value_range_equiv::set. + (vr_values::extract_range_basic): Same. + +2022-06-01 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105763 + * tree-ssa-loop-unswitch.cc (find_unswitching_predicates_for_bb): + Check gimple_range_ssa_p. + +2022-05-31 Jason Merrill <jason@redhat.com> + + * Makefile.in (TAGS): Look at libcpp/*.cc. + +2022-05-31 Christophe Lyon <christophe.lyon@arm.com> + + * config/aarch64/aarch64.cc (aarch64_gimplify_va_arg_expr): + Prefix mode names with E_. + +2022-05-31 Alan Modra <amodra@gmail.com> + + * dwarf2out.cc (gen_namelist_decl): Adjust to suit correct + spelling of DW_AT_namelist_item. + +2022-05-31 Jakub Jelinek <jakub@redhat.com> + + * omp-low.cc (build_outer_var_ref): For code == OMP_CLAUSE_ALLOCATE + allow var to be private in the outer context. + (lower_private_allocate): Pass OMP_CLAUSE_ALLOCATE as last argument + to build_outer_var_ref. + +2022-05-30 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/i386.cc (ix86_modes_tieable_p): Allow SCmode to be + tieable with DImode on TARGET_64BIT, and SCmode tieable with + V2SFmode, and DCmode with V2DFmode. + +2022-05-30 Roger Sayle <roger@nextmovesoftware.com> + + PR rtl-optimization/101617 + * config/i386/i386-expand.cc (ix86_expand_int_movcc): Add a + special case (indicated by negate_cc_compare_p) to generate a + -1/0 mask using neg;sbb. + * config/i386/i386.md (x86_neg<mode>_ccc): New define_expand + to generate an *x86_neg<mode>_ccc instruction. + (x86_mov<mode>cc_0_m1_neg): Likewise, a new define_expand to + generate a *x86_mov<mode>cc_0_m1_neg instruction. + +2022-05-30 Roger Sayle <roger@nextmovesoftware.com> + + * rtlanal.cc (rtx_cost) <MULT>: Treat FMA, SS_MULT, US_MULT, + SMUL_HIGHPART and UMUL_HIGHPART as having the same cost as MULT. + <DIV>: Likewise, SS_DIV and US_DIV have the same default as DIV. + +2022-05-30 Roger Sayle <roger@nextmovesoftware.com> + + PR target/70321 + * config/i386/i386-expand.cc (ix86_expand_branch): Don't decompose + DI mode equality/inequality using XOR here. Instead generate a + COMPARE for doubleword modes (DImode on !TARGET_64BIT or TImode). + * config/i386/i386-features.cc (gen_gpr_to_xmm_move_src): Use + gen_rtx_SUBREG when NUNITS is 1, i.e. for TImode to V1TImode. + (general_scalar_chain::convert_compare): New function to convert + scalar equality/inequality comparison into vector operations. + (general_scalar_chain::convert_insn) [COMPARE]: Refactor. Call + new convert_compare helper method. + (convertible_comparion_p): Update to match doubleword COMPARE + of two register, memory or integer constant operands. + * config/i386/i386-features.h (general_scalar_chain::convert_compare): + Prototype/declare member function here. + * config/i386/i386.md (cstore<mode>4): Change mode to SDWIM, but + only allow new doubleword modes for EQ and NE operators. + (*cmp<dwi>_doubleword): New define_insn_and_split, to split a + doubleword comparison into a pair of XORs followed by an IOR to + set the (zero) flags register, optimizing the XORs if possible. + * config/i386/sse.md (V_AVX): Include V1TI and V2TI in mode + iterator; V_AVX is (currently) only used by ptest. + (sse4_1 mode attribute): Update to support V1TI and V2TI. + +2022-05-30 Uroš Bizjak <ubizjak@gmail.com> + + * config/i386/i386.md: Remove constraints when used with + const_int_operand, const0_operand, const_1_operand, constm1_operand, + const8_operand, const128_operand, const248_operand, const123_operand, + const2367_operand, const1248_operand, const359_operand, + const_4_or_8_to_11_operand, const48_operand, const_0_to_1_operand, + const_0_to_3_operand, const_0_to_4_operand, const_0_to_5_operand, + const_0_to_7_operand, const_0_to_15_operand, const_0_to_31_operand, + const_0_to_63_operand, const_0_to_127_operand, const_0_to_255_operand, + const_0_to_255_mul_8_operand, const_1_to_31_operand, + const_1_to_63_operand, const_2_to_3_operand, const_4_to_5_operand, + const_4_to_7_operand, const_6_to_7_operand, const_8_to_9_operand, + const_8_to_11_operand, const_8_to_15_operand, const_10_to_11_operand, + const_12_to_13_operand, const_12_to_15_operand, const_14_to_15_operand, + const_16_to_19_operand, const_16_to_31_operand, const_20_to_23_operand, + const_24_to_27_operand and const_28_to_31_operand. + * config/i386/mmx.md: Ditto. + * config/i386/sse.md: Ditto. + * config/i386/subst.md: Ditto. + * config/i386/sync.md: Ditto. + +2022-05-30 Jan Beulich <jbeulich@suse.com> + + * config/i386/i386.md (bmi2_umul<mode><dwi>3_1): Correct MEM_P() + arguments. + +2022-05-30 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> + + * config/arm/arm.cc (arm_vectorize_vec_perm_const): Adjust prototype. + +2022-05-29 Iain Sandoe <iain@sandoe.co.uk> + + PR target/105599 + * config/darwin.h: Move versions-specific handling of multiply_defined + from SUBTARGET_DRIVER_SELF_SPECS to LINK_SPEC. + +2022-05-29 Eric Gallager <egallager@gcc.gnu.org> + + PR other/82383 + * doc/sourcebuild.texi: Add entries for the c++tools, + gotools, libbacktrace, libcc1, libcody, liboffloadmic, + and libsanitizer directories. Remove entry for boehm-gc. + Fix alphabetization for libquadmath. + +2022-05-28 Joel Holdsworth <jholdsworth@nvidia.com> + + * config/avr/avr-mcus.def: Add device definitions. + * doc/avr-mmcu.texi: Corresponding changes. + * config/avr/gen-avr-mmcu-texi.cc: Added support for avr + device prefix. + * config/avr/gen-avr-mmcu-specs.cc: Prevent -mmcu=avr* flags + from leaking into cc1. + +2022-05-28 Vladimir Makarov <vmakarov@gcc.gnu.org> + + PR target/103722 + * config/sh/sh.cc (sh_register_move_cost): Avoid cost "2" (which + is special) for various scenarios. + +2022-05-28 Iain Sandoe <iain@sandoe.co.uk> + + * config/darwin.h (REAL_LIBGCC_SPEC): Update the comment block + describing this macro. + +2022-05-27 Richard Biener <rguenther@suse.de> + + * tree-dfa.cc (get_ref_base_and_extent): Avoid shift. + +2022-05-27 Martin Jambor <mjambor@suse.cz> + + PR ipa/105639 + * ipa-prop.cc (propagate_controlled_uses): Check type of the + constant before adding a LOAD reference. + +2022-05-27 Jakub Jelinek <jakub@redhat.com> + + * tree-core.h (enum omp_clause_code): Rename OMP_CLAUSE_TO_DECLARE + to OMP_CLAUSE_ENTER. + * tree.h (OMP_CLAUSE_ENTER_TO): Define. + * tree.cc (omp_clause_num_ops, omp_clause_code_name): Rename + OMP_CLAUSE_TO_DECLARE to OMP_CLAUSE_ENTER. + * tree-pretty-print.cc (dump_omp_clause): Handle OMP_CLAUSE_ENTER + instead of OMP_CLAUSE_TO_DECLARE, if OMP_CLAUSE_ENTER_TO, print + "to" instead of "enter". + * tree-nested.cc (convert_nonlocal_omp_clauses, + convert_local_omp_clauses): Handle OMP_CLAUSE_ENTER instead of + OMP_CLAUSE_TO_DECLARE. + +2022-05-27 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105726 + * gimple-ssa-warn-restrict.cc (builtin_memref::set_base_and_offset): + Constrain array-of-flexarray case more. + +2022-05-27 Jakub Jelinek <jakub@redhat.com> + + PR sanitizer/105729 + * fold-const.cc (fold_unary_loc): Don't optimize (X &) ((Y *) z + w) + to (X &) z + w if -fsanitize=null during GENERIC folding. + +2022-05-27 Roger Sayle <roger@nextmovesoftware.com> + + * match.pd (match_zero_one_valued_p): New predicate. + (mult @0 @1): Use zero_one_valued_p for optimization to the + expression "bit_and @0 @1". + (bit_and (negate zero_one_valued_p@0) @1): Optimize to MULT_EXPR. + (plus @0 (mult (minus @1 @0) zero_one_valued_p@2)): New transform. + (minus @0 (mult (minus @0 @1) zero_one_valued_p@2)): Likewise. + (bit_xor @0 (mult (bit_xor @0 @1) zero_one_valued_p@2)): Likewise. + Remove three redundant transforms obsoleted by the three above. + +2022-05-27 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/i386.md (*test<mode>_not): New define_insn_and_split + to split a combined "and;cmp" sequence into "not;test". + +2022-05-27 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md (bswapsi2): New expansion pattern. + (bswapsi2_internal): Revise the template and condition, and add + detection code for preceding the same insn in order to omit a + "SSAI 8" instruction of the latter. + (bswapdi2): Suppress built-in insn expansion with the corresponding + library call when optimizing for size. + +2022-05-27 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa-protos.h + (xtensa_expand_block_set_unrolled_loop, + xtensa_expand_block_set_small_loop): New prototypes. + * config/xtensa/xtensa.cc (xtensa_sizeof_MOVI, + xtensa_expand_block_set_unrolled_loop, + xtensa_expand_block_set_small_loop): New functions. + * config/xtensa/xtensa.md (setmemsi): New expansion pattern. + * config/xtensa/xtensa.opt (mlongcalls): Add target mask. + +2022-05-26 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.cc (xtensa_expand_block_move): + Make instruction counting more accurate, and simplify emitting insns. + +2022-05-26 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/constraints.md (M, O): Use the macro. + * config/xtensa/predicates.md (addsubx_operand, extui_fldsz_operand, + sext_fldsz_operand): Ditto. + * config/xtensa/xtensa.cc (xtensa_simm8, xtensa_simm8x256, + xtensa_simm12b, xtensa_uimm8, xtensa_uimm8x2, xtensa_uimm8x4, + xtensa_mask_immediate, smalloffset_mem_p, printx, xtensa_call_save_reg, + xtensa_expand_prologue): Ditto. + * config/xtensa/xtensa.h (FUNCTION_ARG_REGNO_P): Ditto. + +2022-05-26 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/predicates.md (extui_fldsz_operand): Simplify. + * config/xtensa/xtensa.cc (xtensa_mask_immediate, print_operand): + Ditto. + +2022-05-25 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-cache.cc: Adjust comments. + * gimple-range-infer.cc: Adjust comments. + * gimple-range-infer.h: Adjust comments. + * gimple-range.cc: Adjust comments. + +2022-05-25 Andrew MacLeod <amacleod@redhat.com> + + * Makefile.in (OBJS): Use gimple-range-infer.o. + * gimple-range-cache.cc (ranger_cache::fill_block_cache): Change msg. + (ranger_cache::range_from_dom): Rename var side_effect to infer. + (ranger_cache::apply_inferred_ranges): Rename from apply_side_effects. + * gimple-range-cache.h: Include gimple-range-infer.h. + (class ranger_cache): Adjust prototypes, use infer_range_manager. + * gimple-range-infer.cc: Rename from gimple-range-side-effects.cc. + (gimple_infer_range::*): Rename from stmt_side_effects. + (infer_range_manager::*): Rename from side_effect_manager. + * gimple-range-side-effect.cc: Rename. + * gimple-range-side-effect.h: Rename. + * gimple-range-infer.h: Rename from gimple-range-side-effects.h. + (class gimple_infer_range): Rename from stmt_side_effects. + (class infer_range_manager): Rename from side_effect_manager. + * gimple-range.cc (gimple_ranger::register_inferred_ranges): Rename + from register_side_effects. + * gimple-range.h (register_inferred_ranges): Adjust prototype. + * range-op.h: Adjust comment. + * tree-vrp.cc (rvrp_folder::pre_fold_bb): Use register_inferred_ranges. + (rvrp_folder::post_fold_bb): Use register_inferred_ranges. + +2022-05-25 Simon Cook <simon.cook@embecosm.com> + + * config/riscv/arch-canonicalize: Only add mafd extension if + base was rv32/rv64g. + +2022-05-25 Tobias Burnus <tobias@codesourcery.com> + + * doc/invoke.texi (AMD GCN Options): Add gfx908/gfx90a. + +2022-05-25 Jakub Jelinek <jakub@redhat.com> + + PR sanitizer/105714 + * asan.cc (has_stmt_been_instrumented_p): For assignments which + are both stores and loads, return true only if both destination + and source have been instrumented. + +2022-05-25 Martin Liska <mliska@suse.cz> + Richard Biener <rguenther@suse.de> + + * dbgcnt.def (DEBUG_COUNTER): Add loop_unswitch counter. + * params.opt (max-unswitch-level): Remove. + * doc/invoke.texi (max-unswitch-level): Likewise. + * tree-cfg.cc (gimple_lv_add_condition_to_bb): Support not + gimplified expressions. + * tree-ssa-loop-unswitch.cc (struct unswitch_predicate): New. + (tree_may_unswitch_on): Rename to ... + (find_unswitching_predicates_for_bb): ... this and handle + switch statements. + (get_predicates_for_bb): Likewise. + (set_predicates_for_bb): Likewise. + (init_loop_unswitch_info): Likewise. + (tree_ssa_unswitch_loops): Prepare stuff before calling + tree_unswitch_single_loop. + (tree_unswitch_single_loop): Rework the function using + pre-computed predicates and with a per original loop cost model. + (merge_last): New. + (add_predicate_to_path): Likewise. + (find_range_for_lhs): Likewise. + (simplify_using_entry_checks): Rename to ... + (evaluate_control_stmt_using_entry_checks): ... this, handle + switch statements and improve simplifications using ranger. + (simplify_loop_version): Rework using + evaluate_control_stmt_using_entry_checks. + (evaluate_bbs): New. + (evaluate_loop_insns_for_predicate): Likewise. + (tree_unswitch_loop): Adjust to allow switch statements and + pass in the edge to unswitch. + (clean_up_after_unswitching): New. + (pass_tree_unswitch::execute): Pass down fun. + +2022-05-24 Eugene Rozenfeld <erozen@microsoft.com> + + * tree-vect-loop-manip.cc (vect_do_peeling): Save/restore profile + counts for the epilog loop. + +2022-05-24 Martin Sebor <msebor@redhat.com> + Richard Biener <rguenther@suse.de> + + PR middle-end/105604 + * gimple-ssa-sprintf.cc (set_aggregate_size_and_offset): Add comments. + (get_origin_and_offset_r): Remove null handling. Handle variable array + sizes. + (get_origin_and_offset): Handle null argument here. Simplify. + (alias_offset): Update comment. + * pointer-query.cc (field_at_offset): Update comment. Handle members + of variable-length types. + +2022-05-24 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> + + * target.def (vec_perm_const): Define new parameter op_mode and + update doc. + * doc/tm.texi: Regenerate. + * config/aarch64/aarch64.cc (aarch64_vectorize_vec_perm_const): Adjust + vec_perm_const hook to add new parameter op_mode and return false + if result and operand modes do not match. + * config/arm/arm.cc (arm_vectorize_vec_perm_const): Likewise. + * config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Likewise. + * config/ia64/ia64.cc (ia64_vectorize_vec_perm_const): Likewise. + * config/mips/mips.cc (mips_vectorize_vec_perm_const): Likewise. + * config/rs6000/rs6000.cc (rs6000_vectorize_vec_perm_const): Likewise + * config/s390/s390.cc (s390_vectorize_vec_perm_const): Likewise. + * config/sparc/sparc.cc (sparc_vectorize_vec_perm_const): Likewise. + * config/i386/i386-expand.cc (ix86_vectorize_vec_perm_const): Likewise. + * config/i386/i386-expand.h (ix86_vectorize_vec_perm_const): Adjust + prototype. + * config/i386/sse.md (ashrv4di3): Adjust call to vec_perm_const hook. + (ashrv2di3): Likewise. + * optabs.cc (expand_vec_perm_const): Likewise. + * optabs-query.h (can_vec_perm_const_p): Adjust prototype. + * optabs-query.cc (can_vec_perm_const_p): Define new parameter + op_mode and pass it to vec_perm_const hook. + (can_mult_highpart_p): Adjust call to can_vec_perm_const_p. + * match.pd (vec_perm X Y CST): Likewise. + * tree-ssa-forwprop.cc (simplify_vector_constructor): Likewise. + * tree-vect-data-refs.cc (vect_grouped_store_supported): Likewise. + (vect_grouped_load_supported): Likewise. + (vect_shift_permute_load_chain): Likewise. + * tree-vect-generic.cc (lower_vec_perm): Likewise. + * tree-vect-loop-manip.cc (interleave_supported_p): Likewise. + * tree-vect-loop.cc (have_whole_vector_shift): Likewise. + * tree-vect-patterns.cc (vect_recog_rotate_pattern): Likewise. + * tree-vect-slp.cc (can_duplicate_and_interleave_p): Likewise. + (vect_transform_slp_perm_load): Likewise. + (vectorizable_slp_permutation): Likewise. + * tree-vect-stmts.cc (perm_mask_for_reverse): Likewise. + (vectorizable_bswap): Likewise. + (scan_store_can_perm_p): Likewise. + (vect_gen_perm_mask_checked): Likewise. + +2022-05-24 H.J. Lu <hjl.tools@gmail.com> + + PR target/104816 + * config/i386/i386.opt: Remove Undocumented. + * doc/invoke.texi: Document -mcet-switch. + +2022-05-24 Andrew Stubbs <ams@codesourcery.com> + + * config.gcc (amdgcn): Accept --with-arch=gfx908 and gfx90a. + * config/gcn/gcn-opts.h (enum gcn_isa): New. + (TARGET_GCN3): Use enum gcn_isa. + (TARGET_GCN3_PLUS): Likewise. + (TARGET_GCN5): Likewise. + (TARGET_GCN5_PLUS): Likewise. + (TARGET_CDNA1): New. + (TARGET_CDNA1_PLUS): New. + (TARGET_CDNA2): New. + (TARGET_CDNA2_PLUS): New. + (TARGET_M0_LDS_LIMIT): New. + (TARGET_PACKED_WORK_ITEMS): New. + * config/gcn/gcn.cc (gcn_isa): Change to enum gcn_isa. + (gcn_option_override): Recognise CDNA ISA variants. + (gcn_omp_device_kind_arch_isa): Support gfx90a. + (gcn_expand_prologue): Make m0 init optional. + Add support for packed work items. + (output_file_start): Support gfx90a. + (gcn_hsa_declare_function_name): Support gfx90a metadata. + * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS):Add __CDNA1__ and + __CDNA2__. + * config/gcn/gcn.md (<su>mulsi3_highpart): Use TARGET_GCN5_PLUS. + (<su>mulsi3_highpart_imm): Likewise. + (<su>mulsidi3): Likewise. + (<su>mulsidi3_imm): Likewise. + * config/gcn/gcn.opt (gpu_type): Add gfx90a. + * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX90a): New. + (main): Support gfx90a. + * config/gcn/t-gcn-hsa: Add gfx90a multilib. + * config/gcn/t-omp-device: Add gfx90a isa. + +2022-05-24 Andrew Stubbs <ams@codesourcery.com> + + * config.in: Regenerate. + * config/gcn/gcn-hsa.h (X_FIJI): Delete. + (X_900): Delete. + (X_906): Delete. + (X_908): Delete. + (S_FIJI): Delete. + (S_900): Delete. + (S_906): Delete. + (S_908): Delete. + (NO_XNACK): New macro. + (NO_SRAM_ECC): New macro. + (SRAMOPT): Keep only v4 variant. + (HSACO3_SELECT_OPT): Delete. + (DRIVER_SELF_SPECS): Delete. + (ASM_SPEC): Remove LLVM 9 support. + * config/gcn/gcn-valu.md + (gather<mode>_insn_2offsets<exec>): Remove assembler bug workaround. + (scatter<mode>_insn_2offsets<exec_scatter>): Likewise. + * config/gcn/gcn.cc (output_file_start): Remove LLVM 9 support. + (print_operand_address): Remove assembler bug workaround. + * config/gcn/mkoffload.cc (EF_AMDGPU_XNACK_V3): Delete. + (EF_AMDGPU_SRAM_ECC_V3): Delete. + (SET_XNACK_ON): Delete v3 variants. + (SET_XNACK_OFF): Delete v3 variants. + (TEST_XNACK): Delete v3 variants. + (SET_SRAM_ECC_ON): Delete v3 variants. + (SET_SRAM_ECC_ANY): Delete v3 variants. + (SET_SRAM_ECC_OFF): Delete v3 variants. + (SET_SRAM_ECC_UNSUPPORTED): Delete v3 variants. + (TEST_SRAM_ECC_ANY): Delete v3 variants. + (TEST_SRAM_ECC_ON): Delete v3 variants. + (copy_early_debug_info): Remove v3 support. + (main): Remove v3 support. + * configure: Regenerate. + * configure.ac: Replace all GCN feature checks with a version check. + +2022-05-24 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/i386.md (peephole2): Convert xor;neg;adc;neg, + i.e. a double word negation of a zero extended operand, to + neg;sbb. + +2022-05-24 Roger Sayle <roger@nextmovesoftware.com> + + PR tree-optimization/105668 + * config/i386/i386-expand.cc (ix86_expand_sse_movcc): Support + V1TImode, just like V2DImode. + * config/i386/sse.md (vcond_mask_<mode><sseintvecmodelower>): + Use VI_128 mode iterator instead of VI124_128 to include V2DI. + (vcond_mask_v2div2di): Delete. + (vcond_mask_v1tiv1ti): New define_expand. + +2022-05-24 Roger Sayle <roger@nextmovesoftware.com> + + * genpreds.cc (write_lookup_constraint_1): Avoid generating a call + to strncmp for strings of length one. + +2022-05-24 ShiYulong <shiyulong@iscas.ac.cn> + + * config/riscv/predicates.md (imm5_operand): Add a new operand type for + prefetch instructions. + * config/riscv/riscv-builtins.cc (AVAIL): Add new AVAILs for CMO ISA + Extensions. + (RISCV_ATYPE_SI): New. + (RISCV_ATYPE_DI): New. + * config/riscv/riscv-ftypes.def (0): New. + (1): New. + * config/riscv/riscv.md (riscv_clean_<mode>): New. + (riscv_flush_<mode>): New. + (riscv_inval_<mode>): New. + (riscv_zero_<mode>): New. + (prefetch): New. + (riscv_prefetchi_<mode>): New. + * config/riscv/riscv-cmo.def: New file. + +2022-05-24 ShiYulong <shiyulong@iscas.ac.cn> + + * common/config/riscv/riscv-common.cc: Add zicbom, zicboz, zicbop extensions. + * config/riscv/riscv-opts.h (MASK_ZICBOZ): New. + (MASK_ZICBOM): New. + (MASK_ZICBOP): New. + (TARGET_ZICBOZ): New. + (TARGET_ZICBOM): New. + (TARGET_ZICBOP): New. + * config/riscv/riscv.opt (riscv_zicmo_subext): New. + +2022-05-24 David Malcolm <dmalcolm@redhat.com> + + * tree-vect-slp-patterns.cc: Add "final" and "override" to + vect_pattern::build impls as appropriate. + +2022-05-24 David Malcolm <dmalcolm@redhat.com> + + * ipa-cp.cc: Add "final" and "override" to call_summary_base vfunc + implementations, removing redundant "virtual" as appropriate. + * ipa-fnsummary.h: Likewise. + * ipa-modref.cc: Likewise. + * ipa-param-manipulation.cc: Likewise. + * ipa-profile.cc: Likewise. + * ipa-prop.h: Likewise. + * ipa-pure-const.cc: Likewise. + * ipa-reference.cc: Likewise. + * ipa-sra.cc: Likewise. + * symbol-summary.h: Likewise. + * symtab-thunks.cc: Likewise. + +2022-05-24 Martin Liska <mliska@suse.cz> + + Revert: + 2022-05-24 Martin Liska <mliska@suse.cz> + + * expmed.cc (emit_store_flag_1): Mitigate -Wmaybe-uninitialized + warning. + +2022-05-24 Martin Liska <mliska@suse.cz> + + * expmed.cc (emit_store_flag_1): Mitigate -Wmaybe-uninitialized + warning. + +2022-05-24 Bruno Haible <bruno@clisp.org> + + PR other/105527 + * doc/install.texi (Configuration): Add more details about --with-zstd. + Document --with-zstd-include and --with-zstd-lib + +2022-05-24 Richard Biener <rguenther@suse.de> + + PR middle-end/105711 + * expmed.cc (extract_bit_field_as_subreg): Add op0_mode parameter + and use it. + (extract_bit_field_1): Pass down the mode of op0 to + extract_bit_field_as_subreg. + +2022-05-24 Vineet Gupta <vineetg@rivosinc.com> + + * config/riscv/riscv.cc: (struct riscv_tune_param): Add + fmv_cost. + (rocket_tune_info): Add default fmv_cost 8. + (sifive_7_tune_info): Ditto. + (thead_c906_tune_info): Ditto. + (optimize_size_tune_info): Ditto. + (riscv_register_move_cost): Use fmv_cost for int<->fp moves. + +2022-05-24 Jakub Jelinek <jakub@redhat.com> + + PR c/105378 + * omp-builtins.def (BUILT_IN_GOMP_TASKWAIT_DEPEND_NOWAIT): New + builtin. + * gimplify.cc (gimplify_omp_task): Diagnose taskwait with nowait + clause but no depend clauses. + * omp-expand.cc (expand_taskwait_call): Use + BUILT_IN_GOMP_TASKWAIT_DEPEND_NOWAIT rather than + BUILT_IN_GOMP_TASKWAIT_DEPEND if nowait clause is present. + +2022-05-24 Richard Biener <rguenther@suse.de> + + PR tree-optimization/100221 + * tree-ssa-dse.cc (contains_phi_arg): New function. + (dse_classify_store): Postpone PHI defs that feed another PHI in defs. + +2022-05-24 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105629 + * tree-ssa-phiopt.cc (spaceship_replacement): Allow + a sign-extending conversion. + +2022-05-24 Kewen Lin <linkw@linux.ibm.com> + + PR target/105627 + * config/rs6000/rs6000-p8swap.cc (union_defs): Assert def_insn can't + be a debug insn. + (union_uses): Skip debug use_insn. + +2022-05-23 Vineet Gupta <vineetg@rivosinc.com> + + * config/riscv/predicates.md (const_0_operand): Remove + const_double. + * config/riscv/riscv.cc (riscv_rtx_costs): Add check for + CONST_DOUBLE. + * config/riscv/riscv.h (TARGET_SUPPORTS_WIDE_INT): New define. + +2022-05-23 Mayshao <mayshao-oc@zhaoxin.com> + + * common/config/i386/cpuinfo.h (get_zhaoxin_cpu): Detect + the specific type of Zhaoxin CPU, and return Zhaoxin CPU name. + (cpu_indicator_init): Handle Zhaoxin processors. + * common/config/i386/i386-common.cc: Add lujiazui. + * common/config/i386/i386-cpuinfo.h (enum processor_vendor): Add + VENDOR_ZHAOXIN. + (enum processor_types): Add ZHAOXIN_FAM7H. + (enum processor_subtypes): Add ZHAOXIN_FAM7H_LUJIAZUI. + * config.gcc: Add lujiazui. + * config/i386/cpuid.h (signature_SHANGHAI_ebx): Add + Signatures for zhaoxin + (signature_SHANGHAI_ecx): Ditto. + (signature_SHANGHAI_edx): Ditto. + * config/i386/driver-i386.cc (host_detect_local_cpu): Let + -march=native recognize lujiazui processors. + * config/i386/i386-c.cc (ix86_target_macros_internal): Add lujiazui. + * config/i386/i386-options.cc (m_LUJIAZUI): New_definition. + * config/i386/i386.h (enum processor_type): Ditto. + * config/i386/i386.md: Add lujiazui. + * config/i386/x86-tune-costs.h (struct processor_costs): Add + lujiazui costs. + * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add lujiazui. + (ix86_adjust_cost): Ditto. + * config/i386/x86-tune.def (X86_TUNE_SCHEDULE): Add lujiazui Tunnings. + (X86_TUNE_PARTIAL_REG_DEPENDENCY): Ditto. + (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY): Ditto. + (X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY): Ditto. + (X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY): Ditto. + (X86_TUNE_MOVX): Ditto. + (X86_TUNE_MEMORY_MISMATCH_STALL): Ditto. + (X86_TUNE_FUSE_CMP_AND_BRANCH_32): Ditto. + (X86_TUNE_FUSE_CMP_AND_BRANCH_64): Ditto. + (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS): Ditto. + (X86_TUNE_FUSE_ALU_AND_BRANCH): Ditto. + (X86_TUNE_ACCUMULATE_OUTGOING_ARGS): Ditto. + (X86_TUNE_USE_LEAVE): Ditto. + (X86_TUNE_PUSH_MEMORY): Ditto. + (X86_TUNE_LCP_STALL): Ditto. + (X86_TUNE_USE_INCDEC): Ditto. + (X86_TUNE_INTEGER_DFMODE_MOVES): Ditto. + (X86_TUNE_OPT_AGU): Ditto. + (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB): Ditto. + (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES): Ditto. + (X86_TUNE_USE_SAHF): Ditto. + (X86_TUNE_USE_BT): Ditto. + (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI): Ditto. + (X86_TUNE_ONE_IF_CONV_INSN): Ditto. + (X86_TUNE_AVOID_MFENCE): Ditto. + (X86_TUNE_EXPAND_ABS): Ditto. + (X86_TUNE_USE_SIMODE_FIOP): Ditto. + (X86_TUNE_USE_FFREEP): Ditto. + (X86_TUNE_EXT_80387_CONSTANTS): Ditto. + (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL): Ditto. + (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Ditto. + (X86_TUNE_SSE_TYPELESS_STORES): Ditto. + (X86_TUNE_SSE_LOAD0_BY_PXOR): Ditto. + * doc/extend.texi: Add details about lujiazui. + * doc/invoke.texi: Add details about lujiazui. + * config/i386/lujiazui.md: Introduce lujiazui cpu and include new md file. + +2022-05-23 Martin Liska <mliska@suse.cz> + + * config/tilepro/gen-mul-tables.cc (ARRAY_SIZE): Add new macro. + +2022-05-23 Richard Biener <rguenther@suse.de> + + * tree-ssa-forwprop.cc (forward_propagate_into_cond): Remove. + (pass_forwprop::execute): Do not propagate into COND_EXPR conditions. + +2022-05-23 Richard Biener <rguenther@suse.de> + + * gimple-expr.cc (is_gimple_condexpr): Remove. + * gimple-expr.h (is_gimple_condexpr): Likewise. + * gimplify.cc (gimplify_expr): Remove is_gimple_condexpr usage. + * tree-if-conv.cc (set_bb_predicate): Likewie. + (add_to_predicate_list): Likewise. + (gen_phi_arg_condition): Likewise. + (predicate_scalar_phi): Likewise. + (predicate_statements): Likewise. + +2022-05-23 Richard Biener <rguenther@suse.de> + + * gimple-expr.cc (is_gimple_condexpr): Equate to is_gimple_val. + * gimplify.cc (gimplify_pure_cond_expr): Gimplify the condition + as is_gimple_val. + * gimple-fold.cc (valid_gimple_rhs_p): Simplify. + * tree-cfg.cc (verify_gimple_assign_ternary): Likewise. + * gimple-loop-interchange.cc (loop_cand::undo_simple_reduction): + Build the condition of the COND_EXPR separately. + * tree-ssa-loop-im.cc (move_computations_worker): Likewise. + * tree-vect-generic.cc (expand_vector_condition): Likewise. + * tree-vect-loop.cc (vect_create_epilog_for_reduction): + Likewise. + * vr-values.cc (simplify_using_ranges::simplify): Likewise. + * tree-vect-patterns.cc: Add comment indicating we are + building invalid COND_EXPRs and why. + * omp-expand.cc (expand_omp_simd): Gimplify the condition + to the COND_EXPR separately. + (expand_omp_atomic_cas): Note part that should be unreachable + now. + * tree-ssa-forwprop.cc (forward_propagate_into_cond): Adjust + condition for valid replacements. + * tree-if-conv.cc (predicate_bbs): Simulate previous + re-folding of the condition in folded COND_EXPRs which + is necessary because of unfolded GIMPLE_CONDs in the IL + as in for example gcc.dg/fold-bopcond-1.c. + * gimple-range-gori.cc (gori_compute::condexpr_adjust): + Handle that the comparison is now in the def stmt of + the select operand. Required by gcc.dg/pr104526.c. + +2022-05-23 Tobias Burnus <tobias@codesourcery.com> + + PR fortran/104949 + * langhooks-def.h (lhd_omp_array_size): New. + (LANG_HOOKS_OMP_ARRAY_SIZE): Define. + (LANG_HOOKS_DECLS): Add it. + * langhooks.cc (lhd_omp_array_size): New. + * langhooks.h (struct lang_hooks_for_decls): Add hook. + * omp-low.cc (scan_sharing_clauses, lower_omp_target): + Handle GOMP_MAP_FIRSTPRIVATE for array descriptors. + +2022-05-23 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/i386.cc (ix86_rtx_costs) <case AND>: Split from + XOR/IOR case. Account for two instructions for double-word + operations. In case of vector pandn, account for single + instruction. Likewise for integer andn with TARGET_BMI. + <case NOT>: Vector NOT requires more than 1 instruction (pxor). + <case NEG>: Double-word negation requires 3 instructions. + +2022-05-23 Tsukasa OI <research_trasio@irq.a4lg.com> + + * common/config/riscv/riscv-common.cc (riscv_supported_std_ext): + Fix "K" extension prefix to be placed before "J". + * config/riscv/arch-canonicalize: Likewise. + +2022-05-23 liuhongt <hongtao.liu@intel.com> + + * config/i386/x86-tune-costs.h (skylake_cost): Increase gpr + <-> mask cost from 5 to 6. + (icelake_cost): Ditto. + +2022-05-20 Wilco Dijkstra <wilco.dijkstra@arm.com> + + * config/aarch64/aarch64.md + (and_<SHIFT:optab><mode>3_compare0): Support rotate left. + (and_<SHIFT:optab>si3_compare0_uxtw): Likewise. + (<LOGICAL:optab>_<SHIFT:optab><mode>3): Likewise. + (<LOGICAL:optab>_<SHIFT:optab>si3_uxtw): Likewise. + (one_cmpl_<optab><mode>2): Likewise. + (<LOGICAL:optab>_one_cmpl_<SHIFT:optab><mode>3): Likewise. + (<LOGICAL:optab>_one_cmpl_<SHIFT:optab>sidi_uxtw): New pattern. + (eor_one_cmpl_<SHIFT:optab><mode>3_alt): Support rotate left. + (eor_one_cmpl_<SHIFT:optab>sidi3_alt_ze): Likewise. + (and_one_cmpl_<SHIFT:optab><mode>3_compare0): Likewise. + (and_one_cmpl_<SHIFT:optab>si3_compare0_uxtw): Likewise. + (and_one_cmpl_<SHIFT:optab><mode>3_compare0_no_reuse): Likewise. + (and_<SHIFT:optab><mode>3nr_compare0): Likewise. + (*<optab>si3_insn_uxtw): Use SHIFT_no_rotate. + (rolsi3_insn_uxtw): New pattern. + * config/aarch64/iterators.md (SHIFT): Add rotate left. + (SHIFT_no_rotate): Add new iterator. + (SHIFT:shift): Print rotate left as ror. + (is_rotl): Add test for left rotate. + +2022-05-20 Wilco Dijkstra <wilco.dijkstra@arm.com> + + * config.gcc (aarch64*-*-*): Simplify --with-cpu and --with-arch + processing. Add support for architectural extensions. + * config/aarch64/aarch64.h (TARGET_CPU_DEFAULT): Remove + AARCH64_CPU_DEFAULT_FLAGS. + (TARGET_CPU_NBITS): Remove. + (TARGET_CPU_MASK): Remove. + * config/aarch64/aarch64.cc (AARCH64_CPU_DEFAULT_FLAGS): Remove define. + (get_tune_cpu): Assert CPU is always valid. + (get_arch): Assert architecture is always valid. + (aarch64_override_options): Cleanup CPU selection code and simplify logic. + (aarch64_option_restore): Remove unnecessary checks on tune. + +2022-05-20 David Malcolm <dmalcolm@redhat.com> + + * config/aarch64/aarch64-sve-builtins-base.cc: Replace uses of + "FINAL" and "OVERRIDE" with "final" and "override". + * config/aarch64/aarch64-sve-builtins-functions.h: Likewise. + * config/aarch64/aarch64-sve-builtins-shapes.cc: Likewise. + * config/aarch64/aarch64-sve-builtins-sve2.cc: Likewise. + * diagnostic-path.h: Likewise. + * digraph.cc: Likewise. + * gcc-rich-location.h: Likewise. + * gimple-array-bounds.cc: Likewise. + * gimple-loop-versioning.cc: Likewise. + * gimple-range-cache.cc: Likewise. + * gimple-range-cache.h: Likewise. + * gimple-range-fold.cc: Likewise. + * gimple-range-fold.h: Likewise. + * gimple-range-tests.cc: Likewise. + * gimple-range.h: Likewise. + * gimple-ssa-evrp.cc: Likewise. + * input.cc: Likewise. + * json.h: Likewise. + * read-rtl-function.cc: Likewise. + * tree-complex.cc: Likewise. + * tree-diagnostic-path.cc: Likewise. + * tree-ssa-ccp.cc: Likewise. + * tree-ssa-copy.cc: Likewise. + * tree-vrp.cc: Likewise. + * value-query.h: Likewise. + * vr-values.h: Likewise. + +2022-05-20 Marcel Vollweiler <marcel@codesourcery.com> + + * omp-low.cc (omp_runtime_api_call): Added target_memcpy_async and + target_memcpy_rect_async to omp_runtime_apis array. + +2022-05-20 Christophe Lyon <christophe.lyon@arm.com> + + * doc/sourcebuild.texi (Decimal floating point attributes): Document + dfp_bid effective-target. + +2022-05-20 Christophe Lyon <christophe.lyon@arm.com> + + * config/aarch64/aarch64.cc + (aarch64_split_128bit_move): Handle DFP modes. + (aarch64_mode_valid_for_sched_fusion_p): Likewise. + (aarch64_classify_address): Likewise. + (aarch64_legitimize_address_displacement): Likewise. + (aarch64_reinterpret_float_as_int): Likewise. + (aarch64_float_const_zero_rtx_p): Likewise. + (aarch64_can_const_movi_rtx_p): Likewise. + (aarch64_anchor_offset): Likewise. + (aarch64_secondary_reload): Likewise. + (aarch64_rtx_costs): Likewise. + (aarch64_legitimate_constant_p): Likewise. + (aarch64_gimplify_va_arg_expr): Likewise. + (aapcs_vfp_sub_candidate): Likewise. + (aarch64_vfp_is_call_or_return_candidate): Likewise. + (aarch64_output_scalar_simd_mov_immediate): Likewise. + (aarch64_gen_adjusted_ldpstp): Likewise. + (aarch64_scalar_mode_supported_p): Accept DFP modes if enabled. + * config/aarch64/aarch64.md + (movsf_aarch64): Use SFD iterator and rename into + mov<mode>_aarch64. + (movdf_aarch64): Use DFD iterator and rename into + mov<mode>_aarch64. + (movtf_aarch64): Use TFD iterator and rename into + mov<mode>_aarch64. + (split pattern for move TF mode): Use TFD iterator. + * config/aarch64/iterators.md + (GPF_TF_F16_MOV): Add DFP modes. + (SFD, DFD, TFD): New iterators. + (GPF_TF): Add DFP modes. + (TX, DX, DX2): Likewise. + +2022-05-20 Christophe Lyon <christophe.lyon@arm.com> + + * configure: Regenerate. + +2022-05-19 Roger Sayle <roger@nextmovesoftware.com> + + PR middle-end/98865 + * expr.cc (expand_expr_real_2) [MULT_EXPR]: Expand X*Y as X&Y + when both X and Y are [0, 1], X*Y as X&-Y when Y is [0,1] and + likewise X*Y as -X&Y when X is [0,1] using tree_nonzero_bits. + +2022-05-19 Will Schmidt <will_schmidt@vnet.ibm.com> + + * config/rs6000/rs6000-builtins.def: Rephrase + to remove RS6000_BTC_SPECIAL from comment. + * config/rs6000/rs6000.h (RS6000_BTC_UNARY, RS6000_BTC_BINARY, + RS6000_BTC_TERNARY, RS6000_BTC_QUATERNARY, + RS6000_BTC_QUINARY, RS6000_BTC_SENARY, RS6000_BTC_OPND_MASK, + RS6000_BTC_SPECIAL, RS6000_BTC_PREDICATE, RS6000_BTC_ABS, + RS6000_BTC_DST, RS6000_BTC_TYPE_MASK, RS6000_BTC_MISC, + RS6000_BTC_CONST, RS6000_BTC_PURE, RS6000_BTC_FP, + RS6000_BTC_QUAD, RS6000_BTC_PAIR, RS6000_BTC_QUADPAIR, + RS6000_BTC_ATTR_MASK, RS6000_BTC_SPR, RS6000_BTC_VOID, + RS6000_BTC_CR, RS6000_BTC_OVERLOADED, RS6000_BTC_GIMPLE, + RS6000_BTC_MISC_MASK, RS6000_BTC_MEM, RS6000_BTC_SAT, + RS6000_BTM_ALWAYS): Delete. + +2022-05-19 Richard Biener <rguenther@suse.de> + + * omp-expand.cc (expand_omp_atomic_cas): Do not short-cut + computation of the new value. + +2022-05-19 Richard Biener <rguenther@suse.de> + + * tree-ssa-pre.cc (get_or_alloc_expression_id): Remove. + (add_to_value): Use get_expression_id. + (bitmap_insert_into_set): Likewise. + (bitmap_value_insert_into_set): Likewise. + +2022-05-19 David Malcolm <dmalcolm@redhat.com> + + * doc/invoke.texi (-fanalyzer-checker=): Add + -Wanalyzer-va-list-leak and -Wanalyzer-va-list-use-after-va-end to + the list of analyzer warnings disabled by + -fanalyzer-checker=taint. + +2022-05-19 Jakub Jelinek <jakub@redhat.com> + + PR debug/105630 + * cfgexpand.cc (expand_debug_expr): For VAR_DECL, punt for + global vars without symtab node even when they have DECL_RTL + set. + +2022-05-19 Jakub Jelinek <jakub@redhat.com> + + PR c/105635 + * pointer-query.cc (gimple_parm_array_size): Return NULL if var + doesn't have pointer or reference type. + +2022-05-18 Marek Polacek <polacek@redhat.com> + + PR c/105131 + * doc/invoke.texi: Document -Wenum-int-mismatch. + +2022-05-18 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/gnu-user-common.h (defined): Only define + TARGET_CAN_SPLIT_STACK for glibc targets. + * config/i386/gnu.h (defined): Ditto. + +2022-05-18 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/i386.cc (ix86_rtx_costs) [MULT]: When mode size + is wider than word_mode, a multiplication costs three word_mode + multiplications and two word_mode additions. + +2022-05-18 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/i386.md (define_split): Split *andsi_1 + and *andn_si_ccno after reload with -Oz. + +2022-05-18 Frederik Harwath <frederik@codesourcery.com> + + * graphite-scop-detection.cc (scop_detection::can_represent_loop): + Output reason for failure to dump file. + (scop_detection::harmful_loop_in_region): Likewise. + (scop_detection::graphite_can_represent_expr): Likewise. + (scop_detection::stmt_has_simple_data_refs_p): Likewise. + (scop_detection::stmt_simple_for_scop_p): Likewise. + (print_sese_loop_numbers): New function. + (scop_detection::add_scop): Use from here. + +2022-05-18 liuhongt <hongtao.liu@intel.com> + + PR middle-end/103462 + * match.pd (bitwise_induction_p): New match. + * tree-scalar-evolution.cc (gimple_bitwise_induction_p): + Declare. + (analyze_and_compute_bitwise_induction_effect): New function. + (enum bit_op_kind): New enum. + (final_value_replacement_loop): Enhanced to handle bitwise + induction. + +2022-05-18 Haochen Gui <guihaoc@gcc.gnu.org> + + PR target/95737 + * config/rs6000/rs6000.md (*subfsi3_carry_in_xx_64): New. + +2022-05-18 liuhongt <hongtao.liu@intel.com> + + PR target/104375 + * config/i386/i386.md (*bmi2_bzhi_zero_extendsidi_4): New + define_insn. + +2022-05-18 liuhongt <hongtao.liu@intel.com> + + PR target/104610 + * config/i386/i386-expand.cc (ix86_expand_branch): Use ptest + for QImode when code is EQ or NE. + * config/i386/i386.md (cbranchoi4): New expander. + +2022-05-18 Peter Bergner <bergner@linux.ibm.com> + Segher Boessenkool <segher@kernel.crashing.org> + + PR target/105556 + * config/rs6000/mma.md (mma_<vv>, mma_<avv>, mma_<pv>, mma_<apv>, + mma_<vvi4i4i8>, mma_<avvi4i4i8>, mma_<vvi4i4i2>, mma_<avvi4i4i2>, + mma_<vvi4i4>, mma_<avvi4i4>, mma_<pvi4i2>, mma_<apvi4i2>, + mma_<vvi4i4i4>, mma_<avvi4i4i4>): Replace "wa" constraints with "v,?wa". + Update other operands accordingly. + +2022-05-17 Marek Polacek <polacek@redhat.com> + + * godump.cc (go_output_typedef): Use the DECL_INITIAL of the TREE_VALUE. + +2022-05-17 Pat Haugen <pthaugen@linux.ibm.com> + + PR target/99685 + * config/rs6000/rs6000-call.cc (rs6000_function_arg_advance_1): Bump + register count when not splitting IEEE 128-bit Complex. + +2022-05-17 Tobias Burnus <tobias@codesourcery.com> + + * omp-low.cc (check_omp_nesting_restrictions): Skip warning for + target inside target if inner is reverse offload. + +2022-05-17 Tobias Burnus <tobias@codesourcery.com> + + * config/gcn/mkoffload.cc (process_obj): Revert: Use ARRAY_SIZE. + * config/nvptx/mkoffload.cc (process): Likewise. + +2022-05-17 Andrew MacLeod <amacleod@redhat.com> + + * Makefile.in (OBJS): Add gimple-range-side-effect.o. + * gimple-range-cache.cc (non_null_ref::non_null_ref): Delete. + (non_null_ref::~non_null_ref): Delete. + (non_null_ref::set_nonnull): Delete. + (non_null_ref::non_null_deref_p): Delete. + (non_null_ref::process_name): Delete. + (ranger_cache::ranger_cache): Initialize m_exit object. + (ranger_cache::fill_block_cache): Use m_exit object intead of nonnull. + (ranger_cache::range_from_dom): Use side_effect class and m_exit object. + (ranger_cache::update_to_nonnull): Delete. + (non_null_loadstore): Delete. + (ranger_cache::block_apply_nonnull): Delete. + (ranger_cache::apply_side_effects): New. + * gimple-range-cache.h (class non_null_ref): Delete. + (non_null_ref::adjust_range): Delete. + (class ranger_cache): Adjust prototypes, add side effect manager. + * gimple-range-path.cc (path_range_query::range_defined_in_block): Use + side effect manager for queries. + (path_range_query::adjust_for_non_null_uses): Ditto. + * gimple-range-path.h (class path_range_query): Delete non_null_ref. + * gimple-range-side-effect.cc: New. + * gimple-range-side-effect.h: New. + * gimple-range.cc (gimple_ranger::gimple_ranger): Update contructor. + (gimple_ranger::range_of_expr): Check def block for override value. + (gimple_ranger::range_on_entry): Don't scan dominators for non-null. + (gimple_ranger::range_on_edge): Check for outgoing side-effects. + (gimple_ranger::register_side_effects): Call apply_side_effects. + (enable_ranger): Update contructor. + * gimple-range.h (class gimple_ranger): Update prototype. + (enable_ranger): Update prototype. + * tree-vrp.cc (execute_ranger_vrp): Invoke without immediate-use flag. + +2022-05-17 Giuliano Belinassi <gbelinassi@suse.de> + + PR c++/105169 + * targhooks.cc (default_print_patchable_function_entry_1): Handle COMDAT case. + * varasm.cc (switch_to_comdat_section): New + (handle_vtv_comdat_section): Call switch_to_comdat_section. + * varasm.h: Declare switch_to_comdat_section. + +2022-05-17 Richard Biener <rguenther@suse.de> + + * cfgloopmanip.cc (duplicate_loop_body_to_header_edge): Do + not clear bb->aux of the copied blocks. + +2022-05-17 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/105458 + * value-relation.cc (path_oracle::register_relation): Merge, then check + for equivalence. + +2022-05-17 Uroš Bizjak <ubizjak@gmail.com> + + PR target/105624 + Revert: + * config/i386/i386.md: Remove constraints when used with + const_int_operand, const0_operand, const_1_operand, constm1_operand, + const8_operand, const128_operand, const248_operand, const123_operand, + const2367_operand, const1248_operand, const359_operand, + const_4_or_8_to_11_operand, const48_operand, const_0_to_1_operand, + const_0_to_3_operand, const_0_to_4_operand, const_0_to_5_operand, + const_0_to_7_operand, const_0_to_15_operand, const_0_to_31_operand, + const_0_to_63_operand, const_0_to_127_operand, const_0_to_255_operand, + const_0_to_255_mul_8_operand, const_1_to_31_operand, + const_1_to_63_operand, const_2_to_3_operand, const_4_to_5_operand, + const_4_to_7_operand, const_6_to_7_operand, const_8_to_9_operand, + const_8_to_11_operand, const_8_to_15_operand, const_10_to_11_operand, + const_12_to_13_operand, const_12_to_15_operand, const_14_to_15_operand, + const_16_to_19_operand, const_16_to_31_operand, const_20_to_23_operand, + const_24_to_27_operand and const_28_to_31_operand. + * config/i386/mmx.md: Ditto. + * config/i386/sse.md: Ditto. + * config/i386/subst.md: Ditto. + * config/i386/sync.md: Ditto. + +2022-05-17 Thomas Schwinge <thomas@codesourcery.com> + + * diagnostic.cc: Don't advise to call 'abort' instead of + 'internal_error'. + * system.h: Advise to call 'internal_error' instead of 'abort' or + 'fancy_abort'. + +2022-05-17 Frederik Harwath <frederik@codesourcery.com> + + * graphite-sese-to-poly.cc (build_poly_sr_1): Fix a typo and + a reference to a variable which does not exist. + * graphite-isl-ast-to-gimple.cc (gsi_insert_earliest): Fix typo + in comment. + +2022-05-17 Frederik Harwath <frederik@codesourcery.com> + + * graphite-sese-to-poly.cc (isl_id_for_ssa_name): Rename to ... + (isl_id_for_parameter): ... this new function name. + (build_scop_context): Adjust function use. + +2022-05-17 Tobias Burnus <tobias@codesourcery.com> + + PR target/105602 + * config/gcn/t-omp-device (arch): Add 'amdgcn' besides existing 'gcn'. + * config/gcn/gcn.cc (gcn_omp_device_kind_arch_isa): Likewise. + +2022-05-17 Jakub Jelinek <jakub@redhat.com> + + * tree-core.h (enum omp_clause_depend_kind): Add + OMP_CLAUSE_DEPEND_INOUTSET. + * tree-pretty-print.cc (dump_omp_clause): Handle + OMP_CLAUSE_DEPEND_INOUTSET. + * gimplify.cc (gimplify_omp_depend): Likewise. + * omp-low.cc (lower_depend_clauses): Likewise. + +2022-05-17 Jakub Jelinek <jakub@redhat.com> + + PR target/105613 + * config/i386/sse.md (vec_cmpeqv2div2di, vec_cmpeqv1tiv1ti): Use + andv4si3 only for EQ, for NE use iorv4si3 instead. + +2022-05-17 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105618 + * tree-ssa-sink.cc (statement_sink_location): For virtual + PHI uses ignore those defining the used virtual operand. + +2022-05-17 Jakub Jelinek <jakub@redhat.com> + + * tree-ssa-forwprop.cc (simplify_bitfield_ref): Spelling fix: + hanlde -> handle. Fix up comment formatting. + +2022-05-17 liuhongt <hongtao.liu@intel.com> + + PR target/105033 + * config/i386/sse.md (*vec_concatv4si): Extend to .. + (*vec_concat<mode>): .. V16QI and V8HImode. + (*vec_concatv16qi_permt2): New pre_reload define_insn_and_split. + (*vec_concatv8hi_permt2): Ditto. + +2022-05-17 liuhongt <hongtao.liu@intel.com> + + PR tree-optimization/105591 + * tree-ssa-forwprop.cc (simplify_bitfield_ref): Clamp + vec_perm_expr index. + +2022-05-16 Jason Merrill <jason@redhat.com> + + PR c/105492 + * attribs.cc (decl_attributes): Fix broken typedefs here. + +2022-05-16 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/105103 + * Makefile.in (ANALYZER_OBJS): Add analyzer/varargs.o. + * doc/invoke.texi: Add -Wanalyzer-va-arg-type-mismatch, + -Wanalyzer-va-list-exhausted, -Wanalyzer-va-list-leak, and + -Wanalyzer-va-list-use-after-va-end. + +2022-05-16 Richard Biener <rguenther@suse.de> + + * gimple-match.h (gimple_build): Move code_helper overloads ... + * gimple-fold.h (gimple_build): ... here. + (gimple_build): Transition to new worker API. Provide + overloads from sequence-based API. + (gimple_convert): Likewise. + (gimple_convert_to_ptrofftype): Likewise. + (gimple_build_vector_from_val): Likewise. + (gimple_build_vector): Likewise. + (gimple_build_round_up): Likewise. + * gimple-fold.cc (gimple_build_insert_seq): New helper. + (gimple_build): Use it. Transition combined_fn and code_helper + API parts. + (gimple_convert): Transition to new worker API. + (gimple_convert_to_ptrofftype): Likewise. + (gimple_build_vector_from_val): Likewise. + (gimple_build_vector): Likewise. + (gimple_build_round_up): Likewise. + +2022-05-16 Richard Biener <rguenther@suse.de> + + * gimple-match.h (code_helper): Move class ... + * tree.h (code_helper): ... here. + +2022-05-16 Martin Liska <mliska@suse.cz> + + * opts-global.cc (write_langs): Add comment. + +2022-05-16 Eric Botcazou <ebotcazou@adacore.com> + + * dwarf2out.cc (loc_list_from_tree_1) <TRUTH_NOT_EXPR>: Do a logical + instead of a bitwise negation. + <COND_EXPR>: Swap the operands if the condition is TRUTH_NOT_EXPR. + +2022-05-16 Martin Liska <mliska@suse.cz> + + * attribs.cc (diag_attr_exclusions): Use ARRAY_SIZE. + (decls_mismatched_attributes): Likewise. + * builtins.cc (c_strlen): Likewise. + * cfg.cc (DEF_BASIC_BLOCK_FLAG): Likewise. + * common/config/aarch64/aarch64-common.cc (aarch64_option_init_struct): Likewise. + * config/aarch64/aarch64-builtins.cc (aarch64_lookup_simd_builtin_type): Likewise. + (aarch64_init_simd_builtin_types): Likewise. + (aarch64_init_builtin_rsqrt): Likewise. + * config/aarch64/aarch64.cc (is_madd_op): Likewise. + * config/arm/arm-builtins.cc (arm_lookup_simd_builtin_type): Likewise. + (arm_init_simd_builtin_types): Likewise. + * config/avr/gen-avr-mmcu-texi.cc (mcus[ARRAY_SIZE): Likewise. + (c_prefix): Likewise. + (main): Likewise. + * config/c6x/c6x.cc (N_SAVE_ORDER): Likewise. + * config/darwin-c.cc (darwin_register_frameworks): Likewise. + * config/gcn/mkoffload.cc (process_obj): Likewise. + * config/i386/i386-builtins.cc (get_builtin_code_for_version): Likewise. + (fold_builtin_cpu): Likewise. + * config/m32c/m32c.cc (PUSHM_N): Likewise. + * config/nvptx/mkoffload.cc (process): Likewise. + * config/rs6000/driver-rs6000.cc (host_detect_local_cpu): Likewise. + * config/s390/s390.cc (NR_C_MODES): Likewise. + * config/tilepro/gen-mul-tables.cc (find_sequences): Likewise. + (create_insn_code_compression_table): Likewise. + * config/vms/vms.cc (NBR_CRTL_NAMES): Likewise. + * diagnostic-format-json.cc (json_from_expanded_location): Likewise. + * dwarf2out.cc (ARRAY_SIZE): Likewise. + * genhooks.cc (emit_documentation): Likewise. + (emit_init_macros): Likewise. + * gimple-ssa-sprintf.cc (format_floating): Likewise. + * gimple-ssa-warn-access.cc (memmodel_name): Likewise. + * godump.cc (keyword_hash_init): Likewise. + * hash-table.cc (hash_table_higher_prime_index): Likewise. + * input.cc (for_each_line_table_case): Likewise. + * ipa-free-lang-data.cc (free_lang_data): Likewise. + * ipa-inline.cc (sanitize_attrs_match_for_inline_p): Likewise. + * optc-save-gen.awk: Likewise. + * spellcheck.cc (test_metric_conditions): Likewise. + * tree-vect-slp-patterns.cc (sizeof): Likewise. + (ARRAY_SIZE): Likewise. + * tree.cc (build_common_tree_nodes): Likewise. + +2022-05-16 Martin Liska <mliska@suse.cz> + + * opts-global.cc (write_langs): Allocate at least one byte. + +2022-05-16 Richard Biener <rguenther@suse.de> + + * match.pd (A cmp B ? A : B -> min/max): New patterns + carried over from fold_cond_expr_with_comparison. + +2022-05-16 liuhongt <hongtao.liu@intel.com> + + PR target/105587 + * config/i386/i386-expand.cc + (expand_vec_perm_pslldq_psrldq_por): Fail when (d->perm[i] == + d->perm[i-1] + 1) && d->perm[i] == nelt && start != -1. + +2022-05-15 Uroš Bizjak <ubizjak@gmail.com> + + * config/i386/i386.md: Remove constraints when used with + const_int_operand, const0_operand, const_1_operand, constm1_operand, + const8_operand, const128_operand, const248_operand, const123_operand, + const2367_operand, const1248_operand, const359_operand, + const_4_or_8_to_11_operand, const48_operand, const_0_to_1_operand, + const_0_to_3_operand, const_0_to_4_operand, const_0_to_5_operand, + const_0_to_7_operand, const_0_to_15_operand, const_0_to_31_operand, + const_0_to_63_operand, const_0_to_127_operand, const_0_to_255_operand, + const_0_to_255_mul_8_operand, const_1_to_31_operand, + const_1_to_63_operand, const_2_to_3_operand, const_4_to_5_operand, + const_4_to_7_operand, const_6_to_7_operand, const_8_to_9_operand, + const_8_to_11_operand, const_8_to_15_operand, const_10_to_11_operand, + const_12_to_13_operand, const_12_to_15_operand, const_14_to_15_operand, + const_16_to_19_operand, const_16_to_31_operand, const_20_to_23_operand, + const_24_to_27_operand and const_28_to_31_operand. + * config/i386/mmx.md: Ditto. + * config/i386/sse.md: Ditto. + * config/i386/subst.md: Ditto. + * config/i386/sync.md: Ditto. + +2022-05-13 Roger Sayle <roger@nextmovesoftware.com> + Uroš Bizjak <ubizjak@gmail.com> + + * config/i386/sse.md (vec_cmpeqv2div2di): Enable for TARGET_SSE2. + For !TARGET_SSE4_1, expand as a V4SI vector comparison, followed + by a pshufd and pand. + (vec_cmpeqv1tiv1ti): New define_expand implementing V1TImode + vector equality as a V2DImode vector comparison (see above), + followed by a pshufd and pand. + +2022-05-13 Roger Sayle <roger@nextmovesoftware.com> + + PR tree-optimization/83907 + * tree-ssa-strlen.cc (handle_builtin_memset): Record a strinfo + for memset with an constant char value. + (handle_store): Improved handling of stores with a first byte + of zero, but not storing_all_zeros_p. + +2022-05-13 Philipp Tomsich <philipp.tomsich@vrull.eu> + Manolis Tsamis <manolis.tsamis@vrull.eu> + + * config/riscv/riscv.h (CLZ_DEFINED_VALUE_AT_ZERO): Implement. + (CTZ_DEFINED_VALUE_AT_ZERO): Same. + * doc/sourcebuild.texi: add documentation for RISC-V specific + test target keywords + +2022-05-13 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/105597 + * range-op.cc (operator_minus::lhs_op1_relation): Use op1 instead + of the lhs and make sure it is not undefined. + +2022-05-13 Sebastian Pop <spop@amazon.com> + + PR target/105162 + * config/aarch64/aarch64-protos.h (atomic_ool_names): Increase dimension + of str array. + * config/aarch64/aarch64.cc (aarch64_atomic_ool_func): Call + memmodel_from_int and handle MEMMODEL_SYNC_*. + (DEF0): Add __aarch64_*_sync functions. + +2022-05-13 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-fold.cc (fold_using_range::range_of_phi): Use new VREL_* + enumerated values. + * gimple-range-path.cc (maybe_register_phi_relation): Ditto. + * range-op.cc (*::lhs_op1_relation): Return relation_kind, and use + new VREL enumerated values. + (*::lhs_op2_relation): Ditto. + (*::op1_op2_relation): Ditto. + (*::fold_range): Use new VREL enumerated values. + (minus_op1_op2_relation_effect): Ditto. + (range_relational_tests): Ditto. + * range-op.h (fold_range, op1_range, op2_range): Use VREL_VARYING. + (lhs_op1_relation, lhs_op2_relation, op1_op2_relation): Return + relation_kind. + (*_op1_op2_relation): Return relation_kind. + (relop_early_resolve): Use VREL_UNDEFINED. + * value-query.cc (range_query::query_relation): Use VREL_VARYING. + * value-relation.cc (VREL_LAST): Change enumerated value. + (vrel_range_assert): Delete. + (print_relation): Remove range assert. + (rr_negate_table): Adjust table to use new enumerated values.. + (relation_negate): Remove range assert. + (rr_swap_table): Adjust. + (relation_swap): Remove range assert. + (rr_intersect_table): Adjust. + (relation_intersect): Remove range assert. + (rr_union_table): Adjust. + (relation_union): Remove range assert. + (rr_transitive_table): Adjust. + (relation_transitive): Remove range assert. + (equiv_oracle::query_relation): Use new VREL enumerated values. + (equiv_oracle::register_relation): Ditto. + (relation_oracle::register_stmt): Ditto. + (dom_oracle::set_one_relation): Ditto. + (dom_oracle::register_transitives): Ditto. + (dom_oracle::query_relation): Ditto. + (path_oracle::register_relation): Ditto. + (path_oracle::query_relation): Ditto. + * value-relation.h (enum relation_kind_t): New relation_kind. + (*_op1_op2_relation): Adjust prototypes. + +2022-05-13 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-edge.cc (calc_switch_ranges): Check union return value. + * value-range.cc (irange::legacy_verbose_union_): Add return value. + (irange::irange_single_pair_union): New. + (irange::irange_union): Add return value. + * value-range.h (class irange): Adjust prototypes. + +2022-05-13 Andrew MacLeod <amacleod@redhat.com> + + * value-range.cc (irange::legacy_verbose_intersect): Add return value. + (irange::irange_contains_p): New. + (irange::irange_intersect): Add return value. + * value-range.h (class irange): Adjust prototypes. + +2022-05-13 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-cache.cc (ranger_cache::get_global_range): Return the + had_global value instead. + +2022-05-13 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/104547 + * gimple-range-fold.cc (fold_using_range::range_of_range_op): Add + the op1/op2 relation to the relation call. + * range-op.cc (*::lhs_op1_relation): Add param. + (*::lhs_op2_relation): Ditto. + (operator_minus::lhs_op1_relation): New. + (range_relational_tests): Add relation param. + * range-op.h (lhs_op1_relation, lhs_op2_relation): Adjust prototype. + +2022-05-13 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range.cc (gimple_ranger::register_side_effects): First check + if the DEF should be exported as a global. + * tree-vrp.cc (rvrp_folder::pre_fold_bb): Process PHI side effects, + which will export globals. + (execute_ranger_vrp): Remove call to export_global_ranges. + +2022-05-13 Andrew MacLeod <amacleod@redhat.com> + + * value-relation.cc (path_oracle::reset_path): Clear killing_defs. + +2022-05-13 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-cache.cc (ranger_cache::ranger_cache): Start with + worlist truncated. + (ranger_cache::entry_range): Add rfd_mode parameter. + (ranger_cache::exit_range): Ditto. + (ranger_cache::edge_range): New. Incorporate from range_on_edge. + (ranger_cache::range_of_expr): Adjust call to entry_range. + (ranger_cache::range_on_edge): Split to edge_range and call. + (ranger_cache::fill_block_cache): Always invoke range_from_dom. + (ranger_cache::range_from_dom): Make reentrant, add search mode, handle + mutiple predecessors. + (ranger_cache::update_to_nonnull): Adjust call to exit_range. + * gimple-range-cache.h (ranger_cache): Add enum rfd_mode. Adjust + prototypes. + +2022-05-13 Alexandre Oliva <oliva@adacore.com> + + * gimple-harden-conditionals.cc: Include sbitmap.h. + (pass_harden_conditional_branches::execute): Skip new blocks. + (pass_harden_compares::execute): Likewise. + +2022-05-13 Richard Earnshaw <rearnsha@arm.com> + + PR target/105463 + * config/arm/mve.md (*movmisalign<mode>_mve_store): Use + mve_memory_operand. + (*movmisalign<mode>_mve_load): Likewise. + * config/arm/vec-common.md (movmisalign<mode>): Convert to generator + form... + (@movmisalign<mode>): ... thus. Use generic predicates and then + rework operands if they are not valid. For MVE rework to a + narrower element size if the alignment is not high enough. + +2022-05-13 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/arm.cc (mve_vector_mem_operand): Allow SP_REGNUM + when there is no write-back. Fix use when strict is true. + +2022-05-13 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.h (TARGET_HAS_NO_HW_DIVIDE): New macro + definition. + +2022-05-13 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp> + + * config/xtensa/xtensa.md (extvsi, extvsi_internal, extzvsi, + extzvsi_internal): Rename from extv, extv_internal, extzv and + extzv_internal, respectively. + +2022-05-13 Eric Botcazou <ebotcazou@adacore.com> + + * tree-sra.cc (sra_modify_assign): Check that scalar storage order + is the same on the LHS and RHS before rewriting one with the model + of the other. + +2022-05-13 Richard Biener <rguenther@suse.de> + + * gimple-fold.cc (gimple_build): Adjust for new + main API. + * gimple-fold.h (gimple_build): New main APIs with + iterator, insert direction and iterator update. + (gimple_build): New forwarder template. + (clear_padding_type_may_have_padding_p): Remove. + (clear_type_padding_in_mask): Likewise. + (arith_overflowed_p): Likewise. + * fold-const.h (clear_padding_type_may_have_padding_p): Declare. + (clear_type_padding_in_mask): Likewise. + (arith_overflowed_p): Likewise. + * tree-vect-generic.cc (gimplify_build3): Use main gimple_build API. + (gimplify_build2): Likewise. + (gimplify_build1): Likewise. + * ubsan.cc (ubsan_expand_ptr_ifn): Likewise, avoid extra + compare stmt. + * gengtype.cc (open_base_files): Re-order includes. + * builtins.cc: Re-order gimple-fold.h include. + * calls.cc: Likewise. + * cgraphbuild.cc: Likewise. + * cgraphunit.cc: Likewise. + * config/rs6000/rs6000-builtin.cc: Likewise. + * config/rs6000/rs6000-call.cc: Likewise. + * config/rs6000/rs6000.cc: Likewise. + * config/s390/s390.cc: Likewise. + * expr.cc: Likewise. + * fold-const.cc: Likewise. + * function-tests.cc: Likewise. + * gimple-match-head.cc: Likewise. + * gimple-range-fold.cc: Likewise. + * gimple-ssa-evrp-analyze.cc: Likewise. + * gimple-ssa-evrp.cc: Likewise. + * gimple-ssa-sprintf.cc: Likewise. + * gimple-ssa-warn-access.cc: Likewise. + * gimplify.cc: Likewise. + * graphite-isl-ast-to-gimple.cc: Likewise. + * ipa-cp.cc: Likewise. + * ipa-devirt.cc: Likewise. + * ipa-prop.cc: Likewise. + * omp-low.cc: Likewise. + * pointer-query.cc: Likewise. + * range-op.cc: Likewise. + * tree-cfg.cc: Likewise. + * tree-if-conv.cc: Likewise. + * tree-inline.cc: Likewise. + * tree-object-size.cc: Likewise. + * tree-ssa-ccp.cc: Likewise. + * tree-ssa-dom.cc: Likewise. + * tree-ssa-forwprop.cc: Likewise. + * tree-ssa-ifcombine.cc: Likewise. + * tree-ssa-loop-ivcanon.cc: Likewise. + * tree-ssa-math-opts.cc: Likewise. + * tree-ssa-pre.cc: Likewise. + * tree-ssa-propagate.cc: Likewise. + * tree-ssa-reassoc.cc: Likewise. + * tree-ssa-sccvn.cc: Likewise. + * tree-ssa-strlen.cc: Likewise. + * tree-ssa.cc: Likewise. + * value-pointer-equiv.cc: Likewise. + * vr-values.cc: Likewise. + +2022-05-13 Alexandre Oliva <oliva@adacore.com> + + PR rtl-optimization/105455 + * gimple-harden-conditionals.cc (insert_check_and_trap): Set + probabilities for newly-conditional edges. + +2022-05-13 liuhongt <hongtao.liu@intel.com> + + PR tree-optimization/102583 + * tree-ssa-forwprop.cc (simplify_bitfield_ref): Extended to a + contiguous stride in the VEC_PERM_EXPR. + +2022-05-12 Richard Biener <rguenther@suse.de> + + PR rtl-optimization/105577 + * dse.cc (rest_of_handle_dse): Make sure to purge dead EH + edges before running fast DCE via df_analyze. + +2022-05-12 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105562 + * tree-ssa-sccvn.cc (vn_reference_lookup_3): Disambiguate + against all CLOBBER defs if there's not an obvious must-alias + and we are not doing redundant store elimination. + (vn_walk_cb_data::redundant_store_removal_p): New field. + (vn_reference_lookup_pieces): Initialize it. + (vn_reference_lookup): Add argument to specify if we are + doing redundant store removal. + (eliminate_dom_walker::eliminate_stmt): Specify we do. + * tree-ssa-sccvn.h (vn_reference_lookup): Adjust. + +2022-05-12 Haochen Jiang <haochen.jiang@intel.com> + + PR target/104371 + * config/i386/sse.md (vi1avx2const): New define_mode_attr. + (pxor/pcmpeqb/pmovmskb/cmp 0xffff to ptest splitter): + New define_split pattern. + +2022-05-12 Jakub Jelinek <jakub@redhat.com> + + * gimplify.cc (gimplify_omp_depend): Don't build_fold_addr_expr + if null_pointer_node. + (gimplify_scan_omp_clauses): Likewise. + * tree-pretty-print.cc (dump_omp_clause): Print null_pointer_node + as omp_all_memory. + +2022-05-11 Patrick Palka <ppalka@redhat.com> + + * tree.h (TREE_VEC_BEGIN): Define. + (TREE_VEC_END): Correct 'length' member access. + (class tree_vec_range): Define. + +2022-05-11 Segher Boessenkool <segher@kernel.crashing.org> + + * config/rs6000/rs6000.md: Use wa instead of <Fv>. + +2022-05-11 Segher Boessenkool <segher@kernel.crashing.org> + + * config/rs6000/rs6000.md: Use d instead of <Ff>. + +2022-05-11 Segher Boessenkool <segher@kernel.crashing.org> + + * config/rs6000/constraints.md (register_constraint "f"): Use + RS6000_CONSTRAINT_d. + * config/rs6000/rs6000.cc (rs6000_debug_reg_global): Do not handle + RS6000_CONSTRAINT_f. + (rs6000_init_hard_regno_mode_ok): Ditto. Reorder and simplify a bit. + * config/rs6000/rs6000.h (r6000_reg_class_enum): Delete + RS6000_CONSTRAINT_d. + +2022-05-11 Richard Biener <rguenther@suse.de> + + * gimple-fold.h (gimple_build): Use variadic template + functions for the gimple_build API forwarders without + location_t argument. + +2022-05-11 Siddhesh Poyarekar <siddhesh@gotplt.org> + + PR middle-end/70090 + * asan.cc (initialize_sanitizer_builtins): Register + __builtin_dynamic_object_size if necessary. + +2022-05-11 Richard Biener <rguenther@suse.de> + + PR rtl-optimization/105559 + * cfgrtl.cc (delete_insn_and_edges): Only perform search to BB_END + for non-debug insns. + +2022-05-11 Richard Biener <rguenther@suse.de> + + * generic-match-head.cc: Include tree-eh.h. + * match.pd ((cond ...) cmp X): New simplification inspired + by fold_binary_op_with_conditional_arg. + (eq/ne (cmp ...) true/false): Likewise. + +2022-05-11 Thomas Schwinge <thomas@codesourcery.com> + + * doc/install.texi: Don't document '--with-hsa-runtime', + '--with-hsa-runtime-include', '--with-hsa-runtime-lib'. + +2022-05-11 Martin Liska <mliska@suse.cz> + + PR other/105527 + * doc/install.texi: Document the configure option --with-zstd. + +2022-05-11 Martin Liska <mliska@suse.cz> + + * common/config/i386/cpuinfo.h (has_cpu_feature): Directly + compute index in cpu_features2. + (set_cpu_feature): Likewise. + * config/i386/i386-builtins.cc (fold_builtin_cpu): Also remove + loop for cpu_features2 and use NOP_EXPRs. + +2022-05-11 Richard Biener <rguenther@suse.de> + + PR bootstrap/105551 + * opts.cc (finish_options): Also disable var-tracking if + !DWARF2_DEBUGGING_INFO. + +2022-05-11 liuhongt <hongtao.liu@intel.com> + + PR target/104915 + * config/i386/sse.md (*vec_set<mode>_0_zero_extendhi): New + pre_reload define_insn_and_split. + (*vec_setv2di_0_zero_extendhi_1): Ditto. + (*vec_set<mode>_0_zero_extendsi): Ditto. + (*vec_setv2di_0_zero_extendsi_1): Ditto. + (ssewvecmode): New mode attr. + (ssewvecmodelower): Ditto. + (ssepackmodelower): Ditto. + +2022-05-11 Kewen Lin <linkw@linux.ibm.com> + + * config/rs6000/constraints.md (register constraint v): Use + rs6000_constraints[RS6000_CONSTRAINT_v] instead of ALTIVEC_REGS. + +2022-05-11 Martin Liska <mliska@suse.cz> + + PR target/105355 + * config/riscv/riscv.opt: Remove Separate from + -msmall-data-limit=. + * optc-gen.awk: Report error for the described situation. + * gcc.cc: Use Separate syntax. + * opts.cc (gen_command_line_string): Change option name. + +2022-05-11 Haochen Gui <guihaoc@gcc.gnu.org> + + PR target/105414 + * match.pd (minmax): Skip constant folding for fmin/fmax when both + arguments are sNaN or one is sNaN and another is NaN. + +2022-05-10 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/105528 + * gimple-isel.cc (gimple_expand_vec_set_expr): After gsi_remove + set *gsi to gsi_for_stmt (ass_stmt). Fix up function comment. + +2022-05-10 Segher Boessenkool <segher@kernel.crashing.org> + + * doc/md.texi (Defining Mode Iterators): Correct example replacement + text. + +2022-05-10 Maciej W. Rozycki <macro@embecosm.com> + + * config/riscv/riscv.md (UNSPEC_FMIN, UNSPEC_FMAX): New + constants. + (fmin<mode>3, fmax<mode>3): New insns. + +2022-05-10 Richard Biener <rguenther@suse.de> + + * tree-if-conv.cc (fold_build_cond_expr): Use + match-and-simplify to simplify the condition. + (ifcvt_follow_ssa_use_edges): Remove. + (predicate_scalar_phi): Use follow_all_ssa_edges. + +2022-05-10 Thomas Schwinge <thomas@codesourcery.com> + + PR middle-end/100400 + * omp-oacc-kernels-decompose.cc + (visit_loops_in_gang_single_region) <GIMPLE_OMP_FOR>: Explicitly + call 'internal_error'. + +2022-05-10 Richard Biener <rguenther@suse.de> + + PR middle-end/105537 + * toplev.cc (process_options): Move flag_var_tracking + handling ... + * opts.cc (finish_options): ... here. + +2022-05-10 Martin Liska <mliska@suse.cz> + + * basic-block.h (struct basic_block_d): Use void * + instead PTR. + * cfgloop.h: Likewise. + * cgraph.h: Likewise. + * gengtype-state.cc (state_ident_by_name): Likewise. + (record_type): Likewise. + (read_state_already_seen_type): Likewise. + * gengtype.cc (dump_type): Likewise. + (input_file_by_name): Likewise. + (main): Likewise. + * ggc-common.cc (ggc_cleared_alloc_ptr_array_two_args): Likewise. + * ipa-utils.h (struct ipa_dfs_info): Likewise. + * plugin.cc (htab_hash_plugin): Likewise. + +2022-05-10 Richard Biener <rguenther@suse.de> + + * flags.h (dwarf_debuginfo_p): Add opts argument, guard + API with !GENERATOR_FILE. + * opts.cc (global_options): Poison. + (global_options_set): Likewise. + (finish_options): Refer to options via opts. + +2022-05-10 Uroš Bizjak <ubizjak@gmail.com> + Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/i386.md (*testqi_1_maybe_si): Prefer shorter SImode + alternative when optimizing for size and the immediate operand is + const_0_to_127_operand. + (*andqi_2_maybe_si): Likewise. + * config/i386/predicates.md (const_0_to_127_operand): New predicate. + +2022-05-10 Roger Sayle <roger@nextmovesoftware.com> + + * tree-chrec.cc (chrec_apply): Attempt to fold the linear chrec + "{a, +, a} (x-1)" as "a*x", as the number of loop iterations, x-1, + can't be negative. + +2022-05-10 Eric Botcazou <ebotcazou@adacore.com> + + PR target/105292 + * config/sparc/sparc.cc (sparc_vectorize_vec_perm_const): Return + true only for 8-byte vector modes. + +2022-05-10 Siddhesh Poyarekar <siddhesh@gotplt.org> + + PR middle-end/70090 + * ubsan.cc (ubsan_expand_objsize_ifn): Allow non-constant SIZE. + (instrument_object_size): Get dynamic object size expression. + +2022-05-10 Jiufu Guo <guojiufu@linux.ibm.com> + + PR preprocessor/101168 + * config/rs6000/rs6000-c.cc (rs6000_macro_to_expand): + Avoid empty identifier. + +2022-05-09 Qing Zhao <qing.zhao@oracle.com> + + PR target/101891 + * config/i386/i386.cc (zero_call_used_regno_mode): use V2SImode + as a generic MMX mode instead of V4HImode. + (zero_all_mm_registers): Use SET to zero instead of MOV for + zeroing scratch registers. + (ix86_zero_call_used_regs): Likewise. + +2022-05-09 liuhongt <hongtao.liu@intel.com> + + PR target/105354 + * config/i386/i386-expand.cc + (expand_vec_perm_pslldq_psrldq_por): New function. + (ix86_expand_vec_perm_const_1): Try + expand_vec_perm_pslldq_psrldq_por for both 3-instruction and + 4/5-instruction sequence. + +2022-05-09 Martin Liška <mliska@suse.cz> + + * basic-block.h (STATIC_ASSERT): Use normal STATIC_ASSERT. + * system.h (STATIC_ASSERT): Define as static_assert for C++ + and fallback to array index in C. + +2022-05-09 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105517 + * tree-ssa-sccvn.cc (vn_reference_lookup): Make sure the accumulated + offset can be represented in the POINTER_PLUS_EXPR IL. + (vn_reference_insert): Likewise. + * poly-int.h (sext_hwi): Add poly version of sext_hwi. + +2022-05-09 Richard Biener <rguenther@suse.de> + + * match.pd: Remove #if GIMPLE guards around ! using patterns. + +2022-05-09 liuhongt <hongtao.liu@intel.com> + + PR target/105072 + * config/i386/sse.md (*sse4_1_<code>v2qiv2di2<mask_name>_1): + New define_insn. + (*sse4_1_zero_extendv2qiv2di2_2): New pre_reload + define_insn_and_split. + +2022-05-09 Alex Coplan <alex.coplan@arm.com> + + * cgraph.cc (cgraph_node::get_create): Don't dump if the current + symtab state is PARSING. + +2022-05-09 Martin Liska <mliska@suse.cz> + + * system.h (LIKELY): Define. + (UNLIKELY): Likewise. + * domwalk.cc (sort_bbs_postorder): Use {,UN}LIKELY + macros. + * dse.cc (set_position_unneeded): Likewise. + (set_all_positions_unneeded): Likewise. + (any_positions_needed_p): Likewise. + (all_positions_needed_p): Likewise. + * expmed.cc (flip_storage_order): Likewise. + * genmatch.cc (dt_simplify::gen_1): Likewise. + * ggc-common.cc (gt_pch_save): Likewise. + * print-rtl.cc: Likewise. + * rtl-iter.h (T>::array_type::~array_type): Likewise. + (T>::next): Likewise. + * rtl-ssa/internals.inl: Likewise. + * rtl-ssa/member-fns.inl: Likewise. + * rtlanal.cc (T>::add_subrtxes_to_queue): Likewise. + (rtx_properties::try_to_add_dest): Likewise. + * rtlanal.h (growing_rtx_properties::repeat): Likewise. + (vec_rtx_properties_base::~vec_rtx_properties_base): Likewise. + * simplify-rtx.cc (simplify_replace_fn_rtx): Likewise. + * sort.cc (likely): Likewise. + (mergesort): Likewise. + * wide-int.h (wi::eq_p): Likewise. + (wi::ltu_p): Likewise. + (wi::cmpu): Likewise. + (wi::bit_and): Likewise. + (wi::bit_and_not): Likewise. + (wi::bit_or): Likewise. + (wi::bit_or_not): Likewise. + (wi::bit_xor): Likewise. + (wi::add): Likewise. + (wi::sub): Likewise. + +2022-05-09 Kito Cheng <kito.cheng@sifive.com> + + * config/riscv/arch-canonicalize: Handle g correctly. + +2022-05-07 Marek Polacek <polacek@redhat.com> + + PR c++/101833 + PR c++/47634 + * tree-core.h (struct attribute_spec): Update comment for HANDLER. + +2022-05-06 Jason Merrill <jason@redhat.com> + + * diagnostic-color.cc: Add fnname and targs color entries. + * doc/invoke.texi: Document them. + +2022-05-06 Jason Merrill <jason@redhat.com> + + * vec.h (vec::iterate): Fix comment. + +2022-05-06 Michael Meissner <meissner@linux.ibm.com> + + PR target/102059 + * config/rs6000/rs6000.cc (rs6000_can_inline_p): Ignore -mpower8-fusion + and -mpower10-fusion options for inlining purposes. + +2022-05-06 Christophe Lyon <christophe.lyon@arm.com> + + * config/aarch64/iterators.md (GPF_TF_F16): Delete. + +2022-05-06 Marcel Vollweiler <marcel@codesourcery.com> + + * omp-low.cc (omp_runtime_api_call): Added target_is_accessible to + omp_runtime_apis array. + +2022-05-06 Hafiz Abid Qadeer <abidh@codesourcery.com> + + * omp-low.cc (omp_maybe_offloaded_ctx): New prototype. + (scan_sharing_clauses): Check a restriction on allocate clause. + +2022-05-05 Sandra Loosemore <sandra@codesourcery.com> + + * gimplify.cc (gimplify_omp_for): Update messages for SCHEDULED + and ORDERED clause conflict errors. Add check for GRAINSIZE and + NUM_TASKS on TASKLOOP. + +2022-05-05 Martin Liska <mliska@suse.cz> + + * genautomata.cc (create_composed_state): Remove dead code. + * graphite-poly.cc (print_pdrs): Likewise. + * lto-wrapper.cc (run_gcc): Likewise. + * tree-switch-conversion.cc (switch_decision_tree::balance_case_nodes): + Likewise. + +2022-05-05 Martin Liska <mliska@suse.cz> + + * tree-profile.cc (gimple_gen_ic_profiler): Prefix names with + PROF_*. + (gimple_gen_time_profiler): Likewise. + +2022-05-05 Martin Liska <mliska@suse.cz> + + * value-prof.cc (stream_out_histogram_value): Remove sanity + checking. + +2022-05-05 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104162 + * tree-ssa-sccvn.cc (vn_reference_lookup): Handle + &MEM[_1 + 5].a[i] like a POINTER_PLUS_EXPR if the offset + becomes invariant. + (vn_reference_insert): Likewise. + +2022-05-05 Richard Biener <rguenther@suse.de> + + * tree-core.h (tree_real_cst::real_cst_ptr): Remove pointer + to real_value field. + (tree_real_cst::value): Add real_value field. + * tree.h (TREE_REAL_CST_PTR): Adjust. + * tree.cc (build_real): Remove separate allocation. + * tree-streamer-in.cc (unpack_ts_real_cst_value_fields): + Likewise. + +2022-05-05 Richard Biener <rguenther@suse.de> + + * tree-ssa-ifcombine.cc (bb_no_side_effects_p): Avoid executing + divisions with undefined overflow unconditionally. + (pass_tree_ifcombine::execute): Rewrite stmts with undefined + overflow to defined. + +2022-05-05 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105484 + * gimple-isel.cc (gimple_expand_vec_set_expr): Clean EH, return + whether the CFG changed. + (gimple_expand_vec_exprs): When the CFG changed, clean it up. + +2022-05-05 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104595 + * tree-vect-patterns.cc (vect_recog_bool_pattern): For + COND_EXPR do not fail if check_bool_pattern returns false. + +2022-05-04 Tobias Burnus <tobias@codesourcery.com> + + * omp-low.cc (lower_omp_target): Fix use_device_{addr,ptr} with list + item that is in an outer data-sharing clause. + +2022-05-04 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104658 + * tree-vect-slp.cc (vect_slp_convert_to_external): Do not + create VECTOR_BOOLEAN_TYPE_P extern defs. Reset the vector + type on nodes we promote. + (vectorizable_bb_reduc_epilogue): Deal with externalized + root. + * tree-vect-stmts.cc (vect_maybe_update_slp_op_vectype): Do + not allow VECTOR_BOOLEAN_TYPE_P extern defs. + +2022-05-04 Richard Biener <rguenther@suse.de> + + PR tree-optimization/103116 + * tree-vect-stmts.cc (get_group_load_store_type): Handle the + case we need peeling for gaps even though GROUP_GAP is zero. + +2022-05-04 Martin Liska <mliska@suse.cz> + + * gengtype-state.cc (read_a_state_token): Remove dead code. + * ipa-profile.cc (ipa_profile_read_summary_section): Likewise. + +2022-05-04 Richard Biener <rguenther@suse.de> + + * gimplify.cc (gimplify_init_constructor): First gimplify, + then simplify the result to a VECTOR_CST. + +2022-05-04 Jakub Jelinek <jakub@redhat.com> + + * genconditions.cc (write_conditions): Append a { nullptr, -1 } + element at the end of insn_conditions. + (write_writer): Use ARRAY_SIZE (insn_conditions) - 1 instead of + ARRAY_SIZE (insn_conditions). + +2022-05-04 Christophe Lyon <christophe.lyon@arm.com> + + PR target/104662 + * config/arm/arm.cc (simd_valid_immediate): Exit when input is a + vector of booleans and MVE is not enabled. + +2022-05-04 Richard Biener <rguenther@suse.de> + + PR debug/105158 + * tree-cfgcleanup.cc (move_debug_stmts_from_forwarder): + Move debug stmts to the predecessor if moving to the + destination is not possible. + (remove_forwarder_block): Adjust. + (remove_forwarder_block_with_phi): Likewise. + +2022-05-03 Roger Sayle <roger@nextmovesoftware.com> + + PR tree-optimization/102950 + * range-op.cc (wi_optimize_signed_bitwise_op): New function to + determine bounds of bitwise operations on signed types. + (operator_bitwise_and::wi_fold): Call the above function. + (operator_bitwise_or::wi_fold): Likewise. + (operator_bitwise_xor::wi_fold): Likewise. Additionally, the + result can't be zero if the operands can't be equal. + +2022-05-03 Iain Sandoe <iain@sandoe.co.uk> + + * config/darwin.cc (darwin_label_is_anonymous_local_objc_name): Make + protocol class methods linker-visible. + +2022-05-03 Uroš Bizjak <ubizjak@gmail.com> + + PR target/105079 + * config/i386/sse.md (*vec_extract<mode>_0_mem): New pre-reload + define_insn_and_split pattern. + +2022-05-03 Richard Biener <rguenther@suse.de> + + PR middle-end/105083 + * tree-scalar-evolution.cc (scev_initialize): Verify we + have appropriate loop state. + * tree-ssa-dce.cc (perform_tree_ssa_dce): Re-order SCEV and + loop init and finalization. + +2022-05-03 Richard Biener <rguenther@suse.de> + + PR middle-end/105461 + * opts.cc (finish_options): Match the condition to + disable flag_var_tracking to that of process_options. + +2022-05-03 Richard Biener <rguenther@suse.de> + + * opts.cc: #undef OPTIONS_SET_P. + (finish_options): Use opts_set instead of OPTIONS_SET_P. + +2022-05-03 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105394 + * tree-vect-generic.cc (expand_vector_condition): Adjust + comp_width for non-integer mode masks as well. + +2022-05-03 Marcel Vollweiler <marcel@codesourcery.com> + + * omp-low.cc (omp_runtime_api_call): Added get_mapped_ptr to + omp_runtime_apis array. + +2022-05-02 Richard Biener <rguenther@suse.de> + + * tree-scalar-evolution.cc (expression_expensive_p): + Never consider mismatched calls as cheap. + +2022-05-02 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104240 + * tree-vect-slp.cc (op1_op0_map): New. + (vect_get_operand_map): Handle compares. + (vect_build_slp_tree_1): Support swapped operands for + tcc_comparison. + +2022-05-02 Jakub Jelinek <jakub@redhat.com> + + PR debug/105415 + * cfgexpand.cc (expand_debug_expr): Don't make_decl_rtl_for_debug + if there is no symtab node for the VAR_DECL. + +2022-05-02 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * gcov-io.cc (gcov_rewrite): Clear the file error status. + +2022-05-02 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105437 + * tree-vect-slp.cc (vect_schedule_slp_node): Handle the + case where last_stmt alters control flow. + +2022-05-02 Richard Biener <rguenther@suse.de> + + * dojump.cc (do_jump): Use CASE_CONVERT. + * tree-ssa-dom.cc (edge_info::derive_equivalences): Likewise. + +2022-05-02 Jakub Jelinek <jakub@redhat.com> + + * system.h: Include initializer_list. + +2022-05-01 Segher Boessenkool <segher@kernel.crashing.org> + + * config/rs6000/constraints.md (Y constraint): Fix comment. + +2022-05-01 Aldy Hernandez <aldyh@redhat.com> + + * tree-ssanames.cc (set_range_info): Denormalize VR_VARYING to + VR_RANGE before passing a piecewise range to set_range_info_raw. + +2022-04-30 Patrick Palka <ppalka@redhat.com> + + * gengtype.cc (adjust_field_tree_exp): Remove. + (adjust_field_type): Don't handle the "tree_exp" special attribute. + * tree-core.h (struct tree_exp): Remove "special" and "desc" + attributes. Add "length" attribute. + +2022-04-29 Martin Jambor <mjambor@suse.cz> + + PR ipa/100413 + * cgraph.cc (cgraph_node::remove): Release body of the node this + is clone_of if appropriate. + +2022-04-29 Uroš Bizjak <ubizjak@gmail.com> + + PR target/51954 + * config/i386/i386.md (adcl/neg -> sbb peephole): New peephole2. + +2022-04-29 Richard Biener <rguenther@suse.de> + + * gimple-expr.cc (is_gimple_condexpr): Adjust comment. + (canonicalize_cond_expr_cond): Move here from gimple.cc, + allow both COND_EXPR and GIMPLE_COND forms. + * gimple-expr.h (canonicalize_cond_expr_cond): Declare. + * gimple.cc (canonicalize_cond_expr_cond): Remove here. + * gimple.h (canonicalize_cond_expr_cond): Likewise. + * gimple-loop-versioning.cc (loop_versioning::version_loop): + Use is_gimple_condexpr_for_cond. + * tree-parloops.cc (gen_parallel_loop): Likewise. + * tree-ssa-ifcombine.cc (ifcombine_ifandif): Check for + a proper cond expr after canonicalize_cond_expr_cond. + Use is_gimple_condexpr_for_cond where appropriate. + * tree-ssa-loop-manip.cc (determine_exit_conditions): Likewise. + * tree-vect-loop-manip.cc (slpeel_add_loop_guard): Likewise. + +2022-04-29 Richard Biener <rguenther@suse.de> + + * gimple-iterator.h (gsi_after_labels): Add overload for + gimple_seq. + (gsi_start_1): Rename to gsi_start and take a reference. + (gsi_last_1): Likewise. + * gimple-iterator.cc (gsi_for_stmt): Use gsi_start. + * omp-low.cc (lower_rec_input_clauses): Likewise. + (lower_omp_scan): Likewise. + +2022-04-29 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105431 + * tree-ssa-math-opts.cc (powi_as_mults_1): Make n unsigned. + (powi_as_mults): Use absu_hwi. + (gimple_expand_builtin_powi): Remove now pointless n != -n + check. + +2022-04-29 Aldy Hernandez <aldyh@redhat.com> + + * range-op.cc (empty_range_varying): Move to range-op.h. + (range_true): Move to range.h. + (range_false): Same. + (range_true_and_false): Same. + (enum bool_range_state): Move to range-op.h. + (relop_early_resolve): Same. + (operator_equal::op1_op2_relation): Abstract code to... + (equal_op1_op2_relation): ...here. + (operator_not_equal::op1_op2_relation): Abstract code to... + (not_equal_op1_op2_relation): ...here. + (operator_lt::op1_op2_relation): Abstract code to... + (lt_op1_op2_relation): ...here. + (operator_le::op1_op2_relation): Abstract code to... + (le_op1_op2_relation): ...here. + (operator_gt::op1_op2_relation): Abstract code to... + (gt_op1_op2_relation): ...here. + (operator_ge::op1_op2_relation): Abstract code to... + (ge_op1_op2_relation): ...here. + (class range_op_table): Move to range-op.h. + * range-op.h (equal_op1_op2_relation): Moved from range-op.cc. + (not_equal_op1_op2_relation): Same. + (lt_op1_op2_relation): Same. + (le_op1_op2_relation): Same. + (gt_op1_op2_relation): Same. + (ge_op1_op2_relation): Same. + (enum bool_range_state): Same. + (get_bool_state): Same. + (empty_range_varying): Same. + (relop_early_resolve): Same. + (class range_op_table): Same. + * range.h (range_true): Same. + (range_false): Same. + (range_true_and_false): Same. + +2022-04-29 Aldy Hernandez <aldyh@redhat.com> + + * gimple-fold.cc (size_must_be_zero_p): Use reference + instead of pointer + * gimple-ssa-evrp-analyze.cc + (evrp_range_analyzer::record_ranges_from_incoming_edge): Rename + intersect to legacy_verbose_intersect. + * ipa-cp.cc (ipcp_vr_lattice::meet_with_1): Use reference instead + of pointer. + * tree-ssa-dom.cc (dom_jt_simplifier::simplify): Use value_range + instead of value_range_equiv. + * tree-vrp.cc (extract_range_from_plus_minus_expr): Use reference + instead of pointer. + (find_case_label_range): Same. + * value-range-equiv.cc (value_range_equiv::intersect): Rename to... + (value_range_equiv::legacy_verbose_intersect): ...this. + (value_range_equiv::union_): Rename to... + (value_range_equiv::legacy_verbose_union_): ...this. + * value-range-equiv.h (class value_range_equiv): Rename union and + intersect to legacy_verbose_{intersect,union}. + * value-range.cc (irange::union_): Rename to... + (irange::legacy_verbose_union_): ...this. + (irange::intersect): Rename to... + (irange::legacy_verbose_intersect): ...this. + * value-range.h (irange::union_): Rename union_ to + legacy_verbose_union. + (irange::intersect): Rename intersect to legacy_verbose_intersect. + * vr-values.cc (vr_values::update_value_range): Same. + (vr_values::extract_range_for_var_from_comparison_expr): Same. + (vr_values::extract_range_from_cond_expr): Rename union_ to + legacy_verbose_union. + (vr_values::extract_range_from_phi_node): Same. + +2022-04-29 Aldy Hernandez <aldyh@redhat.com> + + * gimple-ssa-evrp-analyze.cc + (evrp_range_analyzer::set_ssa_range_info): Use *range_info methods + that take a range. + * gimple-ssa-sprintf.cc (try_substitute_return_value): Same. + * ipa-prop.cc (ipcp_update_vr): Same. + * tree-inline.cc (remap_ssa_name): Same. + * tree-ssa-copy.cc (fini_copy_prop): Same. + * tree-ssa-math-opts.cc (optimize_spaceship): Same. + * tree-ssa-phiopt.cc (replace_phi_edge_with_variable): Same. + * tree-ssa-pre.cc (insert_into_preds_of_block): Same. + * tree-ssa-sccvn.cc (eliminate_dom_walker::eliminate_stmt): Same. + * tree-ssa-strlen.cc (set_strlen_range): Same. + (strlen_pass::handle_builtin_string_cmp): Same. + * tree-ssanames.cc (set_range_info): Make static. + (duplicate_ssa_name_range_info): Make static and add a new variant + calling the static. + * tree-ssanames.h (set_range_info): Remove version taking wide ints. + (duplicate_ssa_name_range_info): Remove version taking a + range_info_def and replace with a version taking SSA names. + * tree-vect-loop-manip.cc (vect_gen_vector_loop_niters): Use *range_info methods + that take a range. + (vect_do_peeling): Same. + * tree-vrp.cc (vrp_asserts::remove_range_assertions): Same. + * vr-values.cc (simplify_truth_ops_using_ranges): Same. + +2022-04-29 Aldy Hernandez <aldyh@redhat.com> + + * value-range.h (irange::irange): Use set_undefined. + +2022-04-29 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-cache.h (non_null_ref::adjust_range): Do not use + irange::intersect (wide_int, wide_int). + * gimple-range-fold.cc (adjust_pointer_diff_expr): Same. + (adjust_imagpart_expr): Same. + * value-range.h (irange::intersect (wide_int, wide_int)): Make + private. + +2022-04-29 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104322 + * tree-vect-loop.cc (vectorizable_reduction): Remove dead code. + +2022-04-29 Richard Biener <rguenther@suse.de> + + PR middle-end/105376 + * tree.cc (build_real): Special case dconst* arguments + for decimal floating point types. + +2022-04-28 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * doc/gcov.texi (Profiling and Test Coverage in Freestanding + Environments): New section. + +2022-04-28 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * doc/gcov-tool.texi: Document merge-stream subcommand. + * doc/invoke.texi (fprofile-info-section): Mention merge-stream + subcommand of gcov-tool. + * gcov-tool.cc (gcov_profile_merge_stream): Declare. + (print_merge_stream_usage_message): New. + (merge_stream_usage): Likewise. + (do_merge_stream): Likewise. + (print_usage): Call print_merge_stream_usage_message(). + (main): Call do_merge_stream() to execute merge-stream subcommand. + +2022-04-28 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * gcov-io.cc (gcov_file_error): New enum. + (gcov_var): Use gcov_file_error enum for the error member. + (gcov_open): Use GCOV_FILE_NO_ERROR. + (gcov_close): Use GCOV_FILE_WRITE_ERROR. + (gcov_write): Likewise. + (gcov_write_unsigned): Likewise. + (gcov_write_string): Likewise. + (gcov_read_bytes): Set error code if EOF is reached. + (gcov_read_counter): Use GCOV_FILE_COUNTER_OVERFLOW. + +2022-04-28 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * gcov-io.cc (GCOV_MODE_STDIN): Define. + (gcov_position): For gcov-tool, return calculated position if file is + stdin. + (gcov_open): For gcov-tool, use stdin if filename is NULL. + (gcov_close): For gcov-tool, do not close stdin. + (gcov_read_bytes): For gcov-tool, update position if file is stdin. + (gcov_sync): For gcov-tool, discard input if file is stdin. + +2022-04-28 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * doc/invoke.texi (fprofile-info-section): Mention + __gcov_filename_to_gcfn(). Use "freestanding" to match with C11 + standard language. Fix minor example code issues. + * gcov-io.h (GCOV_FILENAME_MAGIC): Define and document. + +2022-04-28 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * gcov-io.cc (gcov_seek): Make it static. + * gcov-io.h (struct gcov_summary): Do not mention gcov_seek(). + +2022-04-28 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * gcov-tool.cc (gcov_do_dump): Add mode parameter. + (gcov_output_files): Open files for reading and writing. + +2022-04-28 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * gcov-io.cc (gcov_open): Always use the mode parameter. + * gcov-io.h (gcov_open): Declare it unconditionally. + +2022-04-28 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * gcov-tool.cc (gcov_profile_merge): Adjust return type. + (profile_merge): Allow merging of directories which contain no profile + files. + +2022-04-28 David Malcolm <dmalcolm@redhat.com> + + * doc/invoke.texi (-fdump-analyzer-feasibility): Mention the + fpath.txt output. + +2022-04-28 Jakub Jelinek <jakub@redhat.com> + + * config/i386/i386-expand.cc (ix86_expand_int_movcc): Create a + temporary only if out overlaps compare_op, not when it overlaps + op0 or op1. + +2022-04-28 Jakub Jelinek <jakub@redhat.com> + + PR lto/105399 + * cgraph.cc (cgraph_node::verify_node): Don't verify + semantic_interposition flag against + opt_for_fn (decl, flag_semantic_interposition) for aliases in lto1. + +2022-04-28 Jakub Jelinek <jakub@redhat.com> + + PR target/105331 + * config/i386/i386.cc (ix86_gimplify_va_arg): Mark va_arg_tmp + temporary TREE_ADDRESSABLE before trying to gimplify ADDR_EXPR + of it. + +2022-04-28 Jonathan Wakely <jwakely@redhat.com> + + * doc/install.texi (Configuration): Remove misleading text + around LE PowerPC Linux multilibs. + +2022-04-28 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + + PR d/103528 + * doc/install.texi (Tools/packages necessary for building GCC) + (GDC): Document libphobos requirement. + (Host/target specific installation notes for GCC, *-*-solaris2*): + Document libphobos and GDC specifics. + +2022-04-28 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105219 + * tree-vect-loop.cc (vect_transform_loop): Disable + special code narrowing the vectorized epilogue max + iterations when peeling for alignment or gaps was in effect. + +2022-04-28 Xi Ruoyao <xry111@mengyan1223.wang> + + * config/loongarch/loongarch.cc + (loongarch_flatten_aggregate_field): Ignore empty fields for + RECORD_TYPE. + +2022-04-27 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/loongarch.md: Add fdiv define_expand template, + then generate floating-point division and floating-point reciprocal + instructions. + +2022-04-27 Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/loongarch.md: Add '(clobber (mem:BLK (scratch)))' + to PLV instruction templates. + +2022-04-27 Richard Biener <rguenther@suse.de> + + PR middle-end/104492 + * gimple-ssa-warn-access.cc + (pass_waccess::warn_invalid_pointer): Exclude equality compare + diagnostics for all kind of invalidations. + (pass_waccess::check_dangling_uses): Fix post-dominator query. + (pass_waccess::check_pointer_uses): Likewise. + +2022-04-27 Andreas Krebbel <krebbel@linux.ibm.com> + + PR target/102024 + * config/s390/s390-protos.h (s390_function_arg_vector): Remove + prototype. + * config/s390/s390.cc (s390_single_field_struct_p): New function. + (s390_function_arg_vector): Invoke s390_single_field_struct_p. + (s390_function_arg_float): Likewise. + +2022-04-27 Jakub Jelinek <jakub@redhat.com> + + PR sanitizer/105396 + * asan.cc (asan_redzone_buffer::emit_redzone_byte): Handle the case + where offset is bigger than off but smaller than m_prev_offset + 32 + bits by pushing one or more 0 bytes. Sink the + m_shadow_bytes.safe_push (value); flush_if_full (); statements from + all cases to the end of the function. + +2022-04-27 Kewen Lin <linkw@linux.ibm.com> + + PR target/105271 + * config/rs6000/rs6000-builtins.def (NEG_V2DI): Move to [power8-vector] + stanza. + +2022-04-26 Thomas Schwinge <thomas@codesourcery.com> + + * config/gcn/gcn.cc (gcn_print_lds_decl): Make "gang-private + data-share memory exhausted" error more verbose. + +2022-04-26 Martin Liska <mliska@suse.cz> + + PR lto/105364 + * lto-wrapper.cc (print_lto_docs_link): Use global_dc. + (run_gcc): Parse OPT_fdiagnostics_urls_. + (main): Initialize global_dc. + +2022-04-26 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/105314 + * ifcvt.cc (noce_try_store_flag_mask): Don't require that the non-zero + operand is equal to if_info->x, instead use the non-zero operand + as one of the operands of AND with if_info->x as target. + +2022-04-26 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/105374 + * tree-ssa-reassoc.cc (eliminate_redundant_comparison): Punt if + !fold_convertible_p rather than assuming fold_convert must succeed. + +2022-04-26 Jakub Jelinek <jakub@redhat.com> + + PR target/105367 + * config/i386/i386.cc (ix86_veclibabi_svml, ix86_veclibabi_acml): Pass + el_mode == DFmode ? double_type_node : float_type_node instead of + TREE_TYPE (type_in) as first arguments to mathfn_built_in. + +2022-04-25 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/104308 + * gimple-fold.cc (gimple_fold_builtin_memory_op): Explicitly set + the location of new_stmt in all places that don't already set it, + whether explicitly, or via a call to gsi_replace. + +2022-04-25 Paul A. Clarke <pc@us.ibm.com> + + * doc/extend.texi (Other Builtins): Correct reference to 'modff'. + +2022-04-25 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/105276 + * gimple-range.cc (gimple_ranger::prefill_stmt_dependencies): Include + existing global range with calculated value. + +2022-04-25 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105368 + * tree-ssa-math-opts.cc (powi_cost): Use absu_hwi. + +2022-04-25 Richard Biener <rguenther@suse.de> + + PR tree-optimization/100810 + * tree-ssa-loop-ivopts.cc (struct iv_cand): Add involves_undefs flag. + (find_ssa_undef): New function. + (add_candidate_1): Avoid adding derived candidates with + undefined SSA names and mark the original ones. + (determine_group_iv_cost_generic): Reject rewriting + uses with a different IV when that involves undefined SSA names. + +2022-04-25 Steven G. Kargl <kargl@gcc.gnu.org> + + PR target/89125 + * config/freebsd.h: Define TARGET_LIBC_HAS_FUNCTION to be + bsd_libc_has_function. + * targhooks.cc (bsd_libc_has_function): New function. + Expand the supported math functions to inclue C99 libm. + * targhooks.h (bsd_libc_has_function): New Prototype. + +2022-04-25 Richard Biener <rguenther@suse.de> + + PR rtl-optimization/105231 + * combine.cc (distribute_notes): Assert that a REG_EH_REGION + with landing pad > 0 is from i3. Put any REG_EH_REGION note + on i3 or drop it if the insn can not trap. + (try_combine): Ensure that we can merge REG_EH_REGION notes + with non-call exceptions. Ensure we are not splitting a + trapping part of an insn with non-call exceptions when there + is any REG_EH_REGION note to preserve. + +2022-04-25 Hongyu Wang <hongyu.wang@intel.com> + + PR target/105339 + * config/i386/avx512fintrin.h (_mm512_scalef_round_pd): + Add parentheses for parameters and djust format. + (_mm512_mask_scalef_round_pd): Ditto. + (_mm512_maskz_scalef_round_pd): Ditto. + (_mm512_scalef_round_ps): Ditto. + (_mm512_mask_scalef_round_ps): Ditto. + (_mm512_maskz_scalef_round_ps): Ditto. + (_mm_scalef_round_sd): Use _mm_undefined_pd. + (_mm_scalef_round_ss): Use _mm_undefined_ps. + (_mm_mask_scalef_round_sd): New macro. + (_mm_mask_scalef_round_ss): Ditto. + (_mm_maskz_scalef_round_sd): Ditto. + (_mm_maskz_scalef_round_ss): Ditto. + +2022-04-23 Jakub Jelinek <jakub@redhat.com> + + PR target/105338 + * config/i386/i386-expand.cc (ix86_expand_int_movcc): Handle + op0 == cst1 ? op0 : op3 like op0 == cst1 ? cst1 : op3 for the non-cmov + cases. + +2022-04-22 Segher Boessenkool <segher@kernel.crashing.org> + + PR target/105334 + * config/rs6000/rs6000.md (pack<mode> for FMOVE128): New expander. + (pack<mode> for FMOVE128): Rename and split the insn_and_split to... + (pack<mode>_hard for FMOVE128): ... this... + (pack<mode>_soft for FMOVE128): ... and this. + +2022-04-22 Paul A. Clarke <pc@us.ibm.com> + + * doc/extend.texi: Correct "This" to "These". + +2022-04-22 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/105333 + * rtlanal.cc (replace_rtx): Use simplify_subreg or + simplify_unary_operation if CONST_SCALAR_INT_P rather than just + CONST_INT_P. + +2022-04-21 Segher Boessenkool <segher@kernel.crashing.org> + + PR target/103197 + PR target/102146 + * config/rs6000/rs6000.md (zero_extendqi<mode>2 for EXTQI): Disparage + the "Z" alternatives in {l,st}{f,xs}iwzx. + (zero_extendhi<mode>2 for EXTHI): Ditto. + (zero_extendsi<mode>2 for EXTSI): Ditto. + (*movsi_internal1): Ditto. + (*mov<mode>_internal1 for QHI): Ditto. + (movsd_hardfloat): Ditto. + +2022-04-21 Martin Liska <mliska@suse.cz> + + * configure.ac: Enable compressed debug sections for mold + linker. + * configure: Regenerate. + +2022-04-21 Jakub Jelinek <jakub@redhat.com> + + PR debug/105203 + * emit-rtl.cc (emit_copy_of_insn_after): Don't call mark_jump_label + on DEBUG_INSNs. + +2022-04-20 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104912 + * tree-vect-loop-manip.cc (vect_loop_versioning): Split + the cost model check to a separate BB to make sure it is + checked first and not combined with other version checks. + +2022-04-20 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105312 + * gimple-isel.cc (gimple_expand_vec_cond_expr): Query both + VCOND and VCONDU for EQ and NE. + +2022-04-20 Jan Hubicka <hubicka@ucw.cz> + + PR ipa/103818 + * ipa-modref-tree.cc (modref_access_node::closer_pair_p): Use + poly_offset_int to avoid overflow. + (modref_access_node::update2): likewise. + +2022-04-20 Jakub Jelinek <jakub@redhat.com> + + PR ipa/105306 + * cgraph.cc (cgraph_node::create): Set node->semantic_interposition + to opt_for_fn (decl, flag_semantic_interposition). + * cgraphclones.cc (cgraph_node::create_clone): Copy over + semantic_interposition flag. + +2022-04-19 Sergei Trofimovich <siarheit@google.com> + + PR gcov-profile/105282 + * value-prof.cc (stream_out_histogram_value): Allow negative counts + on HIST_TYPE_INDIR_CALL. + +2022-04-19 Jakub Jelinek <jakub@redhat.com> + + PR target/105257 + * config/sparc/sparc.cc (epilogue_renumber): If ORIGINAL_REGNO, + use gen_raw_REG instead of gen_rtx_REG and copy over also + ORIGINAL_REGNO. Use return 0; instead of /* fallthrough */. + +2022-04-19 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104010 + PR tree-optimization/103941 + * tree-vect-slp.cc (vect_bb_slp_scalar_cost): When + we run into stmts in patterns continue walking those + for uses outside of the vectorized region instead of + marking the lane live. + +2022-04-18 Hans-Peter Nilsson <hp@axis.com> + + * doc/install.texi <CRIS>: Remove references to removed websites and + adjust for cris-*-elf being the only remaining toolchain. + +2022-04-18 Hans-Peter Nilsson <hp@axis.com> + + * doc/invoke.texi <CRIS>: Remove references to options for removed + subtarget cris-axis-linux-gnu and tweak wording accordingly. + +2022-04-16 Gerald Pfeifer <gerald@pfeifer.com> + + * doc/install.texi (Specific): Adjust mingw-w64 download link. + +2022-04-15 Hongyu Wang <hongyu.wang@intel.com> + + * config/i386/smmintrin.h: Correct target pragma from sse4.1 + and sse4.2 to crc32 for crc32 intrinsics. + +2022-04-14 Indu Bhagat <indu.bhagat@oracle.com> + + PR debug/105089 + * ctfc.cc (ctf_dvd_ignore_insert): New function. + (ctf_dvd_ignore_lookup): Likewise. + (ctf_add_variable): Keep track of non-defining decl DIEs. + (new_ctf_container): Initialize the new hash-table. + (ctfc_delete_container): Empty hash-table. + * ctfc.h (struct ctf_container): Add new hash-table. + (ctf_dvd_ignore_lookup): New declaration. + (ctf_add_variable): Add additional argument. + * ctfout.cc (ctf_dvd_preprocess_cb): Skip adding CTF variable + record for non-defining decl for which a defining decl exists + in the same TU. + (ctf_preprocess): Defer updating the number of global objts + until here. + (output_ctf_header): Use ctfc_vars_list_count as some CTF + variables may not make it to the final output. + (output_ctf_vars): Likewise. + * dwarf2ctf.cc (gen_ctf_variable): Skip generating CTF variable + if this is known to be a non-defining decl DIE. + +2022-04-14 Indu Bhagat <indu.bhagat@oracle.com> + + * ctfc.h (struct ctf_container): Introduce a new member. + * ctfout.cc (ctf_list_add_ctf_vars): Use it instead of static + variable. + +2022-04-14 Jakub Jelinek <jakub@redhat.com> + + PR target/105247 + * simplify-rtx.cc (simplify_const_binary_operation): For shifts + or rotates by VOIDmode constant integer shift count use word_mode + for the operand if int_mode is narrower than word. + +2022-04-14 Robin Dapp <rdapp@linux.ibm.com> + + * config/s390/s390.cc (s390_get_sched_attrmask): Add z16. + (s390_get_unit_mask): Likewise. + (s390_is_fpd): Likewise. + (s390_is_fxd): Likewise. + * config/s390/s390.h (s390_tune_attr): Set max tune level to z16. + * config/s390/s390.md (z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13,z14,z15): + Add z16. + (z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13,z14,z15,z16): + Likewise. + * config/s390/3931.md: New file. + +2022-04-13 Richard Sandiford <richard.sandiford@arm.com> + + PR tree-optimization/105254 + * config/aarch64/aarch64.cc + (aarch64_vector_costs::determine_suggested_unroll_factor): Take a + loop_vec_info as argument. Restrict the unroll factor to values + that divide the VF. + (aarch64_vector_costs::finish_cost): Update call accordingly. + +2022-04-13 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105263 + * tree-ssa-reassoc.cc (try_special_add_to_ops): Do not consume + negates in multiplication chains with DFP. + +2022-04-13 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/105253 + * tree.cc (tree_builtin_call_types_compatible_p): If PROP_gimple, + use useless_type_conversion_p checks instead of TYPE_MAIN_VARIANT + comparisons or tree_nop_conversion_p checks. + +2022-04-13 Hongyu Wang <hongyu.wang@intel.com> + + PR target/103069 + * config/i386/i386-expand.cc (ix86_expand_cmpxchg_loop): + Add missing set to target_val at pause label. + +2022-04-13 Jakub Jelinek <jakub@redhat.com> + + PR target/105234 + * attribs.cc (decl_attributes): Don't set + DECL_FUNCTION_SPECIFIC_TARGET if target_option_default_node is + NULL. + +2022-04-13 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105250 + * fold-const.cc (fold_convertible_p): Revert + r12-7979-geaaf77dd85c333, instead check for size equality + of the vector types involved. + +2022-04-13 Richard Biener <rguenther@suse.de> + + Revert: + 2022-04-13 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104912 + * tree-vect-loop-manip.cc (vect_loop_versioning): Split + the cost model check to a separate BB to make sure it is + checked first and not combined with other version checks. + +2022-04-13 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104912 + * tree-vect-loop-manip.cc (vect_loop_versioning): Split + the cost model check to a separate BB to make sure it is + checked first and not combined with other version checks. + +2022-04-13 Jakub Jelinek <jakub@redhat.com> + + * tree-scalar-evolution.cc (expression_expensive_p): Fix a comment typo. + +2022-04-12 Antoni Boucher <bouanto@zoho.com> + + PR jit/104072 + * reginfo.cc: New functions (clear_global_regs_cache, + reginfo_cc_finalize) to avoid an issue where compiling the same + code multiple times gives an error about assigning the same + register to 2 global variables. + * rtl.h: New function (reginfo_cc_finalize). + * toplev.cc: Call it. + +2022-04-12 Antoni Boucher <bouanto@zoho.com> + + PR jit/104071 + * toplev.cc: Call the new function tree_cc_finalize in + toplev::finalize. + * tree.cc: New functions (clear_nonstandard_integer_type_cache + and tree_cc_finalize) to clear the cache of non-standard integer + types to avoid having issues with some optimizations of + bitcast where the SSA_NAME will have a size of a cached + integer type that should have been invalidated, causing a + comparison of integer constant to fail. + * tree.h: New function (tree_cc_finalize). + +2022-04-12 Thomas Schwinge <thomas@codesourcery.com> + + PR target/97348 + * config/nvptx/nvptx.h (ASM_SPEC): Don't set. + * config/nvptx/nvptx.opt (misa): Adjust comment. + +2022-04-12 Thomas Schwinge <thomas@codesourcery.com> + + Revert: + 2022-03-03 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx.h (ASM_SPEC): Add %{misa=sm_30:--no-verify}. + +2022-04-12 Thomas Schwinge <thomas@codesourcery.com> + + Revert: + 2022-03-31 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx.h (ASM_SPEC): Use "-m sm_35" for -misa=sm_30. + +2022-04-12 Richard Biener <rguenther@suse.de> + + PR ipa/104303 + * tree-ssa-dce.cc (mark_stmt_if_obviously_necessary): Do not + include local escaped memory as obviously necessary stores. + +2022-04-12 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105235 + * tree-ssa-math-opts.cc (execute_cse_conv_1): Clean EH and + return whether the CFG changed. + (execute_cse_sincos_1): Adjust. + +2022-04-12 Przemyslaw Wirkus <Przemyslaw.Wirkus@arm.com> + + PR target/104144 + * config/arm/t-aprofile (MULTI_ARCH_OPTS_A): Remove Armv9-a options. + (MULTI_ARCH_DIRS_A): Remove Armv9-a diretories. + (MULTILIB_REQUIRED): Don't require Armv9-a libraries. + (MULTILIB_MATCHES): Treat Armv9-a as equivalent to Armv8-a. + (MULTILIB_REUSE): Remove remap rules for Armv9-a. + * config/arm/t-multilib (v9_a_nosimd_variants): Delete. + (MULTILIB_MATCHES): Remove mappings for v9_a_nosimd_variants. + +2022-04-12 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105232 + * tree.cc (component_ref_size): Bail out for too large + or non-constant sizes. + +2022-04-12 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105226 + * tree-vect-loop-manip.cc (vect_loop_versioning): Verify + we can split the exit of an outer loop we choose to version. + +2022-04-12 Jakub Jelinek <jakub@redhat.com> + + * config/i386/i386-expand.cc (ix86_emit_i387_sinh, ix86_emit_i387_cosh, + ix86_emit_i387_tanh, ix86_emit_i387_asinh, ix86_emit_i387_acosh, + ix86_emit_i387_atanh, ix86_emit_i387_log1p, ix86_emit_i387_round, + ix86_emit_swdivsf, ix86_emit_swsqrtsf, + ix86_expand_atomic_fetch_op_loop, ix86_expand_cmpxchg_loop): + Formatting fix. + * config/i386/i386.cc (warn_once_call_ms2sysv_xlogues): Likewise. + +2022-04-12 Jakub Jelinek <jakub@redhat.com> + + PR target/105214 + * config/i386/i386-expand.cc (ix86_emit_i387_log1p): Call + do_pending_stack_adjust. + +2022-04-12 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/105211 + * builtins.cc (expand_builtin_int_roundingfn_2): If mathfn_built_in_1 + fails for TREE_TYPE (arg), retry it with + TREE_VALUE (TYPE_ARG_TYPES (TREE_TYPE (fndecl))) and if even that + fails, emit call normally. + +2022-04-12 Andreas Krebbel <krebbel@linux.ibm.com> + + * common/config/s390/s390-common.cc: Rename PF_ARCH14 to PF_Z16. + * config.gcc: Add z16 as march/mtune switch. + * config/s390/driver-native.cc (s390_host_detect_local_cpu): + Recognize z16 with -march=native. + * config/s390/s390-opts.h (enum processor_type): Rename + PROCESSOR_ARCH14 to PROCESSOR_3931_Z16. + * config/s390/s390.cc (PROCESSOR_ARCH14): Rename to ... + (PROCESSOR_3931_Z16): ... throughout the file. + (s390_processor processor_table): Add z16 as cpu string. + * config/s390/s390.h (enum processor_flags): Rename PF_ARCH14 to + PF_Z16. + (TARGET_CPU_ARCH14): Rename to ... + (TARGET_CPU_Z16): ... this. + (TARGET_CPU_ARCH14_P): Rename to ... + (TARGET_CPU_Z16_P): ... this. + (TARGET_ARCH14): Rename to ... + (TARGET_Z16): ... this. + (TARGET_ARCH14_P): Rename to ... + (TARGET_Z16_P): ... this. + * config/s390/s390.md (cpu_facility): Rename arch14 to z16 and + check TARGET_Z16 instead of TARGET_ARCH14. + * config/s390/s390.opt: Add z16 to processor_type. + * doc/invoke.texi: Document z16 and arch14. + +2022-04-12 chenglulu <chenglulu@loongson.cn> + + * config/loongarch/loongarch.cc: Fix bug for + tmpdir-g++.dg-struct-layout-1/t033. + +2022-04-11 Peter Bergner <bergner@linux.ibm.com> + + PR target/104894 + * config/rs6000/rs6000.cc (rs6000_sibcall_aix): Handle pcrel sibcalls + to longcall functions. + +2022-04-11 Jason Merrill <jason@redhat.com> + + * ipa-free-lang-data.cc (free_lang_data_in_decl): Fix typos. + +2022-04-11 Segher Boessenkool <segher@kernel.crashing.org> + + PR target/105213 + PR target/103623 + * config/rs6000/rs6000.md (unpack<mode>_nodm): Add m,r,i alternative. + +2022-04-11 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/105218 + * tree-ssa-phiopt.cc (value_replacement): If middle_bb has + more than one predecessor or phi's bb more than 2 predecessors, + reset phi result uses instead of adding a debug temp. + +2022-04-11 Kito Cheng <kito.cheng@sifive.com> + + PR target/104853 + * config.gcc: Pass -misa-spec to arch-canonicalize and + multilib-generator. + * config/riscv/arch-canonicalize: Adding -misa-spec option. + (SUPPORTED_ISA_SPEC): New. + (arch_canonicalize): New argument `isa_spec`. + Handle multiple ISA spec versions. + * config/riscv/multilib-generator: Adding -misa-spec option. + +2022-04-11 Kito Cheng <kito.cheng@sifive.com> + + * config/riscv/arch-canonicalize: Add TODO item. + (IMPLIED_EXT): Sync. + (arch_canonicalize): Checking until no change. + +2022-04-11 Tamar Christina <tamar.christina@arm.com> + + PR target/105197 + * tree-vect-stmts.cc (vectorizable_condition): Prevent cond swap when + not masked. + +2022-04-11 Jason Merrill <jason@redhat.com> + + PR c++/100370 + * pointer-query.cc (compute_objsize_r) [POINTER_PLUS_EXPR]: Require + deref == -1. + +2022-04-11 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/104639 + * tree-ssa-phiopt.cc: Include tree-ssa-propagate.h. + (value_replacement): Optimize (x != cst1 ? x : cst2) != cst3 + into x != cst3. + +2022-04-11 Jeff Law <jeffreyalaw@gmail.com> + + * config/bfin/bfin.md (rol_one): Fix pattern to indicate the + sign bit of the source ends up in CC. + +2022-04-09 Jan Hubicka <hubicka@ucw.cz> + + PR ipa/103376 + * cgraphunit.cc (cgraph_node::analyze): update semantic_interposition + flag. + +2022-04-09 Jan Hubicka <hubicka@ucw.cz> + + * ipa-modref.cc (ipa_merge_modref_summary_after_inlining): Propagate + nondeterministic and side_effects flags. + +2022-04-08 Andre Vieira <andre.simoesdiasvieira@arm.com> + + PR target/105157 + * config.gcc: Shift ext_mask by TARGET_CPU_NBITS. + * config/aarch64/aarch64.h (TARGET_CPU_NBITS): New macro. + (TARGET_CPU_MASK): Likewise. + (TARGET_CPU_DEFAULT): Use TARGET_CPU_NBITS. + * config/aarch64/aarch64.cc (aarch64_get_tune_cpu): Use TARGET_CPU_MASK. + (aarch64_get_arch): Likewise. + (aarch64_override_options): Use TARGET_CPU_NBITS. + +2022-04-08 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105198 + * tree-predcom.cc (find_looparound_phi): Check whether + the found memory location of the entry value is clobbered + inbetween the value we want to use and loop entry. + +2022-04-08 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/105189 + * fold-const.cc (make_range_step): Fix up handling of + (unsigned) x +[low, -] ranges for signed x if low fits into + typeof (x). + +2022-04-08 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105175 + * tree-vect-stmts.cc (vectorizable_operation): Suppress + -Wvector-operation-performance if using emulated vectors. + * tree-vect-generic.cc (expand_vector_piecewise): Do not diagnose + -Wvector-operation-performance when suppressed. + (expand_vector_parallel): Likewise. + (expand_vector_comparison): Likewise. + (expand_vector_condition): Likewise. + (lower_vec_perm): Likewise. + (expand_vector_conversion): Likewise. + +2022-04-07 Tamar Christina <tamar.christina@arm.com> + + PR target/104409 + * config/aarch64/aarch64-builtins.cc (handle_arm_acle_h): New. + (aarch64_general_init_builtins): Move LS64 code. + * config/aarch64/aarch64-c.cc (aarch64_pragma_aarch64): Support + arm_acle.h + * config/aarch64/aarch64-protos.h (handle_arm_acle_h): New. + * config/aarch64/arm_acle.h: Add pragma GCC aarch64 "arm_acle.h". + +2022-04-07 Richard Biener <rguenther@suse.de> + Jan Hubicka <hubicka@ucw.cz> + + PR ipa/104303 + * tree-ssa-alias.h (ptr_deref_may_alias_global_p, + ref_may_alias_global_p, ref_may_alias_global_p, + stmt_may_clobber_global_p, pt_solution_includes_global): Add + bool parameters indicating whether escaped locals should be + considered global. + * tree-ssa-structalias.cc (pt_solution_includes_global): + When the new escaped_nonlocal_p flag is true also consider + pt->vars_contains_escaped. + * tree-ssa-alias.cc (ptr_deref_may_alias_global_p): + Pass down new escaped_nonlocal_p flag. + (ref_may_alias_global_p): Likewise. + (stmt_may_clobber_global_p): Likewise. + (ref_may_alias_global_p_1): Likewise. For decls also + query the escaped solution if true. + (ref_may_access_global_memory_p): Remove. + (modref_may_conflict): Use ref_may_alias_global_p with + escaped locals considered global. + (ref_maybe_used_by_stmt_p): Adjust. + * ipa-fnsummary.cc (points_to_local_or_readonly_memory_p): + Likewise. + * tree-ssa-dse.cc (dse_classify_store): Likewise. + * trans-mem.cc (thread_private_new_memory): Likewise, but + consider escaped locals global. + * tree-ssa-dce.cc (mark_stmt_if_obviously_necessary): Likewise. + +2022-04-07 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105185 + * tree-ssa-sccvn.cc (visit_reference_op_call): Simplify + modref query again. + +2022-04-07 Tamar Christina <tamar.christina@arm.com> + + PR target/104049 + * config/aarch64/aarch64-simd.md + (aarch64_reduc_plus_internal<mode>): Fix RTL and rename to... + (reduc_plus_scal_<mode>): ... This. + (reduc_plus_scal_v4sf): Moved. + (aarch64_reduc_plus_internalv2si): Fix RTL and rename to... + (reduc_plus_scal_v2si): ... This. + +2022-04-07 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/102586 + * langhooks.h (struct lang_hooks_for_types): Add classtype_as_base + langhook. + * langhooks-def.h (LANG_HOOKS_CLASSTYPE_AS_BASE): Define. + (LANG_HOOKS_FOR_TYPES_INITIALIZER): Add it. + * gimple-fold.cc (clear_padding_type): Use ftype instead of + TREE_TYPE (field) some more. For artificial FIELD_DECLs without + name try the lang_hooks.types.classtype_as_base langhook and + if it returns non-NULL, use that instead of ftype for recursive call. + +2022-04-07 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/105150 + * tree.cc (tree_builtin_call_types_compatible_p): New function. + (get_call_combined_fn): Use it. + +2022-04-07 Richard Biener <rguenther@suse.de> + + PR middle-end/105165 + * tree-complex.cc (expand_complex_asm): Sorry for asm goto + _Complex outputs. + +2022-04-07 liuhongt <hongtao.liu@intel.com> + + * config/i386/sse.md (<sse2_avx2>_andnot<mode>3_mask): + Removed. + (<sse>_andnot<mode>3<mask_name>): Disable V*HFmode patterns + for mask_applied. + (<code><mode>3<mask_name>): Ditto. + (*<code><mode>3<mask_name>): Ditto. + (VFB_128_256): Adjust condition of V8HF/V16HFmode according to + real instruction. + (VFB_512): Ditto. + (VFB): Ditto. + +2022-04-06 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/104985 + * combine.cc (struct undo): Add where.regno member. + (do_SUBST_MODE): Rename to ... + (subst_mode): ... this. Change first argument from rtx * into int, + operate on regno_reg_rtx[regno] and save regno into where.regno. + (SUBST_MODE): Remove. + (try_combine): Use subst_mode instead of SUBST_MODE, change first + argument from regno_reg_rtx[whatever] to whatever. For UNDO_MODE, use + regno_reg_rtx[undo->where.regno] instead of *undo->where.r. + (undo_to_marker): For UNDO_MODE, use regno_reg_rtx[undo->where.regno] + instead of *undo->where.r. + (simplify_set): Use subst_mode instead of SUBST_MODE, change first + argument from regno_reg_rtx[whatever] to whatever. + +2022-04-06 Jakub Jelinek <jakub@redhat.com> + + PR target/105069 + * config/sh/sh.opt (mdiv=): Add Save. + +2022-04-06 Martin Liska <mliska@suse.cz> + + PR driver/105096 + * common.opt: Document properly based on what it does. + * gcc.cc (display_help): Unify with what we have in common.opt. + * opts.cc (common_handle_option): Do not print undocumented + options. + +2022-04-06 Xi Ruoyao <xry111@mengyan1223.wang> + + * config/mips/mips.cc (mips_fpr_return_fields): Ignore + cxx17_empty_base_field_p fields and set an indicator. + (mips_return_in_msb): Adjust for mips_fpr_return_fields change. + (mips_function_value_1): Inform psABI change about C++17 empty + bases. + +2022-04-06 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/105150 + * gimple.cc (gimple_builtin_call_types_compatible_p): Use + builtin_decl_explicit here... + (gimple_call_builtin_p, gimple_call_combined_fn): ... rather than + here. + +2022-04-06 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105173 + * tree-ssa-reassoc.cc (find_insert_point): Get extra + insert_before output argument and compute it. + (insert_stmt_before_use): Adjust. + (rewrite_expr_tree): Likewise. + +2022-04-06 Richard Biener <rguenther@suse.de> + + PR ipa/105166 + * ipa-modref-tree.cc (modref_access_node::get_ao_ref ): Bail + out for non-pointer arguments. + +2022-04-06 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105163 + * tree-ssa-reassoc.cc (repropagate_negates): Avoid propagating + negated abnormals. + +2022-04-06 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/105150 + * gimple.cc (gimple_call_builtin_p, gimple_call_combined_fn): + For BUILT_IN_NORMAL calls, call gimple_builtin_call_types_compatible_p + preferrably on builtin_decl_explicit decl rather than fndecl. + * tree-ssa-strlen.cc (valid_builtin_call): Don't call + gimple_builtin_call_types_compatible_p here. + +2022-04-06 Richard Sandiford <richard.sandiford@arm.com> + + PR tree-optimization/103761 + * tree-vect-stmts.cc (check_load_store_for_partial_vectors): Replace + the ncopies parameter with an slp_node parameter. Calculate the + number of vectors based on it and vectype. Rename lambda to + group_memory_nvectors. + (vectorizable_store, vectorizable_load): Update calls accordingly. + +2022-04-06 Martin Liska <mliska@suse.cz> + + * doc/invoke.texi: Document it. + +2022-04-06 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105148 + * tree-ssa-loop-ivopts.cc (idx_record_use): Walk raw operands + 2 and 3 of ARRAY_REFs. + +2022-04-06 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/sse.md (ANDNOT_MODE): New mode iterator for TF and V1TI. + (*andnottf3): Replace with... + (*andnot<mode>3): New define_insn using ANDNOT_MODE. + +2022-04-06 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105142 + * gimple-fold.h (maybe_fold_and_comparisons): Add defaulted + basic-block parameter. + (maybe_fold_or_comparisons): Likewise. + * gimple-fold.cc (follow_outer_ssa_edges): New. + (maybe_fold_comparisons_from_match_pd): Use follow_outer_ssa_edges + when an outer condition basic-block is specified. + (and_comparisons_1, and_var_with_comparison, + and_var_with_comparison_1, or_comparisons_1, + or_var_with_comparison, or_var_with_comparison_1): Receive and pass + down the outer condition basic-block. + * tree-ssa-ifcombine.cc (ifcombine_ifandif): Pass down the + basic-block of the outer condition. + +2022-04-06 Kewen Lin <linkw@linux.ibm.com> + + PR target/105002 + * config/rs6000/rs6000.cc (rs6000_maybe_emit_maxc_minc): Support more + comparison codes UNLT/UNLE/UNGT/UNGE. + +2022-04-05 David Malcolm <dmalcolm@redhat.com> + + * doc/extend.texi (Common Function Attributes): Document that + 'access' does not imply 'nonnull'. + +2022-04-05 Uroš Bizjak <ubizjak@gmail.com> + + PR target/105139 + * config/i386/mmx.md (*movv2qi_internal): + Change insn mode of alternative 5 to HF for TARGET_AVX512FP16. + +2022-04-05 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64.md (aarch64_cpymemdi): Turn into a + define_expand and turn operands 0 and 1 from REGs to MEMs. + (*aarch64_cpymemdi): New pattern. + (aarch64_setmemdi): Turn into a define_expand and turn operand 0 + from a REG to a MEM. + (*aarch64_setmemdi): New pattern. + * config/aarch64/aarch64.cc (aarch64_expand_cpymem_mops): Use + copy_to_mode_reg on all three registers. Replace the original + MEM addresses rather than creating wild reads and writes. + (aarch64_expand_setmem_mops): Likewise for the size and for the + destination memory and address. + +2022-04-05 Richard Sandiford <richard.sandiford@arm.com> + + PR target/103147 + * config/aarch64/aarch64-protos.h (aarch64_simd_switcher): New class. + * config/aarch64/aarch64-sve-builtins.h (sve_switcher): Inherit + from aarch64_simd_switcher. + * config/aarch64/aarch64-builtins.cc (aarch64_simd_tuple_modes): + New variable. + (aarch64_lookup_simd_builtin_type): Use it instead of TYPE_MODE. + (register_tuple_type): Add more asserts. Expect the alignment + of the structure to be subject to flag_pack_struct and + maximum_field_alignment. Set aarch64_simd_tuple_modes. + (aarch64_simd_switcher::aarch64_simd_switcher): New function. + (aarch64_simd_switcher::~aarch64_simd_switcher): Likewise. + (handle_arm_neon_h): Hold an aarch64_simd_switcher throughout. + (aarch64_general_init_builtins): Hold an aarch64_simd_switcher + while calling aarch64_init_simd_builtins. + * config/aarch64/aarch64-sve-builtins.cc (sve_switcher::sve_switcher) + (sve_switcher::~sve_switcher): Remove code now performed by + aarch64_simd_switcher. + +2022-04-05 Richard Sandiford <richard.sandiford@arm.com> + + PR target/104897 + * config/aarch64/aarch64-sve-builtins.cc + (function_resolver::infer_vector_or_tuple_type): Use error_n + for "%d vectors" messages. + +2022-04-05 Chung-Lin Tang <cltang@codesourcery.com> + + * omp-low.cc (lower_omp_target): Use outer context looked-up 'var' as + argument to lang_hooks.decls.omp_array_data, instead of 'ovar' from + current clause. + +2022-04-05 Richard Biener <rguenther@suse.de> + + PR c/105151 + * passes.def (pass_walloca): Move early instance into + pass_build_ssa_passes to make SSA form available. + +2022-04-05 liuhongt <hongtao.liu@intel.com> + + PR target/101908 + * config/i386/i386.cc (ix86_split_stlf_stall_load): New + function + (ix86_reorg): Call ix86_split_stlf_stall_load. + * config/i386/i386.opt (-param=x86-stlf-window-ninsns=): New + param. + +2022-04-05 Alexandre Oliva <oliva@adacore.com> + + * targhooks.cc (default_zero_call_used_regs): Attempt to group + regs that the target refuses to use in their natural modes. + (zcur_select_mode_rtx): New. + * regs.h (struct target_regs): Add x_hard_regno_max_nregs. + (hard_regno_max_nregs): Define. + * reginfo.cc (init_reg_modes_target): Set hard_regno_max_nregs. + +2022-04-04 Alex Coplan <alex.coplan@arm.com> + + * doc/match-and-simplify.texi: Fix typos. + +2022-04-04 Jakub Jelinek <jakub@redhat.com> + + PR target/105144 + * config/aarch64/t-aarch64 (s-aarch64-tune-md): Do move-if-change + only if configured with --enable-maintainer-mode, otherwise compare + tmp-aarch64-tune.md with $(srcdir)/config/aarch64/aarch64-tune.md and + if they differ, emit a message and fail. + +2022-04-04 Jakub Jelinek <jakub@redhat.com> + + PR target/105144 + * config/aarch64/t-aarch64 (s-mddeps): Depend on s-aarch64-tune-md. + * config/aarch64/aarch64-tune.md: Regenerated. + +2022-04-04 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105132 + * tree-vect-stmts.cc (vectorizable_operation): Check that + the input vectors have the same number of elements. + +2022-04-04 Richard Biener <rguenther@suse.de> + + PR middle-end/105140 + * fold-const.cc (fold_convertible_p): Allow a TYPE_P arg. + +2022-04-03 Jeff Law <jeffreyalaw@gmail.com> + + PR target/104987 + * config/iq2000/iq2000.md (bbi): New attribute, default to no. + (delay slot descripts): Use different delay slot description when + the insn as the "bbi" attribute. + (bbi, bbin patterns): Set the bbi attribute to yes. + +2022-04-03 Jakub Jelinek <jakub@redhat.com> + + PR target/105123 + * config/i386/i386-expand.cc (ix86_expand_vector_init_general): Avoid + using word as target for expand_simple_binop when doing ASHIFT and + IOR. + +2022-04-02 Xi Ruoyao <xry111@mengyan1223.wang> + + * config/mips/mips.cc (mips_function_arg): Check if DECL_SIZE is + NULL before dereferencing it. + +2022-04-01 Qing Zhao <qing.zhao@oracle.com> + + * config/i386/i386.cc (zero_all_st_registers): Return the value of + num_of_st. + (ix86_zero_call_used_regs): Update zeroed_hardregs set according to + the return value of zero_all_st_registers. + * doc/tm.texi: Update the documentation of TARGET_ZERO_CALL_USED_REGS. + * function.cc (gen_call_used_regs_seq): Add an assertion. + * target.def: Update the documentation of TARGET_ZERO_CALL_USED_REGS. + +2022-04-01 Xi Ruoyao <xry111@mengyan1223.wang> + + PR target/102024 + * config/mips/mips.cc (mips_function_arg): Ignore zero-width + fields, and inform if it causes a psABI change. + +2022-04-01 Xi Ruoyao <xry111@mengyan1223.wang> + + PR target/102024 + * config/mips/mips.cc (mips_fpr_return_fields): Detect C++ + zero-width bit-fields and set up an indicator. + (mips_return_in_msb): Adapt for mips_fpr_return_fields change. + (mips_function_value_1): Diagnose when the presense of a C++ + zero-width bit-field changes function returning in GCC 12. + +2022-04-01 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/104645 + * tree-ssa-phiopt.cc (value_replacement): If assign has + CONVERT_EXPR_CODE_P rhs_code, treat it like a preparation + statement with constant evaluation. + +2022-04-01 YunQiang Su <yunqiang.su@cipunited.com> + + * config/mips/mips.cc (mips_expand_prologue): + IPL is 8bit for MCU ASE. + +2022-03-31 Bill Schmidt <wschmidt@linux.ibm.com> + + PR target/104004 + * config/rs6000/rs6000-builtins.def (MFFSL): Mark nosoft. + (MTFSB0): Likewise. + (MTFSB1): Likewise. + (SET_FPSCR_RN): Likewise. + (SET_FPSCR_DRN): Mark nosoft and no32bit. + +2022-03-31 Thomas Schwinge <thomas@codesourcery.com> + + * doc/options.texi (Option file format): Clarifications around + option definition records' help texts. + +2022-03-31 Thomas Schwinge <thomas@codesourcery.com> + + * optc-gen.awk <END>: Fix "Multiple different help strings" error + diagnostic. + +2022-03-31 Andre Vieira <andre.simoesdiasvieira@arm.com> + + * config/aarch64/aarch64.cc (aarch64_vector_costs): Define + determine_suggested_unroll_factor and m_has_avg. + (determine_suggested_unroll_factor): New function. + (aarch64_vector_costs::add_stmt_cost): Check for a qualifying pattern + to set m_nosve_pattern. + (aarch64_vector_costs::finish_costs): Use + determine_suggested_unroll_factor. + * config/aarch64/aarch64.opt (aarch64-vect-unroll-limit): New. + * doc/invoke.texi: (aarch64-vect-unroll-limit): Document new option. + +2022-03-31 Martin Jambor <mjambor@suse.cz> + + PR ipa/103083 + * ipa-prop.h (ipa_ancestor_jf_data): New flag keep_null; + (ipa_get_jf_ancestor_keep_null): New function. + * ipa-prop.cc (ipa_set_ancestor_jf): Initialize keep_null field of the + ancestor function. + (compute_complex_assign_jump_func): Pass false to keep_null + parameter of ipa_set_ancestor_jf. + (compute_complex_ancestor_jump_func): Pass true to keep_null + parameter of ipa_set_ancestor_jf. + (update_jump_functions_after_inlining): Carry over keep_null from the + original ancestor jump-function or merge them. + (ipa_write_jump_function): Stream keep_null flag. + (ipa_read_jump_function): Likewise. + (ipa_print_node_jump_functions_for_edge): Print the new flag. + * ipa-cp.cc (class ipcp_bits_lattice): Make various getters const. New + member function known_nonzero_p. + (ipcp_bits_lattice::known_nonzero_p): New. + (ipcp_bits_lattice::meet_with_1): New parameter drop_all_ones, + observe it. + (ipcp_bits_lattice::meet_with): Likewise. + (propagate_bits_across_jump_function): Simplify. Pass true in + drop_all_ones when it is necessary. + (propagate_aggs_across_jump_function): Take care of keep_null + flag. + (ipa_get_jf_ancestor_result): Propagate NULL accross keep_null + jump functions. + +2022-03-31 Martin Jambor <mjambor@suse.cz> + + PR ipa/102513 + * ipa-cp.cc (decide_whether_version_node): Skip scalar values + which do not fit the known value_range. + +2022-03-31 Martin Jambor <mjambor@suse.cz> + + PR ipa/103171 + * ipa-prop.cc (propagate_controlled_uses): Add a LOAD reference + always when an ADDR_EXPR constant is known to reach a load because + of inlining, not just when removing an ADDR reference. + +2022-03-31 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105109 + * tree-ssa.cc (execute_update_addresses_taken): Suppress + diagnostics on the load of the other complex component. + +2022-03-31 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx.h (ASM_SPEC): Use "-m sm_35" for -misa=sm_30. + +2022-03-31 Richard Biener <rguenther@suse.de> + + PR rtl-optimization/105091 + * gimple-expr.cc (mark_addressable): Handle TARGET_MEM_REF + bases. + +2022-03-31 Richard Biener <rguenther@suse.de> + + Revert: + 2021-09-13 Richard Earnshaw <rearnsha@arm.com> + + PR target/102125 + * gimple-fold.c (gimple_fold_builtin_memory_op): Allow folding + memcpy if the size is not more than MOVE_MAX * MOVE_RATIO. + +2022-03-31 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * gcov-io.cc (gcov_read_string): Reword documentation comment. + +2022-03-30 Bill Schmidt <wschmidt@linux.ibm.com> + + * config/rs6000/rs6000-builtins.def (NEG_V16QI): Move to [altivec] + stanza. + (NEG_V4SF): Likewise. + (NEG_V4SI): Likewise. + (NEG_V8HI): Likewise. + (NEG_V2DF): Move to [vsx] stanza. + (NEG_V2DI): Likewise. + +2022-03-30 Vladimir N. Makarov <vmakarov@redhat.com> + + PR middle-end/105032 + * lra-assigns.cc (find_reload_regno_insns): Modify loop condition. + +2022-03-30 Tom de Vries <tdevries@suse.de> + Tobias Burnus <tobias@codesourcery.com> + + * doc/invoke.texi (march): Document __PTX_SM__. + (mptx): Document __PTX_ISA_VERSION_MAJOR__ and + __PTX_ISA_VERSION_MINOR__. + +2022-03-30 Jakub Jelinek <jakub@redhat.com> + + PR sanitizer/105093 + * ubsan.cc (instrument_object_size): If t is equal to inner and + is a decl other than global var, punt. When emitting call to + UBSAN_OBJECT_SIZE ifn, make sure base is addressable. + +2022-03-30 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/105094 + * gimple-ssa-store-merging.cc (mem_valid_for_store_merging): Punt if + bitsize <= 0 rather than just == 0. + +2022-03-30 Tom de Vries <tdevries@suse.de> + + * doc/invoke.texi (misa, mptx): Update. + (march, march-map): Add. + +2022-03-30 Thomas Schwinge <thomas@codesourcery.com> + + * opt-functions.awk (n_args): New function. + (lang_enabled_by): Merge function into... + * optc-gen.awk <END>: ... sole user here. + Improve diagnostics. + +2022-03-29 Marek Polacek <polacek@redhat.com> + Jakub Jelinek <jakub@redhat.com> + + PR middle-end/103597 + * gimplify.cc (collect_fallthrough_labels): Don't push UNUSED_LABEL_Ps + into labels. Maybe set prev to the statement preceding UNUSED_LABEL_P. + (gimplify_cond_expr): Set UNUSED_LABEL_P. + * tree.h (UNUSED_LABEL_P): New. + +2022-03-29 Michael Meissner <meissner@linux.ibm.com> + + * config/rs6000/vsx.md (vsx_extract_<mode>): Allow destination to + be any VSX register. + +2022-03-29 Richard Earnshaw <rearnsha@arm.com> + + PR target/102024 + * config/aarch64/aarch64.cc (aapcs_vfp_sub_candidate): Handle + zero-sized bit-fields. Detect cases where a warning may be needed. + (aarch64_vfp_is_call_or_return_candidate): Emit a note if a + zero-sized bit-field has caused parameter passing to change. + +2022-03-29 Richard Earnshaw <rearnsha@arm.com> + + PR target/102024 + * config/arm/arm.cc (aapcs_vfp_sub_candidate): Handle zero-sized + bit-fields. Detect cases where a warning may be needed. + (aapcs_vfp_is_call_or_return_candidate): Emit a note if + a zero-sized bit-field has caused parameter passing to change. + +2022-03-29 Richard Earnshaw <rearnsha@arm.com> + + PR target/96882 + * config/arm/arm.cc (arm_get_pcs_model): Disable selection of + ARM_PCS_AAPCS_LOCAL. + +2022-03-29 Tom de Vries <tdevries@suse.de> + + PR target/104857 + * config/nvptx/nvptx-c.cc (nvptx_cpu_cpp_builtins): Emit + __PTX_ISA_VERSION_MAJOR__ and __PTX_ISA_VERSION_MINOR__. + * config/nvptx/nvptx.cc (ptx_version_to_number): New function. + * config/nvptx/nvptx-protos.h (ptx_version_to_number): Declare. + +2022-03-29 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx.opt (m64): Update help text to reflect that it + is ignored. + +2022-03-29 Tom de Vries <tdevries@suse.de> + + PR target/104714 + * config/nvptx/nvptx.opt (march-map=*): Add aliases. + +2022-03-29 Jan Hubicka <hubicka@ucw.cz> + + * config/i386/i386-builtins.cc (ix86_vectorize_builtin_gather): Test + TARGET_USE_GATHER_2PARTS and TARGET_USE_GATHER_4PARTS. + * config/i386/i386.h (TARGET_USE_GATHER_2PARTS): New macro. + (TARGET_USE_GATHER_4PARTS): New macro. + * config/i386/x86-tune.def (X86_TUNE_USE_GATHER_2PARTS): New tune + (X86_TUNE_USE_GATHER_4PARTS): New tune + +2022-03-29 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx.opt (march): Add alias of misa. + +2022-03-29 Chenghua Xu <xuchenghua@loongson.cn> + Lulu Cheng <chenglulu@loongson.cn> + + * doc/install.texi: Add LoongArch options section. + * doc/invoke.texi: Add LoongArch options section. + * doc/md.texi: Add LoongArch options section. + +2022-03-29 Chenghua Xu <xuchenghua@loongson.cn> + Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/loongarch-c.cc + +2022-03-29 Chenghua Xu <xuchenghua@loongson.cn> + Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/larchintrin.h: New file. + * config/loongarch/loongarch-builtins.cc: New file. + +2022-03-29 Chenghua Xu <xuchenghua@loongson.cn> + Lulu Cheng <chenglulu@loongson.cn> + + * config/host-linux.cc: Add LoongArch support. + * config/loongarch/loongarch-protos.h: New file. + * config/loongarch/loongarch-tune.h: Likewise. + * config/loongarch/loongarch.cc: Likewise. + * config/loongarch/loongarch.h: Likewise. + +2022-03-29 Chenghua Xu <xuchenghua@loongson.cn> + Lulu Cheng <chenglulu@loongson.cn> + + * config/loongarch/constraints.md: New file. + * config/loongarch/generic.md: New file. + * config/loongarch/la464.md: New file. + * config/loongarch/loongarch-ftypes.def: New file. + * config/loongarch/loongarch-modes.def: New file. + * config/loongarch/loongarch.md: New file. + * config/loongarch/predicates.md: New file. + * config/loongarch/sync.md: New file. + +2022-03-29 Chenghua Xu <xuchenghua@loongson.cn> + Lulu Cheng <chenglulu@loongson.cn> + + * configure: Regenerate file. + +2022-03-29 Chenghua Xu <xuchenghua@loongson.cn> + Lulu Cheng <chenglulu@loongson.cn> + + * common/config/loongarch/loongarch-common.cc: New file. + * config/loongarch/genopts/genstr.sh: New file. + * config/loongarch/genopts/loongarch-strings: New file. + * config/loongarch/genopts/loongarch.opt.in: New file. + * config/loongarch/loongarch-str.h: New file. + * config/loongarch/gnu-user.h: New file. + * config/loongarch/linux.h: New file. + * config/loongarch/loongarch-cpu.cc: New file. + * config/loongarch/loongarch-cpu.h: New file. + * config/loongarch/loongarch-def.c: New file. + * config/loongarch/loongarch-def.h: New file. + * config/loongarch/loongarch-driver.cc: New file. + * config/loongarch/loongarch-driver.h: New file. + * config/loongarch/loongarch-opts.cc: New file. + * config/loongarch/loongarch-opts.h: New file. + * config/loongarch/loongarch.opt: New file. + * config/loongarch/t-linux: New file. + * config/loongarch/t-loongarch: New file. + * config.gcc: Add LoongArch support. + * configure.ac: Add LoongArch support. + +2022-03-29 Thomas Schwinge <thomas@codesourcery.com> + + * opt-functions.awk (lang_enabled_by): Fix 'enabledby_negargs' + typo. + +2022-03-29 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105080 + * tree-ssa-strlen.cc (printf_strlen_execute): Always init + loops and SCEV. + +2022-03-28 Indu Bhagat <indu.bhagat@oracle.com> + + * ctfout.cc (ctf_preprocess): Use ctfc_get_num_ctf_vars instead. + (output_ctf_vars): Likewise. + +2022-03-28 Jason Merrill <jason@redhat.com> + + PR c++/59426 + * doc/extend.texi: Refer to __is_trivial instead of __is_pod. + +2022-03-28 H.J. Lu <hjl.tools@gmail.com> + + PR target/105068 + * config/i386/sse.md (*ssse3_pshufbv8qi3): Also replace "Yv" with + "Yw" in clobber. + +2022-03-28 Tom de Vries <tdevries@suse.de> + + PR target/104818 + * config/nvptx/gen-opt.sh (ptx_isa): Improve help text. + * config/nvptx/nvptx-gen.opt: Regenerate. + * config/nvptx/nvptx.opt (misa, mptx, ptx_version): Improve help text. + * config/nvptx/t-nvptx (s-nvptx-gen-opt): Add missing dependency on + gen-opt.sh. + +2022-03-28 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/104308 + * gimple-fold.cc (gimple_fold_builtin_memory_op): When optimizing + to loads then stores, set the location of the new load stmt. + +2022-03-28 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105070 + * tree-switch-conversion.h + (bit_test_cluster::hoist_edge_and_branch_if_true): Add location + argument. + * tree-switch-conversion.cc + (bit_test_cluster::hoist_edge_and_branch_if_true): Annotate + cond with location. + (bit_test_cluster::emit): Annotate all generated expressions + with location. + +2022-03-28 Andre Vieira <andre.simoesdiasvieira@arm.com> + + * config/aarch64/aarch64-cores.def: Update Neoverse N2 core entry. + +2022-03-28 liuhongt <hongtao.liu@intel.com> + + PR target/105066 + * config/i386/sse.md (vec_set<mode>_0): Change attr "isa" of + alternative 4 from sse4_noavx to noavx. + +2022-03-28 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/105056 + * tree-predcom.cc (component::component): Initialize also comp_step. + +2022-03-27 H.J. Lu <hjl.tools@gmail.com> + + PR target/105068 + * config/i386/sse.md (*ssse3_pshufbv8qi3): Replace "Yv" with + "Yw". + +2022-03-26 Roger Sayle <roger@nextmovesoftware.com> + + PR middle-end/104885 + * calls.cc (mark_stack_region_used): Check that the region + is within the allocated size of stack_usage_map. + +2022-03-26 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/103775 + * recog.cc (check_invalid_inc_dec): New function. + (insn_invalid_p): Return 1 if REG_INC operand overlaps + any stored REGs. + +2022-03-26 H.J. Lu <hjl.tools@gmail.com> + + PR target/105058 + * config/i386/sse.md (loadiwkey): Replace "v" with "x". + (aes<aesklvariant>u8): Likewise. + +2022-03-26 H.J. Lu <hjl.tools@gmail.com> + + PR target/105052 + * config/i386/sse.md (ssse3_ph<plusminus_mnemonic>wv4hi3): + Replace "Yv" with "x". + (ssse3_ph<plusminus_mnemonic>dv2si3): Likewise. + (ssse3_psign<mode>3): Likewise. + +2022-03-26 Hans-Peter Nilsson <hp@axis.com> + + * reload.cc (find_reloads): Align comment with code where + considering the intersection of register classes then tweaking the + regclass for the current alternative or rejecting it. + +2022-03-25 Christophe Lyon <christohe.lyon@arm.com> + + PR target/104882 + Revert + 2021-06-11 Christophe Lyon <christophe.lyon@linaro.org> + + * config/arm/mve.md (mve_vec_unpack<US>_lo_<mode>): Delete. + (mve_vec_unpack<US>_hi_<mode>): Delete. + (@mve_vec_pack_trunc_lo_<mode>): Delete. + (mve_vmovntq_<supf><mode>): Remove '@' prefix. + * config/arm/neon.md (vec_unpack<US>_hi_<mode>): Move back + from vec-common.md. + (vec_unpack<US>_lo_<mode>): Likewise. + (vec_pack_trunc_<mode>): Rename from + neon_quad_vec_pack_trunc_<mode>. + * config/arm/vec-common.md (vec_unpack<US>_hi_<mode>): Delete. + (vec_unpack<US>_lo_<mode>): Delete. + (vec_pack_trunc_<mode>): Delete. + +2022-03-25 Vladimir N. Makarov <vmakarov@redhat.com> + + PR middle-end/104971 + * lra-lives.cc (process_bb_lives): Check hard_regs_live for hard + regs to clear remove_p flag. + +2022-03-25 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105053 + * tree-vect-loop.cc (vect_create_epilog_for_reduction): Pick + the correct live-out stmt for a reduction chain. + +2022-03-25 Richard Biener <rguenther@suse.de> + + PR middle-end/105049 + * tree.cc (uniform_vector_p): Recurse for VECTOR_CST or + CONSTRUCTOR first elements. + +2022-03-25 Tobias Burnus <tobias@codesourcery.com> + + PR analyzer/103533 + * doc/invoke.texi (Static Analyzer Options): Move + @ignore block after @gccoptlist's '}' for 'make pdf'. + +2022-03-25 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/104954 + * doc/invoke.texi (Static Analyzer Options): Add + -fdump-analyzer-untracked. + +2022-03-25 Avinash Sonawane <rootkea@gmail.com> + + PR analyzer/103533 + * doc/invoke.texi: Document that enabling taint analyzer + checker disables some warnings from `-fanalyzer`. + +2022-03-24 Alexandre Oliva <oliva@adacore.com> + + PR debug/104564 + * gimple-harden-conditionals.cc (detach_value): Keep temps + anonymous. + +2022-03-24 Alexandre Oliva <oliva@adacore.com> + + PR middle-end/104975 + * gimple-harden-conditionals.cc + (pass_harden_compares::execute): Force split in case of + multiple edges. + +2022-03-24 Jakub Jelinek <jakub@redhat.com> + + PR c++/105035 + * fold-const.cc (operand_equal_p) <case COMPONENT_REF>: If either + field0 or field1 is not a FIELD_DECL, return false. + +2022-03-24 Richard Biener <rguenther@suse.de> + + * tree-predcom.cc (chain::chain): Add CTOR. + (component::component): Likewise. + (pcom_worker::release_chain): Use delete. + (release_components): Likewise. + (pcom_worker::filter_suitable_components): Likewise. + (pcom_worker::split_data_refs_to_components): Use new. + (make_invariant_chain): Likewise. + (make_rooted_chain): Likewise. + (pcom_worker::combine_chains): Likewise. + * tree-vect-loop.cc (vect_create_epilog_for_reduction): + Make sure to release previously constructed scalar_results. + * tree-vect-stmts.cc (vectorizable_load): Use auto_vec + for vec_offsets. + * vr-values.cc (simplify_using_ranges::~simplify_using_ranges): + Release m_flag_set_edges. + +2022-03-24 Siddhesh Poyarekar <siddhesh@gotplt.org> + + PR tree-optimization/104970 + * tree-object-size.cc (parm_object_size): Restrict size + computation scenarios to explicit access attributes. + +2022-03-24 Kewen Lin <linkw@linux.ibm.com> + + PR target/104967 + * config/rs6000/rs6000-c.cc (find_instance): Skip instances with null + function types. + +2022-03-23 Richard Biener <rguenther@suse.de> + + PR target/102125 + * gimple-fold.cc (gimple_fold_builtin_memory_op): Allow the + use of movmisalign when either the source or destination + decl is properly aligned. + +2022-03-23 Richard Biener <rguenther@suse.de> + + PR rtl-optimization/105028 + * ira-color.cc (form_threads_from_copies): Remove unnecessary + copying of the sorted_copies tail. + +2022-03-23 Martin Liska <mliska@suse.cz> + + * config/rs6000/rs6000-c.cc (altivec_resolve_overloaded_builtin): + Use %qs in format. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): + Reword the error message. + +2022-03-23 liuhongt <hongtao.liu@intel.com> + + PR target/104976 + * config/i386/sse.md (ssePSmodelower): New. + (*avx_cmp<mode>3_ltint_not): Force_reg operand before + lowpart_subreg to avoid NULL_RTX. + (<avx512>_fmaddc_<mode>_mask1<round_expand_name>, + <avx512>_fcmaddc_<mode>_mask1<round_expand_name>, + fma_<mode>_fmaddc_bcst, fma_<mode>_fcmaddc_bcst, + <avx512>_<complexopname>_<mode>_mask<round_name>, + avx512fp16_fcmaddcsh_v8hf_mask1<round_expand_name>, + avx512fp16_fcmaddcsh_v8hf_mask3<round_expand_name>, + avx512fp16_fmaddcsh_v8hf_mask3<round_expand_name>, + avx512fp16_fmaddcsh_v8hf_mask3<round_expand_name>, + float<floatunssuffix><mode>v4hf2, + float<floatunssuffix>v2div2hf2, + fix<fixunssuffix>_truncv4hf<mode>2, + fix<fixunssuffix>_truncv2hfv2di2, extendv4hf<mode>2, + extendv2hfv2df2, + trunc<mode>v4hf2,truncv2dfv2hf2, + *avx512bw_permvar_truncv16siv16hi_1, + *avx512bw_permvar_truncv16siv16hi_1_hf, + *avx512f_permvar_truncv8siv8hi_1, + *avx512f_permvar_truncv8siv8hi_1_hf, + *avx512f_vpermvar_truncv8div8si_1, + *avx512f_permvar_truncv32hiv32qi_1, + *avx512f_permvar_truncv16hiv16qi_1, + *avx512f_permvar_truncv4div4si_1, + *avx512f_pshufb_truncv8hiv8qi_1, + *avx512f_pshufb_truncv4siv4hi_1, + *avx512f_pshufd_truncv2div2si_1, + sdot_prod<mode>, avx2_pblend<ssemodesuffix>_1, + ashrv2di3,ashrv2di3,usdot_prod<mode>): Ditto. + +2022-03-22 Tom de Vries <tdevries@suse.de> + + PR target/104925 + * config/nvptx/nvptx.md (define_insn "nvptx_uniform_warp_check"): + Use % as register prefix. + +2022-03-22 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx.cc (nvptx_scalar_mode_supported_p) + (nvptx_libgcc_floating_mode_supported_p): Only enable HFmode for + mexperimental. + +2022-03-22 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx.opt (mexperimental): New option. + +2022-03-22 Tom de Vries <tdevries@suse.de> + + PR target/104957 + * config/nvptx/nvptx-protos.h (nvptx_asm_output_def_from_decls): Declare. + * config/nvptx/nvptx.cc (write_fn_proto_1): Don't add function marker + for alias. + (SET_ASM_OP, NVPTX_ASM_OUTPUT_DEF): New macro def. + (nvptx_asm_output_def_from_decls): New function. + * config/nvptx/nvptx.h (ASM_OUTPUT_DEF): New macro def, define to + gcc_unreachable (). + (ASM_OUTPUT_DEF_FROM_DECLS): New macro def, define to + nvptx_asm_output_def_from_decls. + * config/nvptx/nvptx.opt (malias): New opt. + +2022-03-22 Tom de Vries <tdevries@suse.de> + + PR target/104916 + PR target/104783 + * config/nvptx/nvptx.md (define_expand "omp_simt_exit"): Emit warp + sync (or uniform warp check for mptx < 6.0). + +2022-03-22 Richard Biener <rguenther@suse.de> + + PR tree-optimization/105012 + * tree-if-conv.cc (ifcvt_local_dce): Only call + dse_classify_store when we have a VDEF. + +2022-03-22 Martin Liska <mliska@suse.cz> + + PR target/104902 + * config/nvptx/nvptx.cc (handle_ptx_version_option): + Fix option wrapping in an error message. + +2022-03-22 Martin Liska <mliska@suse.cz> + + PR target/104903 + * config/rs6000/rs6000-c.cc (altivec_resolve_overloaded_builtin): + Wrap const keyword. + +2022-03-22 Martin Liska <mliska@suse.cz> + + * config/v850/v850-c.cc (pop_data_area): Fix typo in pragma + name. + +2022-03-22 Martin Liska <mliska@suse.cz> + + PR target/104898 + * config/rs6000/rs6000.cc (rs6000_option_override_internal): + Use %qs instead of (%qs). + +2022-03-22 Martin Liska <mliska@suse.cz> + + PR target/104898 + * config/i386/i386-options.cc (ix86_option_override_internal): + Use '%qs' instead of '(%qs)'. + +2022-03-22 Martin Liska <mliska@suse.cz> + + PR target/104898 + * config/aarch64/aarch64.cc (aarch64_handle_attr_arch): + Use 'qs' and remove usage '(%qs)'. + (aarch64_handle_attr_cpu): Likewise. + (aarch64_handle_attr_tune): Likewise. + (aarch64_handle_attr_isa_flags): Likewise. + +2022-03-22 Tamar Christina <tamar.christina@arm.com> + Andre Vieira <andre.simoesdiasvieira@arm.com> + + * config/aarch64/aarch64.cc (neoversev1_regmove_cost): New tuning + struct. + (neoversev1_tunings): Use neoversev1_regmove_cost and update store_int + cost. + (neoverse512tvb_tunings): Likewise. + +2022-03-22 Tamar Christina <tamar.christina@arm.com> + Andre Vieira <andre.simoesdiasvieira@arm.com> + + * config/aarch64/aarch64.cc (demeter_addrcost_table, + demeter_regmove_cost, demeter_advsimd_vector_cost, + demeter_sve_vector_cost, demeter_scalar_issue_info, + demeter_advsimd_issue_info, demeter_sve_issue_info, + demeter_vec_issue_info, demeter_vector_cost, + demeter_tunings): New tuning structs. + (aarch64_ve_op_count::rename_cycles_per_iter): Enable for demeter + tuning. + * config/aarch64/aarch64-cores.def: Add entry for demeter. + * config/aarch64/aarch64-tune.md (tune): Add demeter to list. + +2022-03-22 Tamar Christina <tamar.christina@arm.com> + Andre Vieira <andre.simoesdiasvieira@arm.com> + + * config/aarch64/aarch64-protos.h (struct cpu_memmov_cost): New struct. + (struct tune_params): Change type of memmov_cost to use cpu_memmov_cost. + * config/aarch64/aarch64.cc (aarch64_memory_move_cost): Update all + tunings to use cpu_memmov_cost struct. + +2022-03-22 Tamar Christina <tamar.christina@arm.com> + Andre Vieira <andre.simoesdiasvieira@arm.com> + + * config/aarch64/aarch64.cc (neoversen2_addrcost_table, + neoversen2_regmove_cost, neoversen2_advsimd_vector_cost, + neoversen2_sve_vector_cost, neoversen2_scalar_issue_info, + neoversen2_advsimd_issue_info, neoversen2_sve_issue_info, + neoversen2_vec_issue_info, neoversen2_tunings): New structs. + (neoversen2_tunings): Use new structs and update tuning flags. + (aarch64_vec_op_count::rename_cycles_per_iter): Enable for neoversen2 + tuning. + +2022-03-22 Andre Vieira <andre.simoesdiasvieira@arm.com> + + * config/aarch64/aarch64.h (AARCH64_FL_FOR_ARCH9): Add FP16 feature + bit. + +2022-03-22 liuhongt <hongtao.liu@intel.com> + + PR target/104982 + * config/i386/i386.md (*jcc_bt<mode>_mask): Extend the + following splitter to reversed condition. + +2022-03-22 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/104989 + * calls.cc (expand_call): Don't set ECF_NORETURN in flags after + sorry for passing too large argument, instead set sibcall_failure + for pass == 0, or a new normal_failure flag otherwise. If + normal_failure is set, don't assert all stack has been deallocated + at the end and throw away the whole insn sequence. + +2022-03-22 Qian Jianhua <qianjh@cn.fujitsu.com> + + * print-tree.cc: Change array length + +2022-03-22 Hongyu Wang <hongyu.wang@intel.com> + + PR target/104978 + * config/i386/sse.md + (avx512fp16_fmaddcsh_v8hf_mask1<round_expand_name): + Use avx512f_movsf_mask instead of vmovaps or vblend, and + force_reg before lowpart_subreg. + (avx512fp16_fcmaddcsh_v8hf_mask1<round_expand_name): Likewise. + +2022-03-21 H.J. Lu <hjl.tools@gmail.com> + + PR target/105000 + * common/config/i386/i386-common.cc + (OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET): Replace + OPTION_MASK_ISA2_AVX512F_UNSET with OPTION_MASK_ISA2_SSE_UNSET. + +2022-03-21 H.J. Lu <hjl.tools@gmail.com> + + PR target/104998 + * common/config/i386/cpuinfo.h (get_available_features): Pass + 0x19 to __cpuid for bit_AESKLE. Enable FEATURE_AESKLE only if + bit_AESKLE is set. + +2022-03-21 Richard Sandiford <richard.sandiford@arm.com> + + PR middle-end/104869 + * rtl-ssa/accesses.h (clobber_group::prev_clobber): Declare. + (clobber_group::next_clobber): Likewise. + (def_lookup::prev_def): Rename to... + (def_lookup::last_def_of_prev_group): ...this. + (def_lookup::next_def): Rename to... + (def_lookup::first_def_of_next_group): ...this. + (def_lookup::matching_or_prev_def): Rename to... + (def_lookup::matching_set_or_last_def_of_prev_group): ...this. + (def_lookup::matching_or_next_def): Rename to... + (def_lookup::matching_set_or_first_def_of_next_group): ...this. + (def_lookup::prev_def): New function, taking the lookup insn as + argument. + (def_lookup::next_def): Likewise. + * rtl-ssa/member-fns.inl (def_lookup::prev_def): Rename to... + (def_lookup::last_def_of_prev_group): ...this. + (def_lookup::next_def): Rename to... + (def_lookup::first_def_of_next_group): ...this. + (def_lookup::matching_or_prev_def): Rename to... + (def_lookup::matching_set_or_last_def_of_prev_group): ...this. + (def_lookup::matching_or_next_def): Rename to... + (def_lookup::matching_set_or_first_def_of_next_group): ...this. + * rtl-ssa/movement.h (restrict_movement_for_dead_range): Update after + above renaming. + * rtl-ssa/accesses.cc (clobber_group::prev_clobber): New function. + (clobber_group::next_clobber): Likewise. + (def_lookup::prev_def): Likewise. + (def_lookup::next_def): Likewise. + (function_info::make_use_available): Pass the lookup insn to + def_lookup::prev_def and def_lookup::next_def. + +2022-03-21 Martin Liska <mliska@suse.cz> + + * doc/invoke.texi: Document min-pagesize parameter. + +2022-03-21 Richard Biener <rguenther@suse.de> + + * tree-ssa-loop-niter.cc (estimate_numbers_of_iterations): Dump + we are estimating niter of loop. + +2022-03-21 Kito Cheng <kito.cheng@sifive.com> + + * common/config/riscv/riscv-common.cc (riscv_ext_flag_table): + Update flag name and mask name. + * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Define + misc macro for vector extensions. + * config/riscv/riscv-opts.h (MASK_VECTOR_EEW_32): Rename to ... + (MASK_VECTOR_ELEN_32): ... this. + (MASK_VECTOR_EEW_64): Rename to ... + (MASK_VECTOR_ELEN_64): ... this. + (MASK_VECTOR_EEW_FP_32): Rename to ... + (MASK_VECTOR_ELEN_FP_32): ... this. + (MASK_VECTOR_EEW_FP_64): Rename to ... + (MASK_VECTOR_ELEN_FP_64): ... this. + (TARGET_VECTOR_ELEN_32): New. + (TARGET_VECTOR_ELEN_64): Ditto. + (TARGET_VECTOR_ELEN_FP_32): Ditto. + (TARGET_VECTOR_ELEN_FP_64): Ditto. + (TARGET_MIN_VLEN): Ditto. + * config/riscv/riscv.opt (riscv_vector_eew_flags): Rename to ... + (riscv_vector_elen_flags): ... this. + +2022-03-21 Hongyu Wang <hongyu.wang@intel.com> + + PR target/104977 + * config/i386/sse.md + (avx512fp16_fma<complexopname>sh_v8hf<mask_scalarcz_name><round_scalarcz_name>): + Correct round operand for intel dialect. + +2022-03-19 Arthur Cohen <arthur.cohen@embecosm.com> + + * diagnostic.cc (diagnostic_cc_tests): Rename to... + (c_diagnostic_cc_tests): ...this. + * opt-problem.cc (opt_problem_cc_tests): Rename to... + (c_opt_problem_cc_tests): ...this. + * selftest-run-tests.cc (selftest::run_tests): No longer run + opt_problem_cc_tests or diagnostic_cc_tests. + * selftest.h (diagnostic_cc_tests): Remove declaration. + (opt_problem_cc_tests): Likewise. + +2022-03-19 Marc Nieper-Wißkirchen <marc@nieper-wisskirchen.de> + + PR jit/63854 + * hash-traits.h (struct typed_const_free_remove): New. + (struct free_string_hash): New. + * pass_manager.h: Use free_string_hash. + * passes.cc (pass_manager::register_pass_name): Use free_string_hash. + (pass_manager::~pass_manager): Delete allocated m_name_to_pass_map. + +2022-03-19 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/104971 + * config/i386/i386-expand.cc + (ix86_expand_builtin) <case IX86_BUILTIN_READ_FLAGS>: If ignore, + don't push/pop anything and just return const0_rtx. + +2022-03-18 Vladimir N. Makarov <vmakarov@redhat.com> + + PR rtl-optimization/104961 + * lra-assigns.cc (find_reload_regno_insns): Process reload pseudo clobber. + +2022-03-18 Jason Merrill <jason@redhat.com> + + * tree.h (IDENTIFIER_LENGTH): Add comment. + +2022-03-18 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/99578 + PR middle-end/100680 + PR tree-optimization/100834 + * params.opt (--param=min-pagesize=): New parameter. + * pointer-query.cc + (compute_objsize_r) <case ARRAY_REF>: Formatting fix. + (compute_objsize_r) <case INTEGER_CST>: Use maximum object size instead + of zero for pointer constants equal or larger than min-pagesize. + +2022-03-18 Tom de Vries <tdevries@suse.de> + + * gimplify.cc (gimplify_omp_for): Set location using 'input_location'. + Set gfor location only when dealing with a OMP_TASKLOOP. + +2022-03-18 Tom de Vries <tdevries@suse.de> + + * gimplify.cc (gimplify_omp_for): Set taskloop location. + +2022-03-18 Tom de Vries <tdevries@suse.de> + + PR target/104952 + * omp-low.cc (lower_rec_input_clauses): Make sure GOMP_SIMT_XCHG_BFLY + is executed unconditionally. + +2022-03-18 liuhongt <hongtao.liu@intel.com> + + PR target/104974 + * config/i386/i386.md (*movhi_internal): Set attr type from HI + to HF for alternative 12 under TARGET_AVX512FP16. + +2022-03-18 Cui,Lili <lili.cui@intel.com> + + PR target/104963 + * config/i386/i386.h (PTA_SAPPHIRERAPIDS): change it to base on ICX. + * doc/invoke.texi: Update documents for Intel sapphirerapids. + +2022-03-17 Roger Sayle <roger@nextmovesoftware.com> + + PR target/86722 + PR tree-optimization/90356 + * config/i386/i386.md (*movtf_internal): Don't guard + standard_sse_constant_p clause by optimize_function_for_size_p. + (*movdf_internal): Likewise. + (*movsf_internal): Likewise. + +2022-03-17 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/102943 + * gimple-range-cache.cc (ranger_cache::range_from_dom): Find range via + dominators and apply intermediary outgoing edge ranges. + +2022-03-17 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104960 + * passes.def: Add pass parameter to pass_sink_code, mark + last one to unsplit edges. + * tree-ssa-sink.cc (pass_sink_code::set_pass_param): New. + (pass_sink_code::execute): Always execute TODO_cleanup_cfg + when we need to unsplit edges. + +2022-03-17 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/103984 + * gimplify.cc (gimplify_target_expr): Gimplify type sizes and + TARGET_EXPR_INITIAL into a temporary sequence, then push clobbers + and asan unpoisioning, then append the temporary sequence and + finally the TARGET_EXPR_CLEANUP clobbers. + +2022-03-16 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/sse.md: Delete corrupt character/typo. + +2022-03-16 Roger Sayle <roger@nextmovesoftware.com> + + PR target/94680 + * config/i386/sse.md (sse2_movq128): New define_expand to + preserve previous named instruction. + (*sse2_movq128_<mode>): Renamed from sse2_movq128, and + generalized to VI8F_128 (both V2DI and V2DF). + +2022-03-16 Siddhesh Poyarekar <siddhesh@gotplt.org> + + PR tree-optimization/104941 + * tree-object-size.cc (size_for_offset): Make useless conversion + check lighter and assign result of fold_convert to OFFSET. + +2022-03-16 H.J. Lu <hjl.tools@gmail.com> + + PR target/104890 + * config/i386/x86gprintrin.h: Also check _SOFT_FLOAT before + pushing target("general-regs-only"). + +2022-03-16 Kito Cheng <kito.cheng@sifive.com> + + * common/config/riscv/riscv-common.cc (riscv_ext_version_table): + Add version info for zk, zks and zkn. + +2022-03-16 LiaoShihua <shihua@iscas.ac.cn> + + * common/config/riscv/riscv-common.cc + (riscv_combine_info): New. + (riscv_subset_list::handle_combine_ext): Combine back into zk to + maintain the canonical order in isa strings. + (riscv_subset_list::parse): Ditto. + * config/riscv/riscv-subset.h (handle_combine_ext): New. + +2022-03-16 Richard Biener <rguenther@suse.de> + + PR tree-optimization/102008 + * passes.def: Move the added code sinking pass before the + preceeding phiopt pass. + +2022-03-16 Patrick Palka <ppalka@redhat.com> + + PR c++/96780 + * doc/invoke.texi (C++ Dialect Options): Document + -ffold-simple-inlines. + +2022-03-16 Siddhesh Poyarekar <siddhesh@gotplt.org> + + PR tree-optimization/104942 + * tree-object-size.cc (alloc_object_size): Remove STRIP_NOPS. + +2022-03-16 Jakub Jelinek <jakub@redhat.com> + + PR target/104910 + * config/aarch64/aarch64.cc (aarch64_load_symref_appropriately): Copy + imm rtx. + +2022-03-16 Roger Sayle <roger@nextmovesoftware.com> + Richard Biener <rguenther@suse.de> + + * gimple-match-head.cc (single_use): Implement inline using a + single loop. + +2022-03-16 Roger Sayle <roger@nextmovesoftware.com> + + * match.pd (X CMP X -> true): Test tree_expr_maybe_nan_p + instead of HONOR_NANS. + (X LTGT X -> false): Enable if X is not tree_expr_maybe_nan_p, as + this can't trap/signal. + +2022-03-16 liuhongt <hongtao.liu@intel.com> + + PR target/104946 + * config/i386/i386-builtin.def (BDESC): Add + CODE_FOR_sse4_1_blendvpd for IX86_BUILTIN_BLENDVPD. + * config/i386/i386.cc (ix86_gimple_fold_builtin): Don't fold + __builtin_ia32_blendvpd w/o sse4.2 + +2022-03-15 Peter Bergner <bergner@linux.ibm.com> + + PR target/104923 + * config/rs6000/predicates.md (mma_disassemble_output_operand): Restrict + acceptable MEM addresses. + +2022-03-15 Jakub Jelinek <jakub@redhat.com> + + PR target/91229 + * config/riscv/riscv.cc (riscv_pass_aggregate_in_fpr_pair_p, + riscv_pass_aggregate_in_fpr_and_gpr_p): Pass OPT_Wpsabi instead of 0 + to warning calls. + +2022-03-15 Jakub Jelinek <jakub@redhat.com> + + PR target/104890 + * config/i386/i386.h (LIBGCC2_UNWIND_ATTRIBUTE): Use no-mmx,no-sse + instead of general-regs-only. + +2022-03-15 Roger Sayle <roger@nextmovesoftware.com> + Marc Glisse <marc.glisse@inria.fr> + Richard Biener <rguenther@suse.de> + + PR tree-optimization/101895 + * match.pd (vec_same_elem_p): Handle CONSTRUCTOR_EXPR def. + (plus (vec_perm (mult ...) ...) ...): New reordering simplification. + +2022-03-15 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/104814 + * ifcvt.cc (find_if_case_1, find_if_case_2): Punt if test_bb doesn't + end with onlyjump_p. Assume BB_END (test_bb) is always non-NULL. + +2022-03-15 Martin Sebor <msebor@redhat.com> + + PR middle-end/104436 + * gimple-ssa-warn-access.cc (pass_waccess::check_dangling_stores): + Check for warning suppression. Avoid by-value arguments transformed + into by-transparent-reference. + +2022-03-14 Roger Sayle <roger@nextmovesoftware.com> + Uroš Bizjak <ubizjak@gmail.com> + + * config/i386/i386.md (peephole2 xorl;movb -> movzbl): Disable + transformation when *zero_extend<mode>si2 is not available. + +2022-03-14 Xi Ruoyao <xry111@mengyan1223.wang> + + * config/mips/mips.h (SUBTARGET_SHADOW_OFFSET): Define. + * config/mips/mips.cc (mips_option_override): Make + -fsanitize=address imply -fasynchronous-unwind-tables. This is + needed by libasan for stack backtrace on MIPS. + (mips_asan_shadow_offset): Return SUBTARGET_SHADOW_OFFSET. + +2022-03-14 Jakub Jelinek <jakub@redhat.com> + + PR debug/104778 + * lra.cc (lra_substitute_pseudo): For debug_p mode, simplify + SUBREG, ZERO_EXTEND, SIGN_EXTEND, FLOAT or UNSIGNED_FLOAT if recursive + call simplified the first operand into VOIDmode constant. + +2022-03-14 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/102586 + * doc/extend.texi (__builtin_clear_padding): Clearify that for C++ + argument type should be pointer to trivially-copyable type unless it + is address of a variable or parameter. + +2022-03-14 Jakub Jelinek <jakub@redhat.com> + + PR target/99754 + * config/i386/emmintrin.h (_mm_loadu_si32): Put loaded value into + first rather than last element of the vector, use __m32_u to do + a really unaligned load, use just 0 instead of (int)0. + (_mm_loadu_si16): Put loaded value into first rather than last + element of the vector, use __m16_u to do a really unaligned load, + use just 0 instead of (short)0. + +2022-03-14 Jakub Jelinek <jakub@redhat.com> + + PR other/104899 + * config/bfin/bfin.cc (bfin_handle_longcall_attribute): Fix a typo + in diagnostic message - cannott -> cannot. Use %< and %> around + names of attribute. Avoid too long line. + * range-op.cc (operator_logical_and::op1_range): Fix up a typo + in comment - cannott -> cannot. Use 2 spaces after . instead of one. + +2022-03-14 liuhongt <hongtao.liu@intel.com> + + PR target/104666 + * config/i386/i386-expand.cc + (ix86_check_builtin_isa_match): New func. + (ix86_expand_builtin): Move code to + ix86_check_builtin_isa_match and call it. + * config/i386/i386-protos.h + (ix86_check_builtin_isa_match): Declare. + * config/i386/i386.cc (ix86_gimple_fold_builtin): Don't fold + builtin into gimple when isa mismatches. + +2022-03-13 Tobias Burnus <tobias@codesourcery.com> + + * doc/invoke.texi: Fix typos. + * doc/tm.texi.in: Remove duplicated word. + * doc/tm.texi: Regenerate. + +2022-03-12 Segher Boessenkool <segher@kernel.crashing.org> + + PR target/104829 + * config/rs6000/rs6000.cc (rs6000_machine_from_flags): Don't output + "ppc" and "ppc64" based on rs6000_cpu. + +2022-03-12 Thomas Schwinge <thomas@codesourcery.com> + + PR middle-end/100280 + PR middle-end/104892 + * omp-oacc-kernels-decompose.cc (omp_oacc_kernels_decompose_1): + Remove special handling of 'GOMP_MAP_FORCE_TOFROM'. + +2022-03-12 Thomas Schwinge <thomas@codesourcery.com> + + PR middle-end/100280 + PR middle-end/104086 + * omp-oacc-kernels-decompose.cc (omp_oacc_kernels_decompose_1): + Mark variables used in 'present' clauses as addressable. + * omp-low.cc (scan_sharing_clauses) <OMP_CLAUSE_MAP>: Gracefully + handle duplicate 'OMP_CLAUSE_MAP_DECL_MAKE_ADDRESSABLE'. + +2022-03-12 Thomas Schwinge <thomas@codesourcery.com> + + PR other/65095 + * tree-core.h (user_omp_claus_code_name): Declare function. + * tree.cc (user_omp_clause_code_name): New function. + +2022-03-12 Roger Sayle <roger@nextmovesoftware.com> + + PR middle-end/98420 + * match.pd (minus @0 @0): Additional checks for -fno-rounding-math + (the defaut) or -fno-signed-zeros. + +2022-03-12 Michael Meissner <meissner@linux.ibm.com> + + PR target/104868 + * config/rs6000/vsx.md (extendditi2): Use a 'b' constraint when + moving from a GPR register to an Altivec register. + +2022-03-11 Roger Sayle <roger@nextmovesoftware.com> + + PR tree-optimization/98335 + * config/i386/i386.md (peephole2): Eliminate redundant insv. + Combine movl followed by movb. Transform xorl followed by + a suitable movb or movw into the equivalent movz[bw]l. + +2022-03-11 Roger Sayle <roger@nextmovesoftware.com> + Richard Biener <rguenther@suse.de> + + PR tree-optimization/98335 + * builtins.cc (get_object_alignment_2): Export. + * builtins.h (get_object_alignment_2): Likewise. + * tree-ssa-alias.cc (ao_ref_alignment): New. + * tree-ssa-alias.h (ao_ref_alignment): Declare. + * tree-ssa-dse.cc (compute_trims): Improve logic deciding whether + to align head/tail, writing more bytes but using fewer store insns. + +2022-03-11 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104880 + * tree-ssa.cc (execute_update_address_taken): Remember if we + optimistically made something not addressable and + prepare to undo it. + +2022-03-11 Richard Biener <rguenther@suse.de> + + PR target/104762 + * config/i386/i386.cc (ix86_builtin_vectorization_cost): Do not + cost the first lane of SSE pieces as inserts for vec_construct. + +2022-03-10 Roger Sayle <roger@nextmovesoftware.com> + + PR c++/84964 + * calls.cc (expand_call): Ignore stack adjustments after sorry. + +2022-03-10 Vladimir N. Makarov <vmakarov@redhat.com> + + PR target/103074 + * lra-constraints.cc (split_reg): Set up + check_and_force_assignment_correctness_p when splitting hard + register live range. + +2022-03-10 Martin Jambor <mjambor@suse.cz> + + PR ipa/104813 + * ipa-cp.cc (create_specialized_node): Move removal of + self-recursive calls from callers vector before refrence + adjustments. + +2022-03-10 Richard Biener <rguenther@suse.de> + + PR tree-optimization/102943 + * gimple-range-cache.cc (sbr_sparse_bitmap::bitvec): + Make a bitmap_head. + (sbr_sparse_bitmap::sbr_sparse_bitmap): Adjust and switch + to tree view. + (sbr_sparse_bitmap::set_bb_range): Adjust. + (sbr_sparse_bitmap::get_bb_range): Likewise. + +2022-03-10 Richard Biener <rguenther@suse.de> + + PR tree-optimization/102943 + * tree-ssa-dom.cc (back_propagate_equivalences): Only + populate the dominance bitmap if fast queries are not + available. Use a tree view bitmap. + (record_temporary_equivalences): Cache the dominance bitmap + across all equivalences on the edge. + +2022-03-10 Tom de Vries <tdevries@suse.de> + + PR target/104840 + * config/nvptx/nvptx.md (define_attr "predicable"): Use no,yes instead + of false,true. + +2022-03-10 Tom de Vries <tdevries@suse.de> + + PR target/104783 + * config/nvptx/nvptx.cc (nvptx_init_unisimt_predicate) + (nvptx_output_unisimt_switch): Handle unisimt_outside_simt_predicate. + (nvptx_get_unisimt_outside_simt_predicate): New function. + (predicate_insn): New function, factored out of ... + (nvptx_reorg_uniform_simt): ... here. Predicate all emitted insns. + * config/nvptx/nvptx.h (struct machine_function): Add + unisimt_outside_simt_predicate field. + * config/nvptx/nvptx.md (define_insn "nvptx_warpsync") + (define_insn "nvptx_uniform_warp_check"): Make predicable. + +2022-03-10 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx.cc (nvptx_unisimt_handle_set): Handle unused + result. + +2022-03-10 Tom de Vries <tdevries@suse.de> + + PR target/104815 + * config/nvptx/nvptx.cc (nvptx_print_operand): Handle 'x' operand + modifier. + * config/nvptx/nvptx.md: Use %x0 destination operand in atom insns. + +2022-03-10 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx.md (define_insn "atomic_fetch_<logic><mode>"): + Emit atom.and.b64 instead of atom.b64.and. + +2022-03-10 Tom de Vries <tdevries@suse.de> + + * config/nvptx/t-nvptx (MULTILIB_EXTRA_OPTS): Move mptx=3.1 ... + (MULTILIB_OPTIONS): ... here. + +2022-03-10 Tom de Vries <tdevries@suse.de> + + PR target/104758 + * config/nvptx/nvptx.opt (misa): Set default to sm_30. + * config/nvptx/t-nvptx (MULTILIB_EXTRA_OPTS): Remove misa=sm_30. + +2022-03-10 Thomas Schwinge <thomas@codesourcery.com> + + PR middle-end/90115 + PR middle-end/102330 + PR middle-end/104774 + * omp-low.cc (oacc_privatization_candidate_p) + (oacc_privatization_scan_clause_chain) + (oacc_privatization_scan_decl_chain, lower_oacc_private_marker): + Analyze 'lookup_decl'-translated DECL. + +2022-03-10 Jakub Jelinek <jakub@redhat.com> + + PR target/99708 + * config/rs6000/rs6000.h (enum rs6000_builtin_type_index): Remove + RS6000_BTI_ptr_ieee128_float and RS6000_BTI_ptr_ibm128_float. + (ptr_ieee128_float_type_node, ptr_ibm128_float_type_node): Remove. + * config/rs6000/rs6000-builtin.cc (rs6000_type_string): Return + "**NULL**" if type_node is NULL first. Handle + ieee128_float_type_node. + (rs6000_init_builtins): Don't initialize ptr_ieee128_float_type_node + and ptr_ibm128_float_type_node. Set ibm128_float_type_node and + ieee128_float_type_node to NULL rather than long_double_type_node if + they aren't supported. Do support __ibm128 even if + !TARGET_FLOAT128_TYPE when long double is double double. + (rs6000_expand_builtin): Error if bif_is_ibm128 and + !ibm128_float_type_node. Remap RS6000_BIF_{,UN}PACK_IF to + RS6000_BIF_{,UN}PACK_TF much earlier and only use bif_is_ibm128 check + for it. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + __SIZEOF_FLOAT128__ here and only iff __float128 macro is defined. + (rs6000_cpu_cpp_builtins): Don't define __SIZEOF_FLOAT128__ here. + Define __SIZEOF_IBM128__=16 if ieee128_float_type_node is non-NULL. + Formatting fix. + * config/rs6000/rs6000-gen-builtins.cc: Document ibm128 attribute. + (struct attrinfo): Add isibm128 member. + (TYPE_MAP_SIZE): Remove. + (type_map): Use [] instead of [TYPE_MAP_SIZE]. For "if" use + ibm128_float_type_node only if it is non-NULL, otherwise fall back + to long_double_type_node. Remove "pif" entry. + (parse_bif_attrs): Handle ibm128 attribute and print it for debugging. + (write_decls): Output bif_ibm128_bit and bif_is_ibm128. + (write_type_node): Use sizeof type_map / sizeof type_map[0] + instead of TYPE_MAP_SIZE. + (write_bif_static_init): Handle isibm128. + * config/rs6000/rs6000-builtins.def: Document ibm128 attribute. + (__builtin_pack_ibm128, __builtin_unpack_ibm128): Add ibm128 + attribute. + +2022-03-09 Richard Biener <rguenther@suse.de> + + * cfgexpand.cc (expand_gimple_asm): Special-case MEM_REF + with non-decl operand, avoiding a copy. + +2022-03-09 Jakub Jelinek <jakub@redhat.com> + + PR target/104781 + * config/i386/i386.h (LIBGCC2_UNWIND_ATTRIBUTE): Define for ia32. + +2022-03-09 Richard Biener <rguenther@suse.de> + + PR middle-end/104786 + * cfgexpand.cc (expand_asm_stmt): Do not generate a copy + for VLAs without an upper size bound. + +2022-03-09 Xi Ruoyao <xry111@mengyan1223.wang> + + PR tree-optimization/104851 + * optabs-query.cc (supports_vec_convert_optab_p): Fix off-by-one + error. + +2022-03-09 Jakub Jelinek <jakub@redhat.com> + + PR c/104711 + * doc/invoke.texi (-Wextra): Document that -Wshift-negative-value + is enabled by it only for C++11 to C++17 rather than for C++03 or + later. + (-Wshift-negative-value): Similarly (except here we stated + that it is enabled for C++11 or later). + +2022-03-09 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/104839 + * simplify-rtx.cc (simplify_unary_operation_1) <case SIGN_EXTEND>: + Use SRP_SIGNED instead of incorrect 1 in SUBREG_PROMOTED_SET. + (simplify_unary_operation_1) <case ZERO_EXTEND>: Use SRP_UNSIGNED + instead of incorrect 0 in SUBREG_PROMOTED_SET. + +2022-03-09 Xi Ruoyao <xry111@mengyan1223.wang> + + PR target/104842 + * config/mips/mips.h (LUI_OPERAND): Cast the input to an unsigned + value before adding an offset. + +2022-03-08 Christophe Lyon <christophe.lyon@arm.com> + + * config/arm/arm-builtins.cc + (arm_binop_none_none_unone_qualifiers): Delete. + (BINOP_NONE_NONE_UNONE_QUALIFIERS): Delete. + +2022-03-08 Iain Sandoe <iain@sandoe.co.uk> + + PR translation/104552 + * config/host-darwin.cc (darwin_gt_pch_get_address): Amend + the PCH out of memory error message punctuation and wording. + +2022-03-08 Marek Polacek <polacek@redhat.com> + + PR rtl-optimization/104777 + * rtl.cc (classify_insn): For ASM_OPERANDS, return JUMP_INSN only if + ASM_OPERANDS_LABEL_VEC has at least one element. + +2022-03-08 H.J. Lu <hjl.tools@gmail.com> + + PR target/104781 + * config/i386/i386.cc (ix86_expand_epilogue): Sorry if there is + stack realignment or regparm nested function with EH return. + +2022-03-08 Andre Vieira <andre.simoesdiasvieira@arm.com> + + PR target/104790 + * config/arm/arm.h (MVE_STN_LDW_MODE): New MACRO. + * config/arm/arm.cc (mve_vector_mem_operand): Relax constraint on base + register for non widening loads or narrowing stores. + +2022-03-08 Eric Gallager <egallager@gcc.gnu.org> + + PR translation/104552 + * params.opt: Fix typo. + +2022-03-08 Richard Biener <rguenther@suse.de> + + PR tree-optimization/84201 + * params.opt (-param=vect-induction-float): Add. + * doc/invoke.texi (vect-induction-float): Document. + * tree-vect-loop.cc (vectorizable_induction): Honor + param_vect_induction_float. + +2022-03-08 Martin Jambor <mjambor@suse.cz> + + PR translation/104552 + * params.opt (ipa-cp-recursive-freq-factor): Remove repeated word + "that" in the description. + +2022-03-08 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104825 + * tree-ssa-sccvn.cc (visit_reference_op_call): Properly + guard modref get_ao_ref on a pointer typed argument. + +2022-03-08 liuhongt <hongtao.liu@intel.com> + + * config/i386/sse.md (*vec_dupv4si): Disable memory operand + for !TARGET_INTER_UNIT_MOVES_TO_VEC when prefer_for_speed. + +2022-03-07 Jonathan Wakely <jwakely@redhat.com> + + * doc/invoke.texi (C++ Modules): Remove anachronism. + +2022-03-07 Martin Liska <mliska@suse.cz> + + PR middle-end/104381 + * opts.cc (finish_options): If debug info is disabled + (debug_info_level) and -fvar-tracking is unset, disable it. + +2022-03-07 Jakub Jelinek <jakub@redhat.com> + + * tree-ssa-propagate.cc: Fix up duplicated word issue in a comment. + * config/riscv/riscv.cc: Likewise. + * config/darwin.h: Likewise. + * config/i386/i386.cc: Likewise. + * config/aarch64/thunderx3t110.md: Likewise. + * config/aarch64/fractional-cost.h: Likewise. + * config/vax/vax.cc: Likewise. + * config/rs6000/pcrel-opt.md: Likewise. + * config/rs6000/predicates.md: Likewise. + * ctfc.h: Likewise. + * tree-ssa-uninit.cc: Likewise. + * value-relation.h: Likewise. + * gimple-range-gori.cc: Likewise. + * ipa-polymorphic-call.cc: Likewise. + * pointer-query.cc: Likewise. + * ipa-sra.cc: Likewise. + * internal-fn.cc: Likewise. + * varasm.cc: Likewise. + * gimple-ssa-warn-access.cc: Likewise. + +2022-03-07 Martin Liska <mliska@suse.cz> + + PR target/104794 + * config/arm/arm.cc (arm_option_override_internal): Add missing + space. + +2022-03-07 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104782 + * tree-vect-slp.cc (vectorize_slp_instance_root_stmt): + Re-instantiate r10-5979 fix, add comment. + +2022-03-07 Martin Liska <mliska@suse.cz> + + PR target/104797 + * config/msp430/msp430.cc (msp430_expand_delay_cycles): Remove + parenthesis from built-in name. + +2022-03-07 Martin Liska <mliska@suse.cz> + + PR target/104794 + * config/arm/arm.cc (arm_option_override_internal): Fix quoting + of options in error messages. + (arm_option_reconfigure_globals): Likewise. + +2022-03-07 Martin Liska <mliska@suse.cz> + + PR target/104794 + * config/arm/arm-builtins.cc (arm_expand_builtin): Reuse error + message. Fix ARM_BUILTIN_WRORHI and ARM_BUILTIN_WRORH that can + have only range [0,32]. + +2022-03-07 Jakub Jelinek <jakub@redhat.com> + + PR target/104775 + * config/s390/s390.md (*cmp_and_trap_unsigned_int<mode>): Use + S constraint instead of T in the last alternative. + +2022-03-07 Martin Liska <mliska@suse.cz> + + * plugin.cc (default_plugin_dir_name): Remove <dir> from error + message. + +2022-03-07 Martin Liska <mliska@suse.cz> + + PR translation/90148 + * config/rs6000/rs6000.cc (rs6000_linux64_override_options): Put + quote to a proper place. + * plugin.cc (default_plugin_dir_name): Likewise. + +2022-03-07 Martin Liska <mliska@suse.cz> + + PR target/99297 + * config/rx/rx.cc (rx_expand_builtin_mvtc): Fix translation + string. + +2022-03-07 Jakub Jelinek <jakub@redhat.com> + + PR target/104779 + * config/i386/sse.md (avx512dq_mul<mode>3<mask_name>): New + define_expand pattern. Rename define_insn to ... + (*avx512dq_mul<mode>3<mask_name>): ... this. + (<code><mode>3_mask): New any_logic define_expand pattern. + (<mask_codefor><code><mode>3<mask_name>): Rename to ... + (*<code><mode>3<mask_name>): ... this. + +2022-03-05 Jakub Jelinek <jakub@redhat.com> + + * gimple-ssa-warn-access.cc (pass_waccess::use_after_inval_p): Remove + visited bitmap and its use. Also punt on EDGE_ABNORMAL edges. + +2022-03-05 Roger Sayle <roger@nextmovesoftware.com> + Uroš Bizjak <ubizjak@gmail.com> + + PR testsuite/104732 + * config/i386/i386.md (SWIM1248x): Renamed from SWIM1248s. + Include DI mode unconditionally. + (*anddi3_doubleword): Remove && TARGET_STV && TARGET_SSE2 condition, + i.e. always split on !TARGET_64BIT. + (*<any_or>di3_doubleword): Likewise. + (*one_cmpldi2_doubleword): Likewise. + (and<mode>3 expander): Update to use SWIM1248x from SWIM1248s. + (<any_or><mode>3 expander): Likewise. + (one_cmpl<mode>2 expander): Likewise. + +2022-03-05 Michael Meissner <meissner@linux.ibm.com> + + PR target/104698 + * config/rs6000/vsx.md (UNSPEC_MTVSRD_DITI_W1): Delete. + (mtvsrdd_diti_w1): Delete. + (extendditi2): Convert from define_expand to + define_insn_and_split. Replace with code to deal with both GPR + registers and with altivec registers. + +2022-03-04 Segher Boessenkool <segher@kernel.crashing.org> + + * config/rs6000/rs6000.cc (rs6000_machine_from_flags): Restructure a + bit. Handle most older CPUs. + +2022-03-04 Iain Sandoe <iain@sandoe.co.uk> + + * config/darwin.cc (darwin_fold_builtin): Make fcode an int to + avoid a mismatch with DECL_MD_FUNCTION_CODE(). + +2022-03-04 Iain Sandoe <iain@sandoe.co.uk> + + PR target/104117 + * config/rs6000/darwin.md (@machopic_high_<mode>): New. + (@machopic_low_<mode>): New. + * config/rs6000/predicates.md (macho_pic_address): New. + * config/rs6000/rs6000.cc (rs6000_legitimize_address): Do not + apply the TLS processing to Darwin. + * lra-constraints.cc (process_address_1): Revert the changes + in r12-7209. + +2022-03-04 Peter Bergner <bergner@linux.ibm.com> + + PR target/87496 + PR target/104208 + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Make the + ISA 2.06 requirement for -mabi=ieeelongdouble conditional on + -mlong-double-128. + Move the -mabi=ieeelongdouble and -mabi=ibmlongdouble error checking + from here... + * common/config/rs6000/rs6000-common.cc (rs6000_handle_option): + ... to here. + +2022-03-04 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/104529 + * gimplify.cc (gimplify_init_constructor): Clear TREE_READONLY + on automatic objects which will be runtime initialized. + +2022-03-04 Thomas Schwinge <thomas@codesourcery.com> + + PR middle-end/100280 + PR middle-end/104132 + PR middle-end/104133 + * omp-low.cc (task_shared_vars): Rename to + 'make_addressable_vars'. Adjust all users. + (scan_sharing_clauses) <OMP_CLAUSE_MAP> Use it for + 'OMP_CLAUSE_MAP_DECL_MAKE_ADDRESSABLE' DECLs, too. + +2022-03-04 Thomas Schwinge <thomas@codesourcery.com> + + PR middle-end/100280 + * tree.h (OMP_CLAUSE_MAP_DECL_MAKE_ADDRESSABLE): New. + * tree-core.h: Document it. + * omp-low.cc (scan_sharing_clauses) <OMP_CLAUSE_MAP>: Handle + 'OMP_CLAUSE_MAP_DECL_MAKE_ADDRESSABLE'. + * omp-oacc-kernels-decompose.cc (maybe_build_inner_data_region): + Set 'OMP_CLAUSE_MAP_DECL_MAKE_ADDRESSABLE' instead of + 'TREE_ADDRESSABLE'. + +2022-03-04 Thomas Schwinge <thomas@codesourcery.com> + + PR middle-end/100280 + * omp-oacc-kernels-decompose.cc (maybe_build_inner_data_region): + Add diagnostic: "note: OpenACC 'kernels' decomposition: variable + '[...]' declared in block made addressable". + +2022-03-04 Thomas Schwinge <thomas@codesourcery.com> + + PR middle-end/100400 + PR middle-end/103836 + PR middle-end/104061 + * omp-oacc-kernels-decompose.cc (decompose_kernels_region_body): + Catch 'GIMPLE_DEBUG'. + +2022-03-04 Jakub Jelinek <jakub@redhat.com> + + PR c/104627 + * tree.cc (warn_deprecated_use): For types prefer to use node + and only use TYPE_MAIN_VARIANT (node) if TYPE_STUB_DECL (node) is + NULL. + +2022-03-04 H.J. Lu <hjl.tools@gmail.com> + + PR target/104704 + * config/i386/i386.cc (ix86_gen_scratch_sse_rtx): Always return + a pseudo register. + +2022-03-03 Martin Sebor <msebor@redhat.com> + + PR middle-end/104761 + * gimple-ssa-warn-access.cc (pass_waccess::execute): Call + mark_dfs_back_edges. + +2022-03-03 Martin Liska <mliska@suse.cz> + + * configure.ac: Use linker plug-in by default. + * configure: Regenerate. + +2022-03-03 Martin Liska <mliska@suse.cz> + + * configure.ac: Now ld.mold support LTO plugin API, use it. + * configure: Regenerate. + +2022-03-03 Tom de Vries <tdevries@suse.de> + + * config/nvptx/t-nvptx (MULTILIB_EXTRA_OPTS): Add mptx=3.1. + +2022-03-03 Tom de Vries <tdevries@suse.de> + + PR target/104758 + * config/nvptx/t-nvptx (MULTILIB_EXTRA_OPTS): Add misa=sm_30. + +2022-03-03 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx.h (ASM_SPEC): Add %{misa=sm_30:--no-verify}. + +2022-03-03 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/104757 + * gimplify.cc (gimplify_omp_loop): Call gimplify_expr rather than + gimplify_omp_for. + (gimplify_expr) <case OMP_SIMD>: Temporarily disable + gimplify_ctxp->into_ssa around call to gimplify_omp_for. + +2022-03-03 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/104558 + * calls.cc (store_one_arg): When not calling emit_push_insn + because size_rtx is const0_rtx, call at least anti_adjust_stack + on arg->locate.alignment_pad if !argblock and the alignment might + be non-zero. + +2022-03-02 Alexandre Oliva <oliva@adacore.com> + + * lra-constraints.cc (undo_optional_reloads): Recognize and + drop insns of multi-word move sequences, tolerate removal + iteration on an already-removed clobber, and refuse to + substitute original pseudos into clobbers. + +2022-03-02 Qing Zhao <qing.zhao@oracle.com> + + PR middle-end/102276 + * common.opt (-Wtrivial-auto-var-init): New option. + * doc/invoke.texi (-Wtrivial-auto-var-init): Document new option. + (-ftrivial-auto-var-init): Update option; + * gimplify.cc (emit_warn_switch_unreachable): New function. + (warn_switch_unreachable_r): Rename to ... + (warn_switch_unreachable_and_auto_init_r): This. + (maybe_warn_switch_unreachable): Rename to ... + (maybe_warn_switch_unreachable_and_auto_init): This. + (gimplify_switch_expr): Update calls to renamed function. + +2022-03-02 Richard Biener <rguenther@suse.de> + + PR rtl-optimization/104686 + * ira-color.cc (object_conflicts_with_allocno_p): New function + using a bitvector test instead of iterating when possible. + (allocnos_conflict_p): Choose the best allocno to iterate over + object conflicts. + (update_conflict_hard_regno_costs): Do allocnos_conflict_p test + last. + +2022-03-02 Jakub Jelinek <jakub@redhat.com> + + * cfg.cc (dump_edge_info): Dump goto_locus if present. + +2022-03-02 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/104589 + * cfgrtl.cc (fixup_reorder_chain): Use loc_equal instead of direct + INSN_LOCATION comparison with goto_locus. + +2022-03-02 Jakub Jelinek <jakub@redhat.com> + + * tree-ssa-strlen.cc (strlen_pass::handle_assign, + strlen_pass::before_dom_children): Comment spelling fixes. + +2022-03-02 Jakub Jelinek <jakub@redhat.com> + + * ipa-modref-tree.cc (modref_access_node::contains, + modref_access_node::closer_pair_p, modref_access_node::insert, + modref_access_node::insert_kill): Comment spelling fixes. + * ipa-modref.cc: Likewise. + (modref_summary::finalize, ignore_nondeterminism_p, + class modref_access_analysis, + modref_access_analysis::set_side_effects, + modref_access_analysis::set_nondeterministic, + modref_access_analysis::record_global_memory_load, + modref_access_analysis::propagate, modref_access_analysis::analyze, + struct escape_point, class modref_lattice, modref_lattice::merge, + modref_lattice::merge_deref, class modref_eaf_analysis, + modref_eaf_analysis::merge_call_lhs_flags, + modref_eaf_analysis::analyze_ssa_name, modref_eaf_analysis::propagate, + modref_eaf_analysis::record_escape_points, remap_kills, + update_escape_summary, remove_useless_summaries, + ipa_merge_modref_summary_after_inlining, pass_ipa_modref::execute): + Likewise. + * ipa-modref.h (struct modref_summary, interposable_eaf_flags): + Likewise. + * ipa-modref-tree.h (enum modref_special_parms, + struct modref_access_node): Likewise. + +2022-03-01 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/104715 + * gimple-ssa-warn-access.cc (pass_waccess::check_pointer_uses): Don't + unnecessarily test if ptr is a SSA_NAME, it has to be. Only push lhs + of a call if gimple_call_return_arg is equal to ptr, not just when it + is non-NULL. + +2022-03-01 Jakub Jelinek <jakub@redhat.com> + + * gimple-ssa-warn-access.cc (warn_string_no_nul, + maybe_warn_nonstring_arg, fndecl_alloc_p, new_delete_mismatch_p, + matching_alloc_calls_p, maybe_warn_alloc_args_overflow, + pass_waccess::check_alloca, pass_waccess::check_strcat, + memmodel_to_uhwi, fntype_argno_type, + pass_waccess::maybe_check_access_sizes, + pass_waccess::check_call_access, + pass_waccess::maybe_check_dealloc_call, pass_waccess::check_stmt): + Comment spelling fixes. + +2022-03-01 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104716 + * tree-loop-distribution.cc (find_seed_stmts_for_distribution): + Check if we can copy the loop. + +2022-03-01 H.J. Lu <hjl.tools@gmail.com> + + PR middle-end/104721 + * cfgexpand.cc (expand_gimple_basic_block): Clear + currently_expanding_gimple_stmt when returning inside the loop. + +2022-03-01 Martin Liska <mliska@suse.cz> + + PR ipa/104533 + * multiple_target.cc (get_attr_len): Move to tree.c. + (expand_target_clones): Remove single value checking. + * tree.cc (get_target_clone_attr_len): New fn. + * tree.h (get_target_clone_attr_len): Likewise. + +2022-03-01 Martin Liska <mliska@suse.cz> + + PR gcov-profile/104677 + * doc/invoke.texi: Document more .gcda file name generation. + +2022-03-01 Tom de Vries <tdevries@suse.de> + + PR target/102429 + * config/nvptx/nvptx.cc (nvptx_gen_shuffle): Handle DCmode and CDImode. + * config/nvptx/nvptx.md + (define_predicate "nvptx_register_or_complex_di_df_register_operand"): + New predicate. + (define_expand "omp_simt_xchg_bfly", define_expand "omp_simt_xchg_idx"): + Use nvptx_register_or_complex_di_df_register_operand. + +2022-03-01 Tom de Vries <tdevries@suse.de> + + * config.gcc (nvptx*-*-*): Add nvptx/nvptx-gen.opt to extra_options. + * config/nvptx/gen-copyright.sh: New file. + * config/nvptx/gen-h.sh: New file. + * config/nvptx/gen-opt.sh: New file. + * config/nvptx/nvptx.h (TARGET_SM35, TARGET_SM53, TARGET_SM70) + (TARGET_SM75, TARGET_SM80): Move ... + * config/nvptx/nvptx-gen.h: ... here. New file, generate. + * config/nvptx/nvptx.opt (Enum ptx_isa): Move ... + * config/nvptx/nvptx-gen.opt: ... here. New file, generate. + * config/nvptx/t-nvptx ($(srcdir)/config/nvptx/nvptx-gen.h) + ($(srcdir)/config/nvptx/nvptx-gen.opt): New make target. + +2022-03-01 Tom de Vries <tdevries@suse.de> + + * config/nvptx/gen-omp-device-properties.sh: New file. + * config/nvptx/t-omp-device: Use gen-omp-device-properties.sh. + +2022-03-01 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx-sm.def: New file. + * config/nvptx/nvptx-c.cc (nvptx_cpu_cpp_builtins): Use nvptx-sm.def. + * config/nvptx/nvptx-opts.h (enum ptx_isa): Same. + * config/nvptx/nvptx.cc (sm_version_to_string) + (nvptx_omp_device_kind_arch_isa): Same. + +2022-03-01 Robin Dapp <rdapp@linux.ibm.com> + + PR rtl-optimization/104154 + * config/arc/arc.cc (gen_compare_reg): Return the CC-mode + comparison ifcvt passed us. + +2022-03-01 Hongyu Wang <hongyu.wang@intel.com> + + PR target/104664 + * config/i386/i386-expand.cc (ix86_expand_vector_init_duplicate): + Use vec_setv8hf_0 for HF to V8HFmode move instead of subreg. + +2022-02-28 Roger Sayle <roger@nextmovesoftware.com> + + PR tree-optimization/91384 + * config/i386/i386.md (peephole2): Eliminate final testl insn + from the sequence *movsi_internal, *negsi_1, *cmpsi_ccno_1 by + transforming using *negsi_2 for the negation. + +2022-02-28 Roger Sayle <roger@nextmovesoftware.com> + Eric Botcazou <ebotcazou@adacore.com> + + PR middle-end/80270 + * expmed.cc (extract_integral_bit_field): If OP0 is a hard + register, copy it to a pseudo before calling simplify_gen_subreg. + +2022-02-28 Vladimir N. Makarov <vmakarov@redhat.com> + + PR rtl-optimization/104637 + * lra-assigns.cc (lra_split_hard_reg_for): Split hard regs as many + as possible on one subpass. + +2022-02-28 Qing Zhao <qing.zhao@oracle.com> + + PR middle-end/104550 + * gimple-fold.cc (clear_padding_flush): Suppress warnings for new + created uses. + +2022-02-28 Martin Liska <mliska@suse.cz> + + PR ipa/104648 + * main.cc (main): Use flag_checking instead of CHECKING_P + and run toplev::finalize only if there is not error seen. + +2022-02-28 Richard Biener <rguenther@suse.de> + + * tree-ssa-pre.cc (compute_avail): Revert part of last change. + +2022-02-28 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104700 + * tree-ssa-pre.cc (get_or_alloc_expr_for): Remove and inline + into ... + (find_or_generate_expression): ... here, simplifying code. + +2022-02-28 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx-opts.h (enum ptx_version): Add + PTX_VERSION_default. + * config/nvptx/nvptx.cc (handle_ptx_version_option): Handle + PTX_VERSION_default. + * config/nvptx/nvptx.opt: Add EnumValue "_" / PTX_VERSION_default. + +2022-02-28 Richard Biener <rguenther@suse.de> + + PR rtl-optimization/104686 + * ira-int.h (minmax_set_iter_cond): Use ctz_hwi to elide loop + skipping bits that are zero. + (ira_object_conflict_iter_cond): Likewise. + +2022-02-28 Hongyu Wang <hongyu.wang@intel.com> + + * config/i386/avx512fintrin.h (_MM_TERNLOG_ENUM): New enum. + (_mm512_ternarylogic_epi64): Truncate imm to unsigned + char to avoid error when using ~enum as parameter. + (_mm512_mask_ternarylogic_epi64): Likewise. + (_mm512_maskz_ternarylogic_epi64): Likewise. + (_mm512_ternarylogic_epi32): Likewise. + (_mm512_mask_ternarylogic_epi32): Likewise. + (_mm512_maskz_ternarylogic_epi32): Likewise. + * config/i386/avx512vlintrin.h (_mm256_ternarylogic_epi64): + Adjust imm param type to unsigned char. + (_mm256_mask_ternarylogic_epi64): Likewise. + (_mm256_maskz_ternarylogic_epi64): Likewise. + (_mm256_ternarylogic_epi32): Likewise. + (_mm256_mask_ternarylogic_epi32): Likewise. + (_mm256_maskz_ternarylogic_epi32): Likewise. + (_mm_ternarylogic_epi64): Likewise. + (_mm_mask_ternarylogic_epi64): Likewise. + (_mm_maskz_ternarylogic_epi64): Likewise. + (_mm_ternarylogic_epi32): Likewise. + (_mm_mask_ternarylogic_epi32): Likewise. + (_mm_maskz_ternarylogic_epi32): Likewise. + +2022-02-25 Jakub Jelinek <jakub@redhat.com> + Marc Glisse <marc.glisse@inria.fr> + + PR tree-optimization/104675 + * match.pd (t * 2U / 2 -> t & (~0 / 2), t / 2U * 2 -> t & ~1): + Restrict simplifications to INTEGRAL_TYPE_P. + +2022-02-25 Jakub Jelinek <jakub@redhat.com> + + PR target/104681 + * config/rs6000/vector.md (movmisalign<mode>): Use rs6000_emit_move. + +2022-02-25 Claudiu Zissulescu <claziss@synopsys.com> + + * config/arc/arc.cc (gen_compare_reg): Return NULL_RTX if the + comparison is not valid. + * config/arc/arc.md (movsicc): Fail if comparison is not valid. + (movdicc): Likewise. + (movsfcc): Likewise. + (movdfcc): Likewise. + +2022-02-25 Richard Biener <rguenther@suse.de> + + PR tree-optimization/103037 + * tree-ssa-sccvn.h (alloc_vn_nary_op_noinit): Declare. + (vn_nary_length_from_stmt): Likewise. + (init_vn_nary_op_from_stmt): Likewise. + (vn_nary_op_compute_hash): Likewise. + * tree-ssa-sccvn.cc (alloc_vn_nary_op_noinit): Export. + (vn_nary_length_from_stmt): Likewise. + (init_vn_nary_op_from_stmt): Likewise. + (vn_nary_op_compute_hash): Likewise. + * tree-ssa-pre.cc (pre_expr_obstack): New obstack. + (get_or_alloc_expr_for_nary): Pass in the value-id to use, + (re-)compute the hash value and if the expression is not + found allocate it from pre_expr_obstack. + (phi_translate_1): Do not insert the NARY found in the + VN tables but build a PRE expression from the valueized + NARY with the value-id we eventually found. + (find_or_generate_expression): Assert we have an entry + for constant values. + (compute_avail): Insert not valueized expressions into + EXP_GEN using the value-id from the VN tables. + (init_pre): Allocate pre_expr_obstack. + (fini_pre): Free pre_expr_obstack. + +2022-02-25 Jakub Jelinek <jakub@redhat.com> + + PR target/104674 + * config/i386/i386.h (enum ix86_stack_slot): Add SLOT_FLOATxFDI_387. + * config/i386/i386.md (splitter to floatdi<mode>2_i387_with_xmm): Use + SLOT_FLOATxFDI_387 rather than SLOT_TEMP. + +2022-02-25 Jakub Jelinek <jakub@redhat.com> + + * warning-control.cc (get_nowarn_spec): Comment spelling fix. + +2022-02-25 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/104679 + * internal-fn.cc (expand_SPACESHIP): Call do_pending_stack_adjust. + +2022-02-25 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/104675 + * match.pd (-A - 1 -> ~A, -1 - A -> ~A): Don't simplify for + COMPLEX_TYPE. + +2022-02-25 Alexandre Oliva <oliva@adacore.com> + + PR target/104121 + PR target/103302 + * expr.cc (emit_move_multi_word): Restore clobbers during LRA. + +2022-02-25 Alexandre Oliva <oliva@adacore.com> + + PR middle-end/104540 + * dwarf2cfi.cc (cfi_oprnd_equal_p): Cope with NULL + dw_cfi_cfa_loc. + +2022-02-25 Alexandre Oliva <oliva@adacore.com> + + PR tree-optimization/103856 + * gimple-harden-conditionals.cc (non_eh_succ_edge): Enable the + eh edge to be requested through an extra parameter. + (pass_harden_compares::execute): Copy PHI args in the EH dest + block for the new EH edge added for the inverted compare. + +2022-02-24 Palmer Dabbelt <palmer@rivosinc.com> + + * doc/invoke.texi (RISC-V -mcmodel=medany): Document the degree + of position independence that -mcmodel=medany affords. + +2022-02-24 Jose E. Marchesi <jose.marchesi@oracle.com> + + PR target/104656 + * configure.ac: --disable-gcov if targetting bpf-*. + * configure: Regenerate. + +2022-02-24 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104676 + * tree-loop-distribution.cc (loop_distribution::execute): + Do a full scev_reset. + +2022-02-24 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/104601 + * tree-ssa-sccvn.cc (visit_reference_op_call): For calls with + non-SSA_NAME lhs value number vdef to itself instead of e.g. the + vuse value number. + +2022-02-24 Tom de Vries <tdevries@suse.de> + Tobias Burnus <tobias@codesourcery.com> + + * config/nvptx/nvptx.cc (nvptx_omp_device_kind_arch_isa): Handle + sm_70, sm_75 and sm_80. + * config/nvptx/t-omp-device: Add sm_53, sm_70, sm_75 and sm_80. + +2022-02-24 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx.md (define_insn "rotlsi3", define_insn + "rotrsi3"): New define_insn. + +2022-02-24 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx.cc (gen_comment): Use + DECL_SOURCE_LOCATION (cfun->decl) instead of cfun->function_start_locus. + +2022-02-24 liuhongt <hongtao.liu@intel.com> + + * config/i386/sse.md (<code>v1ti3): Add suffix and replace + isa attr of alternative 2 from avx to avx512vl. + +2022-02-23 Richard Biener <rguenther@suse.de> + Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/104644 + * doc/match-and-simplify.texi: Amend ! documentation. + * genmatch.cc (expr::gen_transform): Code-generate ! support + for GENERIC. + (parser::parse_expr): Allow ! for GENERIC. + * match.pd (cmp (bswap @0) INTEGER_CST@1): Use ! modifier on + bswap. + +2022-02-23 Richard Biener <rguenther@suse.de> + + PR tree-optimization/101636 + * tree-vect-slp.cc (vect_print_slp_tree): Dump the + vector type of the node. + (vect_slp_analyze_operations): Make sure the CTOR + is vectorized with an expected type. + (vectorize_slp_instance_root_stmt): Revert r10-5979 fix. + +2022-02-23 Jakub Jelinek <jakub@redhat.com> + + PR c/104633 + * gimple-warn-recursion.cc (pass_warn_recursion::find_function_exit): + Don't warn about calls to corresponding builtin from extern inline + gnu_inline wrappers. + +2022-02-23 Roger Sayle <roger@nextmovesoftware.com> + + PR target/104489 + * config/nvptx/nvptx.md (*movhf_insn): Add subregs_ok attribute. + +2022-02-23 Christophe Lyon <christophe.lyon@arm.com> + + PR target/100757 + PR target/101325 + * config/arm/vfp.md (thumb2_movhi_vfp, thumb2_movhi_fp16): Fix + typo. + +2022-02-23 Cui,Lili <lili.cui@intel.com> + + * doc/invoke.texi: Update documents for Intel architectures. + +2022-02-22 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/i386-expand.cc (ix86_expand_cmpxchg_loop): Restore + bootstrap. + +2022-02-22 Thomas Schwinge <thomas@codesourcery.com> + + * omp-low.cc (omp_build_component_ref): Move function... + * omp-general.cc (omp_build_component_ref): ... here. Remove + 'static'. + * omp-general.h (omp_build_component_ref): Declare function. + * omp-oacc-neuter-broadcast.cc (oacc_build_component_ref): Remove + function. + (build_receiver_ref, build_sender_ref): Call + 'omp_build_component_ref' instead. + +2022-02-22 Thomas Schwinge <thomas@codesourcery.com> + + * omp-oacc-neuter-broadcast.cc (record_field_map_t): Further + simplify. Adjust all users. + +2022-02-22 Segher Boessenkool <segher@kernel.crashing.org> + + PR target/88134 + * config/rs6000/rs6000.cc (atomic_hold_decl, atomic_clear_decl, + atomic_update_decl): Add GTY markup. + +2022-02-22 Christophe Lyon <christophe.lyon@arm.com> + + * config/arm/arm.h (REG_CLASS_CONTENTS): Add VPR_REG to ALL_REGS. + +2022-02-22 Christophe Lyon <christophe.lyon@arm.com> + + PR target/100757 + PR target/101325 + * config/arm/arm-builtins.cc (CX_UNARY_UNONE_QUALIFIERS): Use + predicate. + (CX_BINARY_UNONE_QUALIFIERS): Likewise. + (CX_TERNARY_UNONE_QUALIFIERS): Likewise. + (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Delete. + (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Delete. + (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Delete. + * config/arm/arm_mve_builtins.def: Use predicated qualifiers. + * config/arm/mve.md: Use VxBI instead of HI. + +2022-02-22 Christophe Lyon <christophe.lyon@arm.com> + + PR target/100757 + PR target/101325 + * config/arm/arm-builtins.cc (STRSBS_P_QUALIFIERS): Use predicate + qualifier. + (STRSBU_P_QUALIFIERS): Likewise. + (LDRGBS_Z_QUALIFIERS): Likewise. + (LDRGBU_Z_QUALIFIERS): Likewise. + (LDRGBWBXU_Z_QUALIFIERS): Likewise. + (LDRGBWBS_Z_QUALIFIERS): Likewise. + (LDRGBWBU_Z_QUALIFIERS): Likewise. + (STRSBWBS_P_QUALIFIERS): Likewise. + (STRSBWBU_P_QUALIFIERS): Likewise. + * config/arm/mve.md: Use VxBI instead of HI. + +2022-02-22 Christophe Lyon <christophe.lyon@arm.com> + + PR target/100757 + PR target/101325 + * config/arm/arm-builtins.cc (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Change to ... + (TERNOP_UNONE_UNONE_NONE_PRED_QUALIFIERS): ... this. + (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Change to ... + (TERNOP_UNONE_UNONE_IMM_PRED_QUALIFIERS): ... this. + (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Change to ... + (TERNOP_NONE_NONE_IMM_PRED_QUALIFIERS): ... this. + (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Change to ... + (TERNOP_NONE_NONE_UNONE_PRED_QUALIFIERS): ... this. + (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Change to ... + (QUADOP_UNONE_UNONE_NONE_NONE_PRED_QUALIFIERS): ... this. + (QUADOP_NONE_NONE_NONE_NONE_PRED_QUALIFIERS): New. + (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Change to ... + (QUADOP_NONE_NONE_NONE_IMM_PRED_QUALIFIERS): ... this. + (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED_QUALIFIERS): New. + (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Change to ... + (QUADOP_UNONE_UNONE_NONE_IMM_PRED_QUALIFIERS): ... this. + (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Change to ... + (QUADOP_NONE_NONE_UNONE_IMM_PRED_QUALIFIERS): ... this. + (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Change to ... + (QUADOP_UNONE_UNONE_UNONE_IMM_PRED_QUALIFIERS): ... this. + (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Change to ... + (QUADOP_UNONE_UNONE_UNONE_NONE_PRED_QUALIFIERS): ... this. + (STRS_P_QUALIFIERS): Use predicate qualifier. + (STRU_P_QUALIFIERS): Likewise. + (STRSU_P_QUALIFIERS): Likewise. + (STRSS_P_QUALIFIERS): Likewise. + (LDRGS_Z_QUALIFIERS): Likewise. + (LDRGU_Z_QUALIFIERS): Likewise. + (LDRS_Z_QUALIFIERS): Likewise. + (LDRU_Z_QUALIFIERS): Likewise. + (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Change to ... + (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED_QUALIFIERS): ... this. + (BINOP_NONE_NONE_PRED_QUALIFIERS): New. + (BINOP_UNONE_UNONE_PRED_QUALIFIERS): New. + * config/arm/arm_mve_builtins.def: Use new predicated qualifiers. + * config/arm/mve.md: Use MVE_VPRED instead of HI. + +2022-02-22 Christophe Lyon <christophe.lyon@arm.com> + + PR target/100757 + PR target/101325 + * config/arm/arm-builtins.cc (BINOP_UNONE_NONE_NONE_QUALIFIERS): + Delete. + (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Change to ... + (TERNOP_PRED_NONE_NONE_PRED_QUALIFIERS): ... this. + (TERNOP_PRED_UNONE_UNONE_PRED_QUALIFIERS): New. + * config/arm/arm_mve_builtins.def (vcmp*q_n_, vcmp*q_m_f): Use new + predicated qualifiers. + * config/arm/mve.md (mve_vcmp<mve_cmp_op>q_n_<mode>) + (mve_vcmp*q_m_f<mode>): Use MVE_VPRED instead of HI. + +2022-02-22 Christophe Lyon <christophe.lyon@arm.com> + + PR target/100757 + * config/arm/arm-protos.h (arm_get_mask_mode): New prototype. + (arm_expand_vector_compare): Update prototype. + * config/arm/arm.cc (TARGET_VECTORIZE_GET_MASK_MODE): New. + (arm_vector_mode_supported_p): Add support for VxBI modes. + (arm_expand_vector_compare): Remove useless generation of vpsel. + (arm_expand_vcond): Fix select operands. + (arm_get_mask_mode): New. + * config/arm/mve.md (vec_cmp<mode><MVE_vpred>): New. + (vec_cmpu<mode><MVE_vpred>): New. + (vcond_mask_<mode><MVE_vpred>): New. + * config/arm/vec-common.md (vec_cmp<mode><v_cmp_result>) + (vec_cmpu<mode><mode, vcond_mask_<mode><v_cmp_result>): Move to ... + * config/arm/neon.md (vec_cmp<mode><v_cmp_result>) + (vec_cmpu<mode><mode, vcond_mask_<mode><v_cmp_result>): ... here + and disable for MVE. + * doc/sourcebuild.texi (arm_mve): Document new effective-target. + +2022-02-22 Christophe Lyon <christophe.lyon@arm.com> + + PR target/100757 + PR target/101325 + * config/arm/arm-builtins.cc (BINOP_PRED_UNONE_UNONE_QUALIFIERS) + (BINOP_PRED_NONE_NONE_QUALIFIERS) + (TERNOP_NONE_NONE_NONE_PRED_QUALIFIERS) + (TERNOP_UNONE_UNONE_UNONE_PRED_QUALIFIERS): New. + * config/arm/arm-protos.h (mve_bool_vec_to_const): New. + * config/arm/arm.cc (arm_hard_regno_mode_ok): Handle new VxBI + modes. + (arm_mode_to_pred_mode): New. + (arm_expand_vector_compare): Use the right VxBI mode instead of + HI. + (arm_expand_vcond): Likewise. + (simd_valid_immediate): Handle MODE_VECTOR_BOOL. + (mve_bool_vec_to_const): New. + (neon_make_constant): Call mve_bool_vec_to_const when needed. + * config/arm/arm_mve_builtins.def (vcmpneq_, vcmphiq_, vcmpcsq_) + (vcmpltq_, vcmpleq_, vcmpgtq_, vcmpgeq_, vcmpeqq_, vcmpneq_f) + (vcmpltq_f, vcmpleq_f, vcmpgtq_f, vcmpgeq_f, vcmpeqq_f, vpselq_u) + (vpselq_s, vpselq_f): Use new predicated qualifiers. + * config/arm/constraints.md (DB): New. + * config/arm/iterators.md (MVE_7, MVE_7_HI): New mode iterators. + (MVE_VPRED, MVE_vpred): New attribute iterators. + * config/arm/mve.md (@mve_vcmp<mve_cmp_op>q_<mode>) + (@mve_vcmp<mve_cmp_op>q_f<mode>, @mve_vpselq_<supf><mode>) + (@mve_vpselq_f<mode>): Use MVE_VPRED instead of HI. + (@mve_vpselq_<supf>v2di): Define separately. + (mov<mode>): New expander for VxBI modes. + * config/arm/vfp.md (thumb2_movhi_vfp, thumb2_movhi_fp16): Use + MVE_7_HI iterator and add support for DB constraint. + +2022-02-22 Christophe Lyon <christophe.lyon@arm.com> + Richard Sandiford <richard.sandiford@arm.com> + + PR target/100757 + PR target/101325 + * config/aarch64/aarch64-modes.def (VNx16BI, VNx8BI, VNx4BI, + VNx2BI): Update definition. + * config/arm/arm-builtins.cc (arm_init_simd_builtin_types): Add new + simd types. + (arm_init_builtin): Map predicate vectors arguments to HImode. + (arm_expand_builtin_args): Move HImode predicate arguments to VxBI + rtx. Move return value to HImode rtx. + * config/arm/arm-builtins.h (arm_type_qualifiers): Add qualifier_predicate. + * config/arm/arm-modes.def (B2I, B4I, V16BI, V8BI, V4BI): New modes. + * config/arm/arm-simd-builtin-types.def (Pred1x16_t, + Pred2x8_t,Pred4x4_t): New. + * emit-rtl.cc (init_emit_once): Handle all boolean modes. + * genmodes.cc (mode_data): Add boolean field. + (blank_mode): Initialize it. + (make_complex_modes): Fix handling of boolean modes. + (make_vector_modes): Likewise. + (VECTOR_BOOL_MODE): Use new COMPONENT parameter. + (make_vector_bool_mode): Likewise. + (BOOL_MODE): New. + (make_bool_mode): New. + (emit_insn_modes_h): Fix generation of boolean modes. + (emit_class_narrowest_mode): Likewise. + * machmode.def: (VECTOR_BOOL_MODE): Document new COMPONENT + parameter. Use new BOOL_MODE instead of FRACTIONAL_INT_MODE to + define BImode. + * rtx-vector-builder.cc (rtx_vector_builder::find_cached_value): + Fix handling of constm1_rtx for VECTOR_BOOL. + * simplify-rtx.cc (native_encode_rtx): Fix support for VECTOR_BOOL. + (native_decode_vector_rtx): Likewise. + (test_vector_ops_duplicate): Skip vec_merge test + with vectors of booleans. + * varasm.cc (output_constant_pool_2): Likewise. + +2022-02-22 Christophe Lyon <christophe.lyon@arm.com> + + * config/arm/mve.md (mve_vmvnq_n_<supf><mode>): Use V_elem mode + for operand 1. + +2022-02-22 Christophe Lyon <christophe.lyon@arm.com> + + * config/arm/arm.cc (arm_class_likely_spilled_p): Handle VPR_REG. + +2022-02-22 Christophe Lyon <christophe.lyon@arm.com> + + * config/arm/arm.h (reg_class): Add GENERAL_AND_VPR_REGS. + (REG_CLASS_NAMES): Likewise. + (REG_CLASS_CONTENTS): Likewise. + (CLASS_MAX_NREGS): Handle VPR. + * config/arm/arm.cc (arm_hard_regno_nregs): Handle VPR. + +2022-02-22 Tobias Burnus <tobias@codesourcery.com> + Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx-c.cc (nvptx_cpu_cpp_builtins): Handle SM70. + * config/nvptx/nvptx.cc (first_ptx_version_supporting_sm): + Likewise. + * config/nvptx/nvptx.opt (misa): Add sm_70 alias PTX_ISA_SM70. + +2022-02-22 Tobias Burnus <tobias@codesourcery.com> + Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx.opt (mptx): Add 6.0 alias PTX_VERSION_6_0. + * doc/invoke.texi (-mptx): Update for new values and defaults. + +2022-02-22 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx.cc (gen_comment): New function. + (workaround_uninit_method_1, workaround_uninit_method_2) + (workaround_uninit_method_3): : Use gen_comment. + * config/nvptx/nvptx.opt (mptx-comment): New option. + +2022-02-22 Richard Biener <rguenther@suse.de> + + * tree-vect-slp.cc (vect_build_slp_tree_2): Dump the def used + for a splat. + +2022-02-22 Roger Sayle <roger@nextmovesoftware.com> + Richard Biener <rguenther@suse.de> + + * fold-const.cc (ctor_single_nonzero_element): New function to + return the single non-zero element of a (vector) constructor. + * fold-const.h (ctor_single_nonzero_element): Prototype here. + * match.pd (reduc (constructor@0)): Simplify reductions of a + constructor containing a single non-zero element. + (reduc (@0 op VECTOR_CST) -> (reduc @0) op CONST): Simplify + reductions of vector operations of the same operator with + constant vector operands. + +2022-02-22 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/104604 + * gimple-range-fold.cc (adjust_imagpart_expr, adjust_realpart_expr): + Only check if gimple_assign_rhs1 is COMPLEX_CST if + gimple_assign_rhs_code is COMPLEX_CST. + +2022-02-22 Jakub Jelinek <jakub@redhat.com> + + PR target/104612 + * config/i386/i386-expand.cc (ix86_expand_copysign): Call force_reg + on input operands before calling lowpart_subreg on it. For output + operand, use a vmode pseudo as destination and then move its lowpart + subreg into operands[0] if lowpart_subreg fails on dest. + (ix86_expand_xorsign): Likewise. + +2022-02-22 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104582 + PR target/99881 + * config/i386/i386.cc (ix86_vector_costs::add_stmt_cost): + Cost GPR to vector register moves for integer vector construction. + +2022-02-22 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104582 + * tree-vectorizer.h (stmt_info_for_cost::node): New field. + (vector_costs::add_stmt_cost): Add SLP node parameter. + (dump_stmt_cost): Likewise. + (add_stmt_cost): Likewise, new overload and adjust. + (add_stmt_costs): Adjust. + (record_stmt_cost): New overload. + * tree-vectorizer.cc (dump_stmt_cost): Dump the SLP node. + (vector_costs::add_stmt_cost): Adjust. + * tree-vect-loop.cc (vect_estimate_min_profitable_iters): + Adjust. + * tree-vect-slp.cc (vect_prologue_cost_for_slp): Record + the SLP node for costing. + (vectorizable_slp_permutation): Likewise. + * tree-vect-stmts.cc (record_stmt_cost): Adjust and add + new overloads. + * config/i386/i386.cc (ix86_vector_costs::add_stmt_cost): + Adjust. + * config/aarch64/aarch64.cc (aarch64_vector_costs::add_stmt_cost): + Adjust. + * config/rs6000/rs6000.cc (rs6000_vector_costs::add_stmt_cost): + Adjust. + (rs6000_cost_data::adjust_vect_cost_per_loop): Likewise. + +2022-02-22 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104582 + * tree-vectorizer.h (add_stmt_cost): New overload. + (record_stmt_cost): Likewise. + * tree-vect-loop.cc (vect_compute_single_scalar_iteration_cost): + Use add_stmt_costs. + (vect_get_known_peeling_cost): Use new overloads. + (vect_estimate_min_profitable_iters): Likewise. Consistently + use scalar_stmt for costing versioning checks. + * tree-vect-stmts.cc (record_stmt_cost): New overload. + +2022-02-22 Hongyu Wang <hongyu.wang@intel.com> + + PR target/103069 + * config/i386/i386-expand.cc (ix86_expand_atomic_fetch_op_loop): + Split atomic fetch and loop part. + (ix86_expand_cmpxchg_loop): New expander for cmpxchg loop. + * config/i386/i386-protos.h (ix86_expand_cmpxchg_loop): New + prototype. + * config/i386/sync.md (atomic_compare_and_swap<mode>): Call new + expander under TARGET_RELAX_CMPXCHG_LOOP. + (atomic_compare_and_swap<mode>): Likewise for doubleword modes. + +2022-02-21 Dan Li <ashimida@linux.alibaba.com> + + * config/aarch64/aarch64.cc (SLOT_REQUIRED): + Change wb_candidate[12] to wb_push_candidate[12]. + (aarch64_layout_frame): Likewise, and + change callee_adjust when scs is enabled. + (aarch64_save_callee_saves): + Change wb_candidate[12] to wb_push_candidate[12]. + (aarch64_restore_callee_saves): + Change wb_candidate[12] to wb_pop_candidate[12]. + (aarch64_get_separate_components): + Change wb_candidate[12] to wb_push_candidate[12]. + (aarch64_expand_prologue): Push x30 onto SCS before it's + pushed onto stack. + (aarch64_expand_epilogue): Pop x30 frome SCS, while + preventing it from being popped from the regular stack again. + (aarch64_override_options_internal): Add SCS compile option check. + (TARGET_HAVE_SHADOW_CALL_STACK): New hook. + * config/aarch64/aarch64.h (struct GTY): Add is_scs_enabled, + wb_pop_candidate[12], and rename wb_candidate[12] to + wb_push_candidate[12]. + * config/aarch64/aarch64.md (scs_push): New template. + (scs_pop): Likewise. + * doc/invoke.texi: Document -fsanitize=shadow-call-stack. + * doc/tm.texi: Regenerate. + * doc/tm.texi.in: Add hook have_shadow_call_stack. + * flag-types.h (enum sanitize_code): + Add SANITIZE_SHADOW_CALL_STACK. + * opts.cc (parse_sanitizer_options): Add shadow-call-stack + and exclude SANITIZE_SHADOW_CALL_STACK. + * target.def: New hook. + * toplev.cc (process_options): Add SCS compile option check. + * ubsan.cc (ubsan_expand_null_ifn): Enum type conversion. + +2022-02-21 Tom de Vries <tdevries@suse.de> + + PR target/104440 + * config/nvptx/nvptx.cc (workaround_uninit_method_1) + (workaround_uninit_method_2, workaround_uninit_method_3) + (workaround_uninit): New function. + (nvptx_reorg): Use workaround_uninit. + * config/nvptx/nvptx.opt (minit-regs): New option. + +2022-02-21 Andre Vieira <andre.simoesdiasvieira@arm.com> + + PR rtl-optimization/104498 + * alias.cc (compare_base_symbol_refs): Correct distance computation + when swapping x and y. + +2022-02-21 Andrew Pinski <apinski@marvell.com> + + PR c/104506 + * tree-ssa.cc (tree_ssa_useless_type_conversion): + Check the inner type before calling useless_type_conversion_p. + +2022-02-19 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx.cc (nvptx_reorg_uniform_simt): Handle SET insn. + * config/nvptx/nvptx.md + (define_insn "nvptx_atomic_store<mode>"): Rename to ... + (define_insn "nvptx_atomic_store_sm70<mode>"): This. + (define_insn "nvptx_atomic_store<mode>"): New define_insn. + (define_expand "atomic_store<mode>"): Handle rename. Use + nvptx_atomic_store instead of atomic_exchange. + +2022-02-19 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx.cc (nvptx_reorg_uniform_simt): Handle all + insns with atomic attribute. Assert that all handled insns are + PARALLELs. + * config/nvptx/nvptx.md (define_insn "nvptx_atomic_store<mode>"): + Set atomic attribute to false. + +2022-02-19 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx.cc (nvptx_unisimt_handle_set): Change return + type to bool. + (nvptx_reorg_uniform_simt): Insert nvptx_uniform_warp_check or + nvptx_warpsync, if necessary. + +2022-02-19 Jakub Jelinek <jakub@redhat.com> + + PR sanitizer/102656 + * asan.cc (instrument_derefs): If inner is a RESULT_DECL and access is + known to be within bounds, treat it like automatic variables. + If instrumenting access and inner is {VAR,PARM,RESULT}_DECL from + current function and !TREE_STATIC which is not TREE_ADDRESSABLE, mark + it addressable. + +2022-02-18 Pat Haugen <pthaugen@linux.ibm.com> + + * config/rs6000/rs6000.opt (mpower10-fusion): Mark Undocumented. + (mpower10-fusion-ld-cmpi, mpower10-fusion-2logical, + mpower10-fusion-logical-add, mpower10-fusion-add-logical, + mpower10-fusion-2add, mpower10-fusion-2store): Remove. + * config/rs6000/rs6000-cpus.def (ISA_3_1_MASKS_SERVER, + OTHER_P9_VECTOR_MASKS): Remove Power10 fusion sub-options. + * config/rs6000/rs6000.cc (rs6000_option_override_internal, + power10_sched_reorder): Likewise. + * config/rs6000/genfusion.pl (gen_ld_cmpi_p10, gen_logical_addsubf, + gen_addadd): Likewise + * config/rs6000/fusion.md: Regenerate. + +2022-02-18 Jakub Jelinek <jakub@redhat.com> + + PR target/104257 + PR target/104598 + * config/rs6000/mm_malloc.h (_mm_malloc): Call posix_memalign + rather than __posix_memalign. + +2022-02-18 Richard Biener <rguenther@suse.de> + + PR target/104581 + * config/i386/i386.cc (ix86_avx_u128_mode_source): Remove. + (ix86_avx_u128_mode_needed): Return AVX_U128_DIRTY instead + of calling ix86_avx_u128_mode_source which would eventually + have returned AVX_U128_ANY in some very special case. + +2022-02-18 Richard Biener <rguenther@suse.de> + + PR tree-optimization/96881 + * tree-ssa-dce.cc (mark_stmt_if_obviously_necessary): Comment + CLOBBER handling. + (control_parents_preserved_p): New function. + (eliminate_unnecessary_stmts): Check that we preserved control + parents before retaining a CLOBBER. + (perform_tree_ssa_dce): Pass down aggressive flag + to eliminate_unnecessary_stmts. + +2022-02-17 Jason Merrill <jason@redhat.com> + + * tree.cc (warn_deprecated_use): Look for TYPE_STUB_DECL + on TYPE_MAIN_VARIANT. + +2022-02-17 Paul A. Clarke <pc@us.ibm.com> + + PR target/104257 + * config/rs6000/bmi2intrin.h: Uglify local variables. + * config/rs6000/emmintrin.h: Likewise. + * config/rs6000/mm_malloc.h: Likewise. + * config/rs6000/mmintrin.h: Likewise. + * config/rs6000/pmmintrin.h: Likewise. + * config/rs6000/smmintrin.h: Likewise. + * config/rs6000/tmmintrin.h: Likewise. + * config/rs6000/xmmintrin.h: Likewise. + +2022-02-17 Robin Dapp <rdapp@linux.ibm.com> + + PR target/104335 + * config/rs6000/rs6000.cc (rs6000_emit_int_cmove): Return false + if the expected comparison's first operand is of mode MODE_CC. + +2022-02-17 Vladimir N. Makarov <vmakarov@redhat.com> + + PR rtl-optimization/104447 + * lra-constraints.cc (spill_hard_reg_in_range): Initiate ignore + hard reg set by lra_no_alloc_regs. + +2022-02-17 liuhongt <hongtao.liu@intel.com> + + PR tree-optimization/104551 + PR tree-optimization/103771 + * match.pd (cond_expr_convert_p): Add types_match check when + convert is extension. + * tree-vect-patterns.cc + (gimple_cond_expr_convert_p): Adjust comments. + (vect_recog_cond_expr_convert_pattern): Ditto. + +2022-02-17 Jakub Jelinek <jakub@redhat.com> + + PR debug/104557 + * valtrack.cc (debug_lowpart_subreg): Don't call gen_rtx_raw_SUBREG + if expr has VOIDmode. + +2022-02-17 liuhongt <hongtao.liu@intel.com> + + * config/i386/cpuid.h (bit_MPX): Removed. + (bit_BNDREGS): Ditto. + (bit_BNDCSR): Ditto. + +2022-02-17 Michael Meissner <meissner@the-meissners.org> + + PR target/99708 + * config/rs6000/rs6000-c.cc (rs6000_cpu_cpp_builtins): Define + __SIZEOF_IBM128__ if the IBM 128-bit long double type is created. + Define __SIZEOF_FLOAT128__ if the IEEE 128-bit floating point type + is created. + +2022-02-16 Andrew MacLeod <amacleod@redhat.com> + + * gimple-range-gori.cc (gori_compute::condexpr_adjust): Use + range_compatible_p instead of direct type comparison. + +2022-02-16 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/104544 + * combine.cc (try_combine): When looking for insn whose links + should be updated from i3 to i2, don't stop on debug insns, instead + skip over them. + +2022-02-16 Richard Sandiford <richard.sandiford@arm.com> + + PR target/100056 + * config/aarch64/iterators.md (LOGICAL_OR_PLUS): New iterator. + * config/aarch64/aarch64.md: Extend the PR100056 patterns + to handle plus in the same way as ior, if the operands have + no set bits in common. + +2022-02-15 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/104526 + * gimple-range-fold.cc (fold_using_range::range_of_cond_expr): Call + new routine. + * gimple-range-gori.cc (range_def_chain::get_def_chain): Force a build + of dependency chain if there isn't one. + (gori_compute::condexpr_adjust): New. + * gimple-range-gori.h (class gori_compute): New prototype. + +2022-02-15 Richard Sandiford <richard.sandiford@arm.com> + + PR target/100874 + * config/aarch64/aarch64-protos.h (aarch64_maxmin_plus_const): + Declare. + * config/aarch64/aarch64.cc (aarch64_maxmin_plus_const): New function. + * config/aarch64/aarch64.md (*aarch64_minmax_plus): New pattern. + +2022-02-15 Richard Sandiford <richard.sandiford@arm.com> + + * tree-vectorizer.h (vect_scalar_ops_slice): New struct. + (vect_scalar_ops_slice_hash): Likewise. + (vect_scalar_ops_slice::op): New function. + * tree-vect-slp.cc (vect_scalar_ops_slice::all_same_p): New function. + (vect_scalar_ops_slice_hash::hash): Likewise. + (vect_scalar_ops_slice_hash::equal): Likewise. + (vect_prologue_cost_for_slp): Check for duplicate vectors. + * config/aarch64/aarch64.cc + (aarch64_vector_costs::m_stp_sequence_cost): New member variable. + (aarch64_aligned_constant_offset_p): New function. + (aarch64_stp_sequence_cost): Likewise. + (aarch64_vector_costs::add_stmt_cost): Handle new STP heuristic. + (aarch64_vector_costs::finish_cost): Likewise. + +2022-02-15 Richard Sandiford <richard.sandiford@arm.com> + + * tree-vect-slp.cc (vect_bb_vectorization_profitable_p): Fix + use after free. + +2022-02-15 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104543 + * gimple-loop-jam.cc (unroll_jam_possible_p): Check outer loop exits + come after the inner loop. + +2022-02-15 Jakub Jelinek <jakub@redhat.com> + + PR target/104536 + * config/i386/host-cygwin.cc (cygwin_gt_pch_get_address): Use + cannot instead of can%'t in diagnostics. Formatting fixes. + +2022-02-15 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/104522 + * fold-const.h (native_interpret_real): Declare. + * fold-const.cc (native_interpret_real): No longer static. Don't + perform MODE_COMPOSITE_P verification here. + (native_interpret_expr) <case REAL_TYPE>: But perform it here instead + for all modes. + * gimple-fold.cc (clear_padding_type): Call native_interpret_real + instead of native_interpret_expr. + * simplify-rtx.cc (simplify_immed_subreg): Perform the native_encode_rtx + and comparison verification for all FLOAT_MODE_P modes, not just + MODE_COMPOSITE_P. + +2022-02-15 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104519 + * fold-const.cc (multiple_of_p): Remove never true condition. + * tree-ssa-loop-niter.cc (number_of_iterations_ne): Use + the appropriate types for determining whether the difference + of final and base is a multiple of the step. + +2022-02-15 Jakub Jelinek <jakub@redhat.com> + + PR debug/104517 + * omp-low.cc (task_cpyfns): New variable. + (delete_omp_context): Don't call finalize_task_copyfn from here. + (create_task_copyfn): Push task_stmt into task_cpyfns. + (execute_lower_omp): Call finalize_task_copyfn here on entries from + task_cpyfns vector and release the vector. + +2022-02-14 Martin Sebor <msebor@redhat.com> + + PR middle-end/104355 + * doc/invoke.texi (-Warray-bounds): Update documentation. + +2022-02-14 Michael Meissner <meissner@the-meissners.org> + + PR target/104253 + * config/rs6000/rs6000.cc (init_float128_ibm): Update the + conversion functions used to convert IFmode types. + +2022-02-14 Andrew Stubbs <ams@codesourcery.com> + + * config/gcn/gcn.cc (gcn_expand_reduc_scalar): Use force_reg. + +2022-02-14 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104528 + * tree-ssa.h (find_released_ssa_name): Declare. + * tree-ssa.cc (find_released_ssa_name): Export. + * cfgloop.cc (verify_loop_structure): Look for released + SSA names in loops nb_iterations. + * tree-ssa-dse.cc (pass_dse::execute): Release number of iteration + estimates. + +2022-02-14 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104511 + * tree-ssa-forwprop.cc (simplify_vector_constructor): Avoid + touching DFP <-> FP conversions. + +2022-02-14 Richard Biener <rguenther@suse.de> + + PR middle-end/104497 + * gimplify.cc (gimplify_compound_lval): Make sure the + base is a non-register if needed and possible. + +2022-02-13 liuhongt <hongtao.liu@intel.com> + + PR target/103771 + * match.pd (cond_expr_convert_p): New match. + * tree-vect-patterns.cc (gimple_cond_expr_convert_p): Declare. + (vect_recog_cond_expr_convert_pattern): New. + +2022-02-12 Jakub Jelinek <jakub@redhat.com> + + PR sanitizer/104449 + * asan.cc: Include tree-eh.h. + (handle_builtin_alloca): Handle the case when __builtin_alloca or + __builtin_alloca_with_align can throw. + +2022-02-12 Jakub Jelinek <jakub@redhat.com> + + PR target/104502 + * config/i386/i386.md (cvtsd2ss splitter): If operands[1] is xmm16+ + and AVX512VL isn't available, move operands[1] to operands[0] first. + +2022-02-12 Uroš Bizjak <ubizjak@gmail.com> + + PR target/79754 + * config/i386/i386.cc (type_natural_mode): + Skip decimal float vector modes. + +2022-02-11 Iain Sandoe <iain@sandoe.co.uk> + Vladimir Makarov <vmakarov@redhat.com> + + PR target/104117 + * config/rs6000/rs6000.cc (darwin_rs6000_legitimate_lo_sum_const_p): + Check for UNSPEC_MACHOPIC_OFFSET wrappers on symbolic addresses when + emitting PIC code. + (legitimate_lo_sum_address_p): Likewise. + * lra-constraints.cc (process_address_1): Do not attempt to emit a reg + load from an invalid lo_sum address. + +2022-02-11 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/104499 + * match.pd ((X & Y) CMP 0 -> X CMP2 ~Y): Use view_convert instead + of convert. + +2022-02-11 Jakub Jelinek <jakub@redhat.com> + + * tree.cc (build_common_builtin_nodes): Fix up formatting in + __builtin_clear_padding decl creation. + * gimplify.cc (gimple_add_padding_init_for_auto_var): Encode + for_auto_init in the value of 2nd BUILT_IN_CLEAR_PADDING + argument rather than in 3rd argument. + (gimplify_call_expr): Likewise. Fix up comment formatting. + * gimple-fold.cc (gimple_fold_builtin_clear_padding): Expect + 2 arguments instead of 3, take for_auto_init from the value + of 2nd argument. + +2022-02-11 Vladimir N. Makarov <vmakarov@redhat.com> + + PR rtl-optimization/104400 + * lra-constraints.cc (process_alt_operands): Don't make union of + this_alternative_exclude_start_hard_regs when reg class in insn + alternative covers other reg classes in the same alternative. + +2022-02-11 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/104446 + * combine.cc (subst): Don't substitute CONST_INTs into RTX_AUTOINC + operands. + +2022-02-11 Richard Biener <rguenther@suse.de> + + PR middle-end/104496 + * internal-fn.cc (vectorized_internal_fn_supported_p): + Bail out for integer mode vector types. + +2022-02-11 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/104459 + * df-scan.cc (df_insn_change_bb): Don't call df_set_bb_dirty when + moving DEBUG_INSNs between bbs. + +2022-02-11 liuhongt <hongtao.liu@intel.com> + + PR tree-optimization/104479 + * match.pd (uncond_op + vec_cond -> cond_op): Add single_use + for the dest of uncond_op. + +2022-02-11 Tom de Vries <tdevries@suse.de> + + PR target/104456 + * config/nvptx/nvptx.cc (prevent_branch_around_nothing): Handle asm + insn. + +2022-02-10 Qing Zhao <qing.zhao@oracle.com> + + PR middle-end/100775 + * function.cc (gen_call_used_regs_seq): Call + df_update_exit_block_uses when updating df. + +2022-02-10 Uroš Bizjak <ubizjak@gmail.com> + + PR target/104469 + * config/i386/sse.md (vec_unpacks_float_lo_v4si): + Change operand 1 constraint to register_operand. + +2022-02-10 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104373 + * tree-ssa-sccvn.h (do_rpo_vn): New export exposing the + walk kind. + * tree-ssa-sccvn.cc (do_rpo_vn): Export, get the default + walk kind as argument. + (run_rpo_vn): Adjust. + (pass_fre::execute): Likewise. + * tree-ssa-uninit.cc (warn_uninitialized_vars): Skip + blocks not reachable. + (execute_late_warn_uninitialized): Mark all edges as + executable. + (execute_early_warn_uninitialized): Use VN to compute + executable edges. + (pass_data_early_warn_uninitialized): Enable a dump file, + change dump name to warn_uninit. + +2022-02-10 Richard Biener <rguenther@suse.de> + + PR middle-end/104467 + * match.pd (vector extract simplification): Multiply the + number of CTOR elements with the number of element elements. + +2022-02-10 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104466 + * tree-ssa-alias.cc (refs_may_alias_p_2): Use rbase1/rbase2 + for the MR_DEPENDENCE checks as intended. + +2022-02-10 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx.md (define_insn "nvptx_atomic_store<mode>"): New + define_insn. + (define_expand "atomic_store<mode>"): Use nvptx_atomic_store<mode> for + TARGET_SM70. + (define_c_enum "unspecv"): Add UNSPECV_ST. + +2022-02-10 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx-protos.h (nvptx_mem_maybe_shared_p): Declare. + * config/nvptx/nvptx.cc (nvptx_mem_data_area): New static function. + (nvptx_mem_maybe_shared_p): New function. + * config/nvptx/nvptx.md (define_expand "atomic_store<mode>"): New + define_expand. + +2022-02-10 Tom de Vries <tdevries@suse.de> + + PR target/97005 + * config/nvptx/nvptx.md (define_insn "sub<mode>3"): Workaround + driver JIT bug by using sub.s16 instead of sub.u16. + +2022-02-10 Roger Sayle <roger@nextmovesoftware.com> + + * config/nvptx/nvptx.md (copysign<mode>3): Allow immediate + floating point constants as operands 1 and/or 2. + +2022-02-10 Roger Sayle <roger@nextmovesoftware.com> + + PR target/104345 + * config/nvptx/nvptx.md (sel_true<mode>): Fix indentation. + (sel_false<mode>): Likewise. + (define_code_iterator eqne): New code iterator for EQ and NE. + (*selp<mode>_neg_<code>): New define_insn_and_split to optimize + the negation of a selp instruction. + (*selp<mode>_not_<code>): New define_insn_and_split to optimize + the bitwise not of a selp instruction. + (*setcc_int<mode>): Use set instruction for neg:SI of a selp. + +2022-02-10 Roger Sayle <roger@nextmovesoftware.com> + + * config/nvptx/nvptx.md (any_logic): Move code iterator earlier + in machine description. + (logic): Move code attribute earlier in machine description. + (ilogic): New code attribute, like logic but "ior" for IOR. + (and<mode>3, ior<mode>3, xor<mode>3): Delete. Replace with... + (<ilogic><mode>3): New define_insn for HSDIM logic operations. + (<ilogic>bi3): New define_insn for BI mode logic operations. + (define_split): Lower logic operations from integer modes to + BI mode predicate operations. + +2022-02-10 Roger Sayle <roger@nextmovesoftware.com> + + * config/nvptx/nvptx.md (UNSPEC_ISINF): New UNSPEC. + (one_cmplbi2): New define_insn for not.pred. + (mulditi3): New define_expand for signed widening multiply. + (umulditi3): New define_expand for unsigned widening multiply. + (smul<mode>3_highpart): New define_insn for signed highpart mult. + (umul<mode>3_highpart): New define_insn for unsigned highpart mult. + (*smulhi3_highpart_2): Renamed from smulhi3_highpart. + (*smulsi3_highpart_2): Renamed from smulsi3_highpart. + (*umulhi3_highpart_2): Renamed from umulhi3_highpart. + (*umulsi3_highpart_2): Renamed from umulsi3_highpart. + (*setcc<mode>_from_not_bi): New define_insn. + (*setcc_isinf<mode>): New define_insn for testp.infinite. + (isinf<mode>2): New define_expand. + +2022-02-10 Roger Sayle <roger@nextmovesoftware.com> + + * config/nvptx/nvptx.md (cmp<mode>): Renamed from *cmp<mode>. + (setcc<mode>_from_bi): Additionally support QImode. + (extendbi<mode>2): Additionally support QImode. + (zero_extendbi<mode>2): Additionally support QImode. + (any_sbinary, any_ubinary, any_sunary, any_uunary): New code + iterators for signed and unsigned, binary and unary operations. + (<sbinary>qi3, <ubinary>qi3, <sunary>qi2, <uunary>qi2): New + expanders to perform QImode operations using SImode instructions. + (cstoreqi4): New define_expand. + (*ext_truncsi2_qi): New define_insn. + (*zext_truncsi2_qi): New define_insn. + +2022-02-10 Roger Sayle <roger@nextmovesoftware.com> + + * config/nvptx/nvptx.md (*cmpf): New define_insn. + (cstorehf4): New define_expand. + (fmahf4): New define_insn. + (neghf2): New define_insn. + (abshf2): New define_insn. + +2022-02-10 Gerald Pfeifer <gerald@pfeifer.com> + + * doc/install.texi (Specific): Change the www.bitwizard.nl + reference to use https. + +2022-02-10 Marcel Vollweiler <marcel@codesourcery.com> + + * gimplify.cc (gimplify_scan_omp_clauses): Added cases for + OMP_CLAUSE_HAS_DEVICE_ADDR + and handle array sections. + (gimplify_adjust_omp_clauses): Added OMP_CLAUSE_HAS_DEVICE_ADDR case. + * omp-low.cc (scan_sharing_clauses): Handle OMP_CLAUSE_HAS_DEVICE_ADDR. + (lower_omp_target): Same. + * tree-core.h (enum omp_clause_code): Same. + * tree-nested.cc (convert_nonlocal_omp_clauses): Same. + (convert_local_omp_clauses): Same. + * tree-pretty-print.cc (dump_omp_clause): Same. + * tree.cc: Same. + +2022-02-10 Eugene Rozenfeld <erozen@microsoft.com> + + * auto-profile.cc (afdo_indirect_call): Don't attempt to promote indirect calls + that will result in direct recursive calls. + +2022-02-10 Andrew Pinski <apinski@marvell.com> + + PR target/104474 + * config/aarch64/aarch64.cc + (aarch64_sve_expand_vector_init_handle_trailing_constants): + Use CONST0_RTX instead of const0_rtx for the non-constant elements. + +2022-02-09 Uroš Bizjak <ubizjak@gmail.com> + + PR target/104462 + * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_XSAVE_UNSET): + Also include OPTION_MASK_ISA2_AVX2_UNSET. + +2022-02-09 Uroš Bizjak <ubizjak@gmail.com> + + PR target/104458 + * config/i386/i386-expand.cc (ix86_split_idivmod): + Force operands[2] and operands[3] into a register.. + +2022-02-09 Jeff Law <jeffreyalaw@gmail.com> + + PR target/97040 + * config/v850/v850.md (*v850_fnmasf4): Renamed from fnmasf4. + (*v850_fnmssf4): Renamed from fnmssf4 + +2022-02-09 Ian Lance Taylor <iant@golang.org> + + * godump.cc (go_force_record_alignment): Really name the alignment + field "_" (complete 2021-12-29 change). + +2022-02-09 Bill Schmidt <wschmidt@linux.ibm.com> + + * config/rs6000/rs6000-builtins.def (VREPLACE_UN_UV2DI): Change + function prototype. + (VREPLACE_UN_UV4SI): Likewise. + (VREPLACE_UN_V2DF): Likewise. + (VREPLACE_UN_V2DI): Likewise. + (VREPLACE_UN_V4SF): Likewise. + (VREPLACE_UN_V4SI): Likewise. + * config/rs6000/rs6000-overload.def (VEC_REPLACE_UN): Change all + function prototypes. + * config/rs6000/vsx.md (vreplace_un_<mode>): Remove define_expand. + (vreplace_un_<mode>): New define_insn. + +2022-02-09 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/iterators.md (VDCSIF): New mode iterator. + (VDBL): Handle SF. + (single_wx, single_type, single_dtype, dblq): New mode attributes. + * config/aarch64/aarch64-simd.md (load_pair_lanes<mode>): Extend + from VDC to VDCSIF. + (store_pair_lanes<mode>): Likewise. + (*aarch64_combine_internal<mode>): Likewise. + (*aarch64_combine_internal_be<mode>): Likewise. + (*aarch64_combinez<mode>): Likewise. + (*aarch64_combinez_be<mode>): Likewise. + * config/aarch64/aarch64.cc (aarch64_classify_address): Handle + 8-byte modes for ADDR_QUERY_LDP_STP_N. + (aarch64_print_operand): Likewise for %y. + +2022-02-09 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-simd.md (@aarch64_split_simd_mov<mode>): + Use aarch64_combine instead of move_lo/hi_quad. Tabify. + (move_lo_quad_<mode>, aarch64_simd_move_hi_quad_<mode>): Delete. + (aarch64_simd_move_hi_quad_be_<mode>, move_hi_quad_<mode>): Delete. + (vec_pack_trunc_<mode>): Take general_operand elements and use + aarch64_combine rather than move_lo/hi_quad to combine them. + (vec_pack_trunc_df): Likewise. + +2022-02-09 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-protos.h (aarch64_split_simd_combine): + Delete. + * config/aarch64/aarch64-simd.md (@aarch64_combinez<mode>): Rename + to... + (*aarch64_combinez<mode>): ...this. + (@aarch64_combinez_be<mode>): Rename to... + (*aarch64_combinez_be<mode>): ...this. + (@aarch64_vec_concat<mode>): New expander. + (aarch64_combine<mode>): Use it. + (@aarch64_simd_combine<mode>): Delete. + * config/aarch64/aarch64.cc (aarch64_split_simd_combine): Delete. + (aarch64_expand_vector_init): Use aarch64_vec_concat. + +2022-02-09 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/predicates.md (aarch64_reg_or_mem_pair_operand): + New predicate. + * config/aarch64/aarch64-simd.md (*aarch64_combine_internal<mode>) + (*aarch64_combine_internal_be<mode>): New patterns. + +2022-02-09 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-simd.md (move_lo_quad_internal_<mode>) + (move_lo_quad_internal_be_<mode>): Delete. + (move_lo_quad_<mode>): Use aarch64_combine<Vhalf> instead of the above. + +2022-02-09 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-protos.h (aarch64_mergeable_load_pair_p): + Declare. + * config/aarch64/aarch64-simd.md (load_pair_lanes<mode>): Use + aarch64_mergeable_load_pair_p instead of inline check. + * config/aarch64/aarch64.cc (aarch64_expand_vector_init): Likewise. + (aarch64_check_consecutive_mems): Allow the reversed parameter + to be null. + (aarch64_mergeable_load_pair_p): New function. + +2022-02-09 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-simd.md (vec_set<mode>): Allow the + element to be an aarch64_simd_nonimmediate_operand. + +2022-02-09 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-simd.md (aarch64_simd_vec_set<mode>): Use + aarch64_simd_nonimmediate_operand instead of + aarch64_simd_general_operand. + (@aarch64_combinez<mode>): Use nonimmediate_operand instead of + general_operand. + (@aarch64_combinez_be<mode>): Likewise. + +2022-02-09 Richard Biener <rguenther@suse.de> + + PR middle-end/104464 + * gimple-isel.cc (gimple_expand_vec_cond_expr): Postpone + throwing check to after unproblematic replacement. + +2022-02-09 Roger Sayle <roger@nextmovesoftware.com> + + PR tree-optimization/104420 + * match.pd (mult @0 real_zerop): Tweak conditions for constant + folding X*0.0 (or X*-0.0) to HONOR_SIGNED_ZEROS when appropriate. + +2022-02-09 Jakub Jelinek <jakub@redhat.com> + + PR debug/104407 + * dwarf2out.cc (mangle_referenced_decls): New function. + (tree_add_const_value_attribute): Don't call rtl_for_decl_init if + early_dwarf. Instead walk the initializer and try to mangle vars or + functions referenced from it. + +2022-02-09 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/104288 + * gimple-range-cache.cc (non_null_ref::set_nonnull): New. + (non_null_ref::adjust_range): Move to header. + (ranger_cache::range_of_def): Don't check non-null. + (ranger_cache::entry_range): Don't check non-null. + (ranger_cache::range_on_edge): Check for nonnull on normal edges. + (ranger_cache::update_to_nonnull): New. + (non_null_loadstore): New. + (ranger_cache::block_apply_nonnull): New. + * gimple-range-cache.h (class non_null_ref): Update prototypes. + (non_null_ref::adjust_range): Move to here and inline. + (class ranger_cache): Update prototypes. + * gimple-range-path.cc (path_range_query::range_defined_in_block): Do + not search dominators. + (path_range_query::adjust_for_non_null_uses): Ditto. + * gimple-range.cc (gimple_ranger::range_of_expr): Check on-entry for + def overrides. Do not check nonnull. + (gimple_ranger::range_on_entry): Check dominators for nonnull. + (gimple_ranger::range_on_edge): Check for nonnull on normal edges.. + (gimple_ranger::register_side_effects): New. + * gimple-range.h (gimple_ranger::register_side_effects): New. + * tree-vrp.cc (rvrp_folder::fold_stmt): Call register_side_effects. + +2022-02-09 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104445 + PR tree-optimization/102832 + * optabs-query.h (can_vec_extract): New. + * optabs-query.cc (can_vec_extract): Likewise. + * tree-vect-loop.cc (vect_find_reusable_accumulator): Check + we can extract a hi/lo part from the larger vector, rework + check iteration from larger to smaller sizes. + +2022-02-09 H.J. Lu <hjl.tools@gmail.com> + + PR target/35513 + PR target/100593 + * config/i386/gnu-property.cc: Include "i386-protos.h". + (file_end_indicate_exec_stack_and_gnu_property): Generate + a GNU_PROPERTY_1_NEEDED note for -mno-direct-extern-access or + nodirect_extern_access attribute. + * config/i386/i386-options.cc + (handle_nodirect_extern_access_attribute): New function. + (ix86_attribute_table): Add nodirect_extern_access attribute. + * config/i386/i386-protos.h (ix86_force_load_from_GOT_p): Add a + bool argument. + (ix86_has_no_direct_extern_access): New. + * config/i386/i386.cc (ix86_has_no_direct_extern_access): New. + (ix86_force_load_from_GOT_p): Add a bool argument to indicate + call operand. Force non-call load from GOT for + -mno-direct-extern-access or nodirect_extern_access attribute. + (legitimate_pic_address_disp_p): Avoid copy relocation in PIE + for -mno-direct-extern-access or nodirect_extern_access attribute. + (ix86_print_operand): Pass true to ix86_force_load_from_GOT_p + for call operand. + (asm_preferred_eh_data_format): Use PC-relative format for + -mno-direct-extern-access to avoid copy relocation. Check + ptr_mode instead of TARGET_64BIT when selecting DW_EH_PE_sdata4. + (ix86_binds_local_p): Set ix86_has_no_direct_extern_access to + true for -mno-direct-extern-access or nodirect_extern_access + attribute. Don't treat protected data as extern and avoid copy + relocation on common symbol with -mno-direct-extern-access or + nodirect_extern_access attribute. + (ix86_reloc_rw_mask): New to avoid copy relocation for + -mno-direct-extern-access. + (TARGET_ASM_RELOC_RW_MASK): New. + * config/i386/i386.opt: Add -mdirect-extern-access. + * doc/extend.texi: Document nodirect_extern_access attribute. + * doc/invoke.texi: Document -m[no-]direct-extern-access. + +2022-02-09 H.J. Lu <hjl.tools@gmail.com> + + PR target/104441 + * config/i386/i386.cc (ix86_avx_u128_mode_source): New function. + (ix86_avx_u128_mode_needed): Return AVX_U128_ANY for debug INSN. + Call ix86_avx_u128_mode_source to check mode for each component + of source operand. + +2022-02-09 liuhongt <hongtao.liu@intel.com> + + PR target/104451 + * config/i386/sse.md (<insn><mode>3): lowpart_subreg + operands[2] from SImode to QImode. + +2022-02-09 Richard Biener <rguenther@suse.de> + + PR middle-end/104450 + * gimple-isel.cc: Pass cfun around. + (+gimple_expand_vec_cond_expr): Do not combine a throwing + comparison with the select. + +2022-02-09 Richard Biener <rguenther@suse.de> + + PR target/104453 + * config/i386/i386.cc (ix86_gimple_fold_builtin): Guard shift + folding for NULL LHS. + +2022-02-08 Robin Dapp <rdapp@linux.ibm.com> + + PR rtl-optimization/104198 + PR rtl-optimization/104153 + * ifcvt.cc (noce_convert_multiple_sets_1): Copy rtx instead of + using it directly. Rework comparison handling and always + perform a second pass. + +2022-02-08 Jakub Jelinek <jakub@redhat.com> + + PR target/102140 + * config/rs6000/rs6000.cc (vspltis_shifted): Return false also if + split1 pass has finished already. + +2022-02-08 Bill Schmidt <wschmidt@linux.ibm.com> + + * config/rs6000/rs6000-builtins.def (VMSUMCUD): New. + * config/rs6000/rs6000-overload.def (VEC_MSUMC): New. + * config/rs6000/vsx.md (UNSPEC_VMSUMCUD): New constant. + (vmsumcud): New define_insn. + +2022-02-08 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx-opts.h (enum ptx_isa): Add PTX_ISA_SM70. + * config/nvptx/nvptx.h (TARGET_SM70): Define. + +2022-02-08 Robin Dapp <rdapp@linux.ibm.com> + + * config/s390/s390.cc (s390_rtx_costs): Increase costs for load + on condition. + * config/s390/s390.md: Use paradoxical subreg. + +2022-02-08 Robin Dapp <rdapp@linux.ibm.com> + + * combine.cc (reg_subword_p): Check for paradoxical subreg. + +2022-02-08 Tom de Vries <tdevries@suse.de> + + PR target/104283 + * config/nvptx/nvptx-opts.h (enum ptx_version): Add PTX_VERSION_3_0 + and PTX_VERSION_4_2. + * config/nvptx/nvptx.cc (first_ptx_version_supporting_sm) + (default_ptx_version_option, ptx_version_to_string) + (sm_version_to_string, handle_ptx_version_option): New function. + (nvptx_option_override): Call handle_ptx_version_option. + (nvptx_file_start): Use ptx_version_to_string and sm_version_to_string. + * config/nvptx/nvptx.md (define_insn "nvptx_shuffle<mode>") + (define_insn "nvptx_vote_ballot"): Use TARGET_PTX_6_0. + * config/nvptx/nvptx.opt (mptx): Remove 'Init'. + +2022-02-08 Maciej W. Rozycki <macro@embecosm.com> + + * doc/install.texi (Configuration): Document `--with-isa-spec=' + RISC-V option. + * doc/invoke.texi (Option Summary): List `-misa-spec=' RISC-V + option. + (RISC-V Options): Document it. + +2022-02-08 Maciej W. Rozycki <macro@embecosm.com> + + * config/riscv/t-riscv (riscv-sr.o): Add $(TM_H) dependency. + +2022-02-08 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx.cc (write_fn_proto_1): Handle 'main (int)'. + +2022-02-08 Tom de Vries <tdevries@suse.de> + + PR target/104364 + * config/nvptx/nvptx-protos.h (nvptx_mem_local_p): Declare. + * config/nvptx/nvptx.cc (nvptx_reorg_uniform_simt): Assert that + change is validated. + (nvptx_mem_local_p): New function. + * config/nvptx/nvptx.md: Use nvptx_mem_local_p. + (define_c_enum "unspecv"): Add UNSPECV_CAS_LOCAL. + (define_insn "atomic_compare_and_swap<mode>_1_local"): New + non-atomic, non-predicable define_insn, factored out of ... + (define_insn "atomic_compare_and_swap<mode>_1"): ... here. + Make predicable again. + (define_expand "atomic_compare_and_swap<mode>"): Use + atomic_compare_and_swap<mode>_1_local. + +2022-02-08 liuhongt <hongtao.liu@intel.com> + + PR rtl-optimization/104059 + * regcprop.cc (copyprop_hardreg_forward_1): Don't propagate + for a more expensive reg-reg move. + +2022-02-07 Tamar Christina <tamar.christina@arm.com> + + * config/arm/arm_neon.h (vusdotq_s32, vusdot_laneq_s32, + vusdotq_laneq_s32, vsudot_laneq_s32, vsudotq_laneq_s32): New + * config/arm/arm_neon_builtins.def (usdot): Add V16QI. + (usdot_laneq, sudot_laneq): New. + * config/arm/neon.md (neon_<sup>dot_laneq<vsi2qi>): New. + (neon_<sup>dot_lane<vsi2qi>): Remote unneeded code. + +2022-02-07 Tamar Christina <tamar.christina@arm.com> + + * config/arm/arm_neon.h (vdot_laneq_u32, vdotq_laneq_u32, + vdot_laneq_s32, vdotq_laneq_s32): New. + * config/arm/arm_neon_builtins.def (sdot_laneq, udot_laneq): New. + * config/arm/neon.md (neon_<sup>dot<vsi2qi>): New. + (<sup>dot_prod<vsi2qi>): Re-order rtl. + (neon_<sup>dot_lane<vsi2qi>): Fix rtl order and endiannes. + (neon_<sup>dot_laneq<vsi2qi>): New. + +2022-02-07 Andreas Krebbel <krebbel@linux.ibm.com> + + PR target/104327 + * config/s390/s390.cc (s390_can_inline_p): Accept a few more flags + if always_inline is set. Don't inline when tune differs without + always_inline. + +2022-02-07 Richard Biener <rguenther@suse.de> + + PR middle-end/104402 + * gimple-expr.cc (is_gimple_condexpr): _Complex typed + compares are not valid. + * tree-cfg.cc (verify_gimple_assign_ternary): For COND_EXPR + check is_gimple_condexpr. + +2022-02-07 Kewen Lin <linkw@linux.ibm.com> + + PR target/103627 + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Move the + hunk affecting VSX and ALTIVEC to appropriate place. + +2022-02-07 Kewen Lin <linkw@linux.ibm.com> + + PR target/103627 + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Disable + MMA if !TARGET_VSX. + +2022-02-06 Jakub Jelinek <jakub@redhat.com> + + PR c++/89074 + PR c++/104033 + * fold-const.h (folding_initializer): Adjust comment. + (folding_cxx_constexpr): Declare. + * fold-const.cc (folding_initializer): Adjust comment. + (folding_cxx_constexpr): New variable. + (address_compare): Restrict the decl vs. STRING_CST + or vice versa or STRING_CST vs. STRING_CST or + is_global_var != is_global_var optimizations to !folding_cxx_constexpr. + Punt for FUNCTION_DECLs with non-zero offsets. If folding_initializer, + assume non-aliased functions have non-zero size and have different + addresses. For folding_cxx_constexpr, punt on comparisons of start + of some object and end of another one, regardless whether it is a decl + or string literal. Also punt for folding_cxx_constexpr on + STRING_CST vs. STRING_CST comparisons if the two literals could be + overlapping. + +2022-02-05 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/104389 + * match.pd (x * 0 -> 0): Punt if x maybe infinite and NaNs are + honored. + +2022-02-05 Kito Cheng <kito.cheng@sifive.com> + + * configure.ac: Fix detection for zifencei support. + * configure: Regenerate. + +2022-02-05 Kito Cheng <kito.cheng@sifive.com> + + PR target/104219 + * config.gcc (riscv*-*-*): Normalize the with_isa_spec value. + (all_defaults): Add isa_spec. + * config/riscv/riscv.h (OPTION_DEFAULT_SPECS): Add isa_spec. + +2022-02-04 Bill Schmidt <wschmidt@linux.ibm.com> + + * config/rs6000/rs6000-c.cc (resolve_vec_mul): Accept args and types + parameters instead of arglist and nargs. Simplify accordingly. Remove + unnecessary test for argument count mismatch. + (resolve_vec_cmpne): Likewise. + (resolve_vec_adde_sube): Likewise. + (resolve_vec_addec_subec): Likewise. + (altivec_resolve_overloaded_builtin): Move overload special handling + after the gathering of arguments into args[] and types[] and the test + for correct number of arguments. Don't perform the test for correct + number of arguments for certain special cases. Call the other special + cases with args and types instead of arglist and nargs. + +2022-02-04 Bill Schmidt <wschmidt@linux.ibm.com> + + PR target/100808 + * doc/extend.texi (Basic PowerPC Built-in Functions Available on ISA + 3.1): Provide consistent type names. Remove unnecessary semicolons. + Fix bad line breaks. + +2022-02-04 Jakub Jelinek <jakub@redhat.com> + + PR target/104380 + * config/rs6000/rs6000.cc (rs6000_mangle_decl_assembler_name): Also + adjust mangling of __builtin*printf_chk. + +2022-02-04 Jonathan Wakely <jwakely@redhat.com> + + * doc/cpp.texi (Variadic Macros): Replace C++2a with C++20. + +2022-02-04 Richard Biener <rguenther@suse.de> + Bin Cheng <bin.cheng@linux.alibaba.com> + + PR tree-optimization/100499 + * fold-const.h (multiple_of_p): Add nowrap parameter, defaulted + to true. + * fold-const.cc (multiple_of_p): Likewise. Honor it for + MULT_EXPR, PLUS_EXPR and MINUS_EXPR and pass it along, + switching to false for conversions. + * tree-ssa-loop-niter.cc (number_of_iterations_ne): Do not + claim the outermost expression does not wrap when calling + multiple_of_p. Refactor the check done to check the + original IV, avoiding a bias that might wrap. + +2022-02-04 Richard Biener <rguenther@suse.de> + + * fold-const.cc (multiple_of_p): Re-write and move LSHIFT_EXPR + handling. + +2022-02-04 Eric Botcazou <ebotcazou@adacore.com> + + PR debug/104366 + * dwarf2out.cc (dwarf2out_finish): Empty base_types. + (dwarf2out_early_finish): Likewise. + +2022-02-04 Eric Botcazou <ebotcazou@adacore.com> + + PR tree-optimization/104356 + * match.pd (X / bool_range_Y is X): Add guard. + (X / X is one): Likewise. + (X / abs (X) is X < 0 ? -1 : 1): Likewise. + (X / -X is -1): Likewise. + (1 / X -> X == 1): Likewise. + +2022-02-04 Richard Biener <rguenther@suse.de> + + PR tree-optimization/103641 + * tree-vect-patterns.cc (vect_synth_mult_by_constant): + Pass the vector mode to choose_mult_variant. + +2022-02-04 Roger Sayle <roger@nextmovesoftware.com> + + PR rtl-optimization/101885 + * combine.cc (try_combine): When splitting a parallel into two + sequential sets, check not only that the first doesn't clobber + the second but also that the second doesn't clobber the first. + +2022-02-04 Richard Biener <rguenther@suse.de> + + PR middle-end/90348 + PR middle-end/104092 + * tree-core.h (clobber_kind): New enum. + (tree_base::u::bits::address_space): Document use in CONSTRUCTORs. + * tree.h (CLOBBER_KIND): Add. + (build_clobber): Add clobber kind argument, defaulted to + CLOBBER_UNDEF. + * tree.cc (build_clobber): Likewise. + * gimple.h (gimple_clobber_p): New overload with specified kind. + * tree-streamer-in.cc (streamer_read_tree_bitfields): Stream + CLOBBER_KIND. + * tree-streamer-out.cc (streamer_write_tree_bitfields): + Likewise. + * tree-pretty-print.cc (dump_generic_node): Mark EOL CLOBBERs. + * gimplify.cc (gimplify_bind_expr): Build storage end-of-life clobbers + with CLOBBER_EOL. + (gimplify_target_expr): Likewise. + * tree-inline.cc (expand_call_inline): Likewise. + * tree-ssa-ccp.cc (insert_clobber_before_stack_restore): Likewise. + * gimple-ssa-warn-access.cc (pass_waccess::check_stmt): Only treat + CLOBBER_EOL clobbers as ending lifetime of storage. + +2022-02-04 Martin Sebor <msebor@redhat.com> + + * pointer-query.h (pointer_query::cache_type): Use auto_vec for auto + cleanup. + +2022-02-03 Martin Sebor <msebor@redhat.com> + + PR middle-end/104260 + * passes.def (pass_warn_access): Adjust pass placement. + +2022-02-03 Uroš Bizjak <ubizjak@gmail.com> + + PR target/104362 + * config/i386/i386.cc (find_drap_reg): For 32bit targets + return DI_REG if function uses __builtin_eh_return. + +2022-02-03 Martin Sebor <msebor@redhat.com> + + * gimple-ssa-warn-restrict.cc (class pass_wrestrict): Outline ctor. + (pass_wrestrict::m_ptr_qry): New member. + (wrestrict_walk): Rename... + (pass_wrestrict::check_block): ...to this. + (pass_wrestrict::execute): Set up and tear down pointer_query and + ranger. + (builtin_memref::builtin_memref): Change ctor argument. Simplify. + (builtin_access::builtin_access): Same. + (builtin_access::m_ptr_qry): New member. + (check_call): Rename... + (pass_wrestrict::check_call): ...to this. + (check_bounds_or_overlap): Change argument. + * gimple-ssa-warn-restrict.h (check_bounds_or_overlap): Same. + +2022-02-03 Martin Sebor <msebor@redhat.com> + + * gimple-array-bounds.cc (array_bounds_checker::array_bounds_checker): + Define ctor. + (array_bounds_checker::get_value_range): Use new member. + (array_bounds_checker::check_mem_ref): Same. + * gimple-array-bounds.h (array_bounds_checker::array_bounds_checker): + Outline ctor. + (array_bounds_checker::m_ptr_query): New member. + +2022-02-03 Martin Sebor <msebor@redhat.com> + + * gimple-ssa-warn-access.cc (pass_waccess::pass_waccess): Remove + pointer_query cache. + * pointer-query.cc (pointer_query::pointer_query): Remove cache + argument. Zero-initialize new cache member. + (pointer_query::get_ref): Replace cache pointer with direct access. + (pointer_query::put_ref): Same. + (pointer_query::flush_cache): Same. + (pointer_query::dump): Same. + * pointer-query.h (class pointer_query): Remove cache argument from + ctor. Change cache pointer to cache subobject member. + * tree-ssa-strlen.cc: Remove pointer_query cache. + +2022-02-03 Martin Sebor <msebor@redhat.com> + + PR tree-optimization/104119 + * gimple-ssa-sprintf.cc (struct directive): Change argument type. + (format_none): Same. + (format_percent): Same. + (format_integer): Same. + (format_floating): Same. + (get_string_length): Same. + (format_character): Same. + (format_string): Same. + (format_plain): Same. + (format_directive): Same. + (compute_format_length): Same. + (handle_printf_call): Same. + * tree-ssa-strlen.cc (get_range_strlen_dynamic): Same. Call + get_maxbound. + (get_range_strlen_phi): Same. + (get_maxbound): New function. + (strlen_pass::get_len_or_size): Adjust to parameter change. + * tree-ssa-strlen.h (get_range_strlen_dynamic): Change argument type. + +2022-02-03 Bill Schmidt <wschmidt@linux.ibm.com> + + PR target/103686 + * config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_builtin): Remove + test for !rs6000_fold_gimple. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Likewise. + * config/rs6000/rs6000.opt (mfold-gimple): Remove. + +2022-02-03 Bill Schmidt <wschmidt@linux.ibm.com> + + PR target/95082 + * config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Handle + endianness for vclzlsbb and vctzlsbb. + * config/rs6000/rs6000-builtins.def (VCLZLSBB_V16QI): Change + default pattern and indicate a different pattern will be used for + big endian. + (VCLZLSBB_V4SI): Likewise. + (VCLZLSBB_V8HI): Likewise. + (VCTZLSBB_V16QI): Likewise. + (VCTZLSBB_V4SI): Likewise. + (VCTZLSBB_V8HI): Likewise. + +2022-02-03 Bill Schmidt <wschmidt@linux.ibm.com> + + * config.gcc (powerpc*-*-*): Add rs6000-builtin.o to extra_objs. + * config/rs6000/rs6000-builtin.cc: New file, containing code moved + from other files. + * config/rs6000/rs6000-call.cc (cpu_is_info): Move to + rs6000-builtin.cc. + (cpu_supports_info): Likewise. + (rs6000_type_string): Likewise. + (altivec_expand_predicate_builtin): Likewise. + (rs6000_htm_spr_icode): Likewise. + (altivec_expand_vec_init_builtin): Likewise. + (get_element_number): Likewise. + (altivec_expand_vec_set_builtin): Likewise. + (altivec_expand_vec_ext_builtin): Likewise. + (rs6000_invalid_builtin): Likewise. + (rs6000_fold_builtin): Likewise. + (fold_build_vec_cmp): Likewise. + (fold_compare_helper): Likewise. + (map_to_integral_tree_type): Likewise. + (fold_mergehl_helper): Likewise. + (fold_mergeeo_helper): Likewise. + (rs6000_builtin_valid_without_lhs): Likewise. + (rs6000_builtin_is_supported): Likewise. + (rs6000_gimple_fold_mma_builtin): Likewise. + (rs6000_gimple_fold_builtin): Likewise. + (rs6000_expand_ldst_mask): Likewise. + (cpu_expand_builtin): Likewise. + (elemrev_icode): Likewise. + (ldv_expand_builtin): Likewise. + (lxvrse_expand_builtin): Likewise. + (lxvrze_expand_builtin): Likewise. + (stv_expand_builtin): Likewise. + (mma_expand_builtin): Likewise. + (htm_spr_num): Likewise. + (htm_expand_builtin): Likewise. + (rs6000_expand_builtin): Likewise. + (rs6000_vector_type): Likewise. + (rs6000_init_builtins): Likewise. Remove initialization of + builtin_mode_to_type entries. + (rs6000_builtin_decl): Move to rs6000-builtin.cc. + * config/rs6000/rs6000.cc (rs6000_builtin_mask_for_load): New + external declaration. + (rs6000_builtin_md_vectorized_function): Likewise. + (rs6000_builtin_reciprocal): Likewise. + (altivec_builtin_mask_for_load): Move to rs6000-builtin.cc. + (rs6000_builtin_types): Likewise. + (builtin_mode_to_type): Remove. + (rs6000_builtin_mask_for_load): Move to rs6000-builtin.cc. Remove + static qualifier. + (rs6000_builtin_md_vectorized_function): Likewise. + (rs6000_builtin_reciprocal): Likewise. + * config/rs6000/rs6000.h (builtin_mode_to_type): Remove. + * config/rs6000/t-rs6000 (rs6000-builtin.o): New target. + +2022-02-03 Richard Biener <rguenther@suse.de> + + PR debug/104337 + * tree-nrv.cc (pass_nrv::execute): Remove tieing result and found + together via DECL_ABSTRACT_ORIGIN. + +2022-02-03 Bill Schmidt <wschmidt@linux.ibm.com> + + * config/rs6000/rs6000-call.cc (rs6000_expand_builtin): Revise error + message for RES_BITS case. + +2022-02-03 Aldy Hernandez <aldyh@redhat.com> + + * gimple-range-fold.cc (fur_list::fur_list): Set m_local[1] correctly. + +2022-02-03 Jakub Jelinek <jakub@redhat.com> + + * config/arm/arm.opt (mfix-cortex-a57-aes-1742098, + mfix-cortex-a72-aes-1655431): Ensure description ends with full stop. + +2022-02-03 Aldy Hernandez <aldyh@redhat.com> + + * cfganal.cc (verify_marked_backedges): New. + * cfganal.h (verify_marked_backedges): New. + * gimple-range-path.cc (path_range_query::path_range_query): + Verify freshness of back edges. + * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call + mark_dfs_back_edges. + * tree-ssa-threadbackward.cc (back_threader::back_threader): Move + path_range_query construction after backedges have been + updated. + +2022-02-03 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-simd.md (movmisalign<mode>): Extend from + VALL to VALL_F16. + +2022-02-03 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/iterators.md (VALL_F16MOV): Delete. + * config/aarch64/aarch64-simd.md (mov<mode>): Use VALL_F16 instead + of VALL_F16MOV. + +2022-02-03 Martin Liska <mliska@suse.cz> + + * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): + Change subject and object in the error message. + * config/s390/s390.cc (s390_valid_target_attribute_inner_p): + Likewise. + +2022-02-03 Martin Liska <mliska@suse.cz> + + * config/s390/s390.cc (s390_valid_target_attribute_inner_p): + Use the error message for i386 target. + +2022-02-03 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/104334 + * range-op.cc (range_operator::wi_fold_in_parts): Change lh_range + and rh_range type to widest_int and subtract in widest_int. Remove + ov_rh, ov_lh and sign vars, always perform comparisons as signed + and use >, < and == operators for it. + +2022-02-03 Martin Sebor <msebor@redhat.com> + + * common.opt (-Wuse-after-free): Correct typos. + +2022-02-02 David Malcolm <dmalcolm@redhat.com> + + PR analyzer/104270 + * doc/invoke.texi (-ftrivial-auto-var-init=): Add reference to + -Wanalyzer-use-of-uninitialized-value to paragraph documenting that + -ftrivial-auto-var-init= doesn't suppress warnings. + +2022-02-02 Martin Liska <mliska@suse.cz> + + * dwarf2out.cc (TEXT_SECTION_NAME): Remove unused macro. + +2022-02-02 Bernd Kuhls <bernd.kuhls@t-online.de> + + PR target/94372 + * config/or1k/linux.h (CPP_SPEC): Define. + +2022-02-02 Tamar Christina <tamar.christina@arm.com> + + PR tree-optimization/102819 + PR tree-optimization/103169 + * config/arm/vec-common.md (cml<fcmac1><conj_op><mode>4): Use + canonical order. + +2022-02-02 Tamar Christina <tamar.christina@arm.com> + + PR tree-optimization/102819 + PR tree-optimization/103169 + * config/aarch64/aarch64-simd.md (cml<fcmac1><conj_op><mode>4): Use + canonical order. + * config/aarch64/aarch64-sve.md (cml<fcmac1><conj_op><mode>4): Likewise. + +2022-02-02 Tamar Christina <tamar.christina@arm.com> + + PR tree-optimization/102819 + PR tree-optimization/103169 + * doc/md.texi: Update docs for cfms, cfma. + * tree-data-ref.h (same_data_refs): Accept optional offset. + * tree-vect-slp-patterns.cc (is_linear_load_p): Fix issue with repeating + patterns. + (vect_normalize_conj_loc): Remove. + (is_eq_or_top): Change to take two nodes. + (enum _conj_status, compatible_complex_nodes_p, + vect_validate_multiplication): New. + (class complex_add_pattern, complex_add_pattern::matches, + complex_add_pattern::recognize, class complex_mul_pattern, + complex_mul_pattern::recognize, class complex_fms_pattern, + complex_fms_pattern::recognize, class complex_operations_pattern, + complex_operations_pattern::recognize, addsub_pattern::recognize): Pass + new cache. + (complex_fms_pattern::matches, complex_mul_pattern::matches): Pass new + cache and use new validation code. + * tree-vect-slp.cc (vect_match_slp_patterns_2, vect_match_slp_patterns, + vect_analyze_slp): Pass along cache. + (compatible_calls_p): Expose. + * tree-vectorizer.h (compatible_calls_p, slp_node_hash, + slp_compat_nodes_map_t): New. + (class vect_pattern): Update signatures include new cache. + +2022-02-02 Hans-Peter Nilsson <hp@axis.com> + + * config/cris/cris.cc (cris_preferred_reload_class): Reject + "eliminated" registers and small-enough constants unless + reloaded into a class that is a subset of GENERAL_REGS. + * config/cris/cris.md (attribute "cpu_variant"): New. + (attribute "enabled"): Conditionalize on a matching attribute + cpu_variant, if specified. + ("*movsi_internal<setcc><setnz><setnzvc>"): For moves to and from + memory, add cpu-variant-enabled variants for "r" alternatives on + the far side of the "x" alternatives, preferring the "x" ones + only for variants where MOF is present (in addition to SRP). + +2022-02-02 Hans-Peter Nilsson <hp@axis.com> + + * config/cris/cris.cc (cris_register_move_cost): Remove special pre-ira + extra cost for ALL_REGS. + +2022-02-02 Hans-Peter Nilsson <hp@axis.com> + + * config/cris/constraints.md (define_register_constraint "b"): Now + GENERAL_REGS. + * config/cris/cris.md (CRIS_ACR_REGNUM): Remove. + * config/cris/cris.h: (reg_class, REG_CLASS_NAMES) + (REG_CLASS_CONTENTS): Remove ACR_REGS, SPEC_ACR_REGS, GENNONACR_REGS, + and SPEC_GENNONACR_REGS. + * config/cris/cris.cc (cris_preferred_reload_class): Don't mention + ACR_REGS and return GENERAL_REGS instead of GENNONACR_REGS. + +2022-02-02 Hans-Peter Nilsson <hp@axis.com> + + * config/cris/cris.md ("*movsi_internal<setcc><setnz><setnzvc>"): + Conditionalize on (sub-)register operands or operand 1 being 0. + +2022-02-02 Hans-Peter Nilsson <hp@axis.com> + + * config/cris/cris.h (TARGET_DEFAULT): Don't include MASK_MUL_BUG. + (MUL_BUG_ASM_DEFAULT): New macro. + (MAYBE_AS_NO_MUL_BUG_ABORT): Define in terms of MUL_BUG_ASM_DEFAULT. + * doc/invoke.texi (CRIS Options, -mmul-bug-workaround): Adjust + accordingly. + +2022-02-01 Eugene Rozenfeld <erozen@microsoft.com> + + * opts.cc (common_handle_option): Don't set param_early_inliner_max_iterations + to 10 for AutoFDO. + +2022-02-01 Eugene Rozenfeld <erozen@microsoft.com> + + * auto-profile.cc (auto_profile): Hard-code the number of iterations (10). + +2022-02-01 Andrew Pinski <apinski@marvell.com> + + * doc/install.texi: + +2022-02-01 Ilya Leoshkevich <iii@linux.ibm.com> + + * config/s390/s390.cc (s390_code_end): Do not switch back to + code section. + +2022-02-01 Jakub Jelinek <jakub@redhat.com> + + PR target/104323 + * config/rs6000/t-rs6000 (EXTRA_GTYPE_DEPS): Append rs6000-builtins.h + rather than $(srcdir)/config/rs6000/rs6000-builtins.def. + * config/rs6000/rs6000-gen-builtins.cc (write_decls): Don't use + GTY((user)) for struct bifdata and struct ovlddata. Instead add + GTY((skip(""))) to members with pointer and enum types that don't need + to be tracked. Add GTY(()) to rs6000_builtin_info and rs6000_instance_info + declarations. Don't emit gt_ggc_mx and gt_pch_nx declarations. + (write_extern_fntype, write_fntype): Remove. + (write_fntype_init): Emit the fntype vars as automatic vars instead + of file scope ones. + (write_header_file): Don't iterate with write_extern_fntype. + (write_init_file): Don't iterate with write_fntype. Don't emit + gt_ggc_mx and gt_pch_nx definitions. + +2022-02-01 Jason Merrill <jason@redhat.com> + + * tree.h (struct tree_vec_map_cache_hasher): Move from... + * tree.cc (struct tree_vec_map_cache_hasher): ...here. + +2022-02-01 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx.cc (nvptx_single): Use nvptx_uniform_warp_check. + * config/nvptx/nvptx.md (define_c_enum "unspecv"): Add + UNSPECV_UNIFORM_WARP_CHECK. + (define_insn "nvptx_uniform_warp_check"): New define_insn. + +2022-02-01 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx.cc (nvptx_single): Use nvptx_warpsync. + * config/nvptx/nvptx.md (define_c_enum "unspecv"): Add + UNSPECV_WARPSYNC. + (define_insn "nvptx_warpsync"): New define_insn. + +2022-02-01 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx.opt (mptx): Set to PTX_VERSION_6_3 by default. + +2022-02-01 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx-opts.h (enum ptx_version): Add PTX_VERSION_6_0. + * config/nvptx/nvptx.h (TARGET_PTX_6_0): New macro. + * config/nvptx/nvptx.md (define_insn "nvptx_barsync"): Use barrier + insn for TARGET_PTX_6_0. + +2022-02-01 Tom de Vries <tdevries@suse.de> + + PR target/100428 + * config/nvptx/nvptx.cc (prevent_branch_around_nothing): Handle nop + insn. + +2022-02-01 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx.md (define_insn "atomic_compare_and_swap<mode>_1") + (define_insn "atomic_exchange<mode>") + (define_insn "atomic_fetch_add<mode>") + (define_insn "atomic_fetch_addsf") + (define_insn "atomic_fetch_<logic><mode>"): Output non-atomic version + if memory operands is frame-relative. + +2022-02-01 Tom de Vries <tdevries@suse.de> + + * config/nvptx/nvptx.cc (enum nvptx_builtins): Add + NVPTX_BUILTIN_MEMBAR_GL and NVPTX_BUILTIN_MEMBAR_CTA. + (VOID): New macro. + (nvptx_init_builtins): Add MEMBAR_GL and MEMBAR_CTA. + (nvptx_expand_builtin): Handle NVPTX_BUILTIN_MEMBAR_GL and + NVPTX_BUILTIN_MEMBAR_CTA. + (nvptx_lockfull_update): Add level parameter. Emit barriers. + (nvptx_reduction_update, nvptx_goacc_reduction_fini): Update call to + nvptx_lockfull_update. + * config/nvptx/nvptx.md (define_c_enum "unspecv"): Add + UNSPECV_MEMBAR_GL. + (define_expand "nvptx_membar_gl"): New expand. + (define_insn "*nvptx_membar_gl"): New insn. + +2022-02-01 Martin Liska <mliska@suse.cz> + + * doc/install.texi: Remove option for GCC < 4.8. + +2022-02-01 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/104307 + * tree-vect-generic.cc (expand_vector_comparison): Don't push debug + stmts to uses vector, just set vec_cond_expr_only to false for + non-VEC_COND_EXPRs instead of pushing them into uses. Treat + VEC_COND_EXPRs that use lhs not just in rhs1, but rhs2 or rhs3 too + like non-VEC_COND_EXPRs. + +2022-02-01 Bill Schmidt <wschmidt@linux.ibm.com> + + * config/rs6000/rs6000-overload.def (VEC_ABSD): Remove #ifdef token. + (VEC_BLENDV): Likewise. + (VEC_BPERM): Likewise. + (VEC_CFUGE): Likewise. + (VEC_CIPHER_BE): Likewise. + (VEC_CIPHERLAST_BE): Likewise. + (VEC_CLRL): Likewise. + (VEC_CLRR): Likewise. + (VEC_CMPNEZ): Likewise. + (VEC_CNTLZ): Likewise. + (VEC_CNTLZM): Likewise. + (VEC_CNTTZM): Likewise. + (VEC_CNTLZ_LSBB): Likewise. + (VEC_CNTM): Likewise. + (VEC_CNTTZ): Likewise. + (VEC_CNTTZ_LSBB): Likewise. + (VEC_CONVERT_4F32_8F16): Likewise. + (VEC_DIV): Likewise. + (VEC_DIVE): Likewise. + (VEC_EQV): Likewise. + (VEC_EXPANDM): Likewise. + (VEC_EXTRACT_FP_FROM_SHORTH): Likewise. + (VEC_EXTRACT_FP_FROM_SHORTL): Likewise. + (VEC_EXTRACTH): Likewise. + (VEC_EXTRACTL): Likewise. + (VEC_EXTRACTM): Likewise. + (VEC_EXTRACT4B): Likewise. + (VEC_EXTULX): Likewise. + (VEC_EXTURX): Likewise. + (VEC_FIRSTMATCHINDEX): Likewise. + (VEC_FIRSTMACHOREOSINDEX): Likewise. + (VEC_FIRSTMISMATCHINDEX): Likewise. + (VEC_FIRSTMISMATCHOREOSINDEX): Likewise. + (VEC_GB): Likewise. + (VEC_GENBM): Likewise. + (VEC_GENHM): Likewise. + (VEC_GENWM): Likewise. + (VEC_GENDM): Likewise. + (VEC_GENQM): Likewise. + (VEC_GENPCVM): Likewise. + (VEC_GNB): Likewise. + (VEC_INSERTH): Likewise. + (VEC_INSERTL): Likewise. + (VEC_INSERT4B): Likewise. + (VEC_LXVL): Likewise. + (VEC_MERGEE): Likewise. + (VEC_MERGEO): Likewise. + (VEC_MOD): Likewise. + (VEC_MSUB): Likewise. + (VEC_MULH): Likewise. + (VEC_NAND): Likewise. + (VEC_NCIPHER_BE): Likewise. + (VEC_NCIPHERLAST_BE): Likewise. + (VEC_NEARBYINT): Likewise. + (VEC_NMADD): Likewise. + (VEC_ORC): Likewise. + (VEC_PDEP): Likewise. + (VEC_PERMX): Likewise. + (VEC_PEXT): Likewise. + (VEC_POPCNT): Likewise. + (VEC_PARITY_LSBB): Likewise. + (VEC_REPLACE_ELT): Likewise. + (VEC_REPLACE_UN): Likewise. + (VEC_REVB): Likewise. + (VEC_RINT): Likewise. + (VEC_RLMI): Likewise. + (VEC_RLNM): Likewise. + (VEC_SBOX_BE): Likewise. + (VEC_SIGNEXTI): Likewise. + (VEC_SIGNEXTLL): Likewise. + (VEC_SIGNEXTQ): Likewise. + (VEC_SLDB): Likewise. + (VEC_SLV): Likewise. + (VEC_SPLATI): Likewise. + (VEC_SPLATID): Likewise. + (VEC_SPLATI_INS): Likewise. + (VEC_SQRT): Likewise. + (VEC_SRDB): Likewise. + (VEC_SRV): Likewise. + (VEC_STRIL): Likewise. + (VEC_STRIL_P): Likewise. + (VEC_STRIR): Likewise. + (VEC_STRIR_P): Likewise. + (VEC_STXVL): Likewise. + (VEC_TERNARYLOGIC): Likewise. + (VEC_TEST_LSBB_ALL_ONES): Likewise. + (VEC_TEST_LSBB_ALL_ZEROS): Likewise. + (VEC_VEE): Likewise. + (VEC_VES): Likewise. + (VEC_VIE): Likewise. + (VEC_VPRTYB): Likewise. + (VEC_VSCEEQ): Likewise. + (VEC_VSCEGT): Likewise. + (VEC_VSCELT): Likewise. + (VEC_VSCEUO): Likewise. + (VEC_VSEE): Likewise. + (VEC_VSES): Likewise. + (VEC_VSIE): Likewise. + (VEC_VSTDC): Likewise. + (VEC_VSTDCN): Likewise. + (VEC_VTDC): Likewise. + (VEC_XL): Likewise. + (VEC_XL_BE): Likewise. + (VEC_XL_LEN_R): Likewise. + (VEC_XL_SEXT): Likewise. + (VEC_XL_ZEXT): Likewise. + (VEC_XST): Likewise. + (VEC_XST_BE): Likewise. + (VEC_XST_LEN_R): Likewise. + (VEC_XST_TRUNC): Likewise. + (VEC_XXPERMDI): Likewise. + (VEC_XXSLDWI): Likewise. + (VEC_TSTSFI_EQ_DD): Likewise. + (VEC_TSTSFI_EQ_TD): Likewise. + (VEC_TSTSFI_GT_DD): Likewise. + (VEC_TSTSFI_GT_TD): Likewise. + (VEC_TSTSFI_LT_DD): Likewise. + (VEC_TSTSFI_LT_TD): Likewise. + (VEC_TSTSFI_OV_DD): Likewise. + (VEC_TSTSFI_OV_TD): Likewise. + (VEC_VADDCUQ): Likewise. + (VEC_VADDECUQ): Likewise. + (VEC_VADDEUQM): Likewise. + (VEC_VADDUDM): Likewise. + (VEC_VADDUQM): Likewise. + (VEC_VBPERMQ): Likewise. + (VEC_VCLZB): Likewise. + (VEC_VCLZD): Likewise. + (VEC_VCLZH): Likewise. + (VEC_VCLZW): Likewise. + (VEC_VCTZB): Likewise. + (VEC_VCTZD): Likewise. + (VEC_VCTZH): Likewise. + (VEC_VCTZW): Likewise. + (VEC_VEEDP): Likewise. + (VEC_VEESP): Likewise. + (VEC_VESDP): Likewise. + (VEC_VESSP): Likewise. + (VEC_VIEDP): Likewise. + (VEC_VIESP): Likewise. + (VEC_VPKSDSS): Likewise. + (VEC_VPKSDUS): Likewise. + (VEC_VPKUDUM): Likewise. + (VEC_VPKUDUS): Likewise. + (VEC_VPOPCNT): Likewise. + (VEC_VPOPCNTB): Likewise. + (VEC_VPOPCNTD): Likewise. + (VEC_VPOPCNTH): Likewise. + (VEC_VPOPCNTW): Likewise. + (VEC_VPRTYBD): Likewise. + (VEC_VPRTYBQ): Likewise. + (VEC_VPRTYBW): Likewise. + (VEC_VRLD): Likewise. + (VEC_VSLD): Likewise. + (VEC_VSRAD): Likewise. + (VEC_VSRD): Likewise. + (VEC_VSTDCDP): Likewise. + (VEC_VSTDCNDP): Likewise. + (VEC_VSTDCNQP): Likewise. + (VEC_VSTDCNSP): Likewise. + (VEC_VSTDCQP): Likewise. + (VEC_VSTDCSP): Likewise. + (VEC_VSUBECUQ): Likewise. + (VEC_VSUBEUQM): Likewise. + (VEC_VSUBUDM): Likewise. + (VEC_VSUBUQM): Likewise. + (VEC_VTDCDP): Likewise. + (VEC_VTDCSP): Likewise. + (VEC_VUPKHSW): Likewise. + (VEC_VUPKLSW): Likewise. + +2022-02-01 Andreas Krebbel <krebbel@linux.ibm.com> + + PR rtl-optimization/101260 + * regcprop.cc (maybe_mode_change): Invoke mode_change_ok also for + copy_regno. + +2022-02-01 Xi Ruoyao <xry111@mengyan1223.wang> + + PR middle-end/95115 + * fold-const.cc (const_binop): Do not fold NaN result from + non-NaN operands. + +2022-02-01 Tom de Vries <tdevries@suse.de> + + * tree-loop-distribution.cc (generate_reduction_builtin_1): Check for + -ftree-loop-distribute-patterns. + (loop_distribution::execute): Don't call transform_reduction_loop for + -fno-tree-loop-distribute-patterns. + +2022-01-31 Andrew Pinski <apinski@marvell.com> + + * fold-const.h (operand_compare::operand_equal_p): + Fix comment about OEP_* flags. + +2022-01-31 Jakub Jelinek <jakub@redhat.com> + + PR target/104298 + * config/rs6000/aix.h (OPTION_GLIBC): Remove. + * config/rs6000/darwin.h (OPTION_GLIBC): Likewise. + * config/rs6000/option-defaults.h (OPTION_GLIBC): Define to 0 + if not already defined. + +2022-01-31 Martin Sebor <msebor@redhat.com> + + PR middle-end/104232 + * gimple-ssa-warn-access.cc (pointers_related_p): Add argument. + Handle PHIs. Add a synonymous overload. + (pass_waccess::check_pointer_uses): Call pointers_related_p. + +2022-01-31 Richard Biener <rguenther@suse.de> + + PR tree-optimization/100499 + * fold-const.cc (multiple_of_p): Pass the correct type of + the expression to the recursive invocation of multiple_of_p + for conversions and use CASE_CONVERT. + +2022-01-31 Eric Botcazou <ebotcazou@adacore.com> + + PR target/104189 + * config/sparc/linux64.h (TARGET_DEFAULT): Add MASK_V8PLUS. + +2022-01-31 Richard Biener <rguenther@suse.de> + + PR tree-optimization/100499 + * tree-cfg.cc (verify_gimple_assign_ternary): Use multiple_p + on poly-ints instead of multiple_of_p. + * tree-ssa.cc (maybe_rewrite_mem_ref_base): Likewise. + (non_rewritable_mem_ref_base): Likewise. + (non_rewritable_lvalue_p): Likewise. + (execute_update_addresses_taken): Likewise. + +2022-01-29 Jakub Jelinek <jakub@redhat.com> + Andrew Pinski <apinski@marvell.com> + + PR tree-optimization/104279 + PR tree-optimization/104280 + PR tree-optimization/104281 + * match.pd (1 / X -> X == 1 for unsigned X): Build eq with + boolean_type_node and convert to type. Formatting fixes. + +2022-01-28 Yoshinori Sato <yo-satoh@sios.com> + + * config/sh/t-linux (MULTILIB_EXCEPTIONS): Add m1, mb/m1 and m2a. + +2022-01-28 Navid Rahimi <navidrahimi@microsoft.com> + + PR tree-optimization/103514 + * match.pd (a & b) ^ (a == b) -> !(a | b): New optimization. + (a & b) == (a ^ b) -> !(a | b): New optimization. + +2022-01-28 Marek Polacek <polacek@redhat.com> + + * doc/invoke.texi: Update -Wbidi-chars documentation. + +2022-01-28 Iain Sandoe <iain@sandoe.co.uk> + + * config/rs6000/darwin.h (OPTION_GLIBC): Define to 0. + +2022-01-28 Zhao Wei Liew <zhaoweiliew@gmail.com> + + PR tree-optimization/95424 + * match.pd: Simplify 1 / X where X is an integer. + +2022-01-28 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/104263 + * gimple-ssa-store-merging.cc (get_status_for_store_merging): For + cfun->can_throw_non_call_exceptions && cfun->eh test whether + last non-debug stmt in the bb is store_valid_for_store_merging_p + rather than last stmt. + +2022-01-28 Martin Liska <mliska@suse.cz> + + * diagnostic.cc (diagnostic_action_after_output): Remove extra + newline. + +2022-01-28 Martin Liska <mliska@suse.cz> + + * config/rs6000/host-darwin.cc (segv_crash_handler): + Do not use leading capital letter. + (segv_handler): Likewise. + * ipa-sra.cc (verify_splitting_accesses): Likewise. + * varasm.cc (get_section): Likewise. + +2022-01-28 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104267 + * tree-vect-stmts.cc (vectorizable_call): Properly use the + per-argument determined vector type for externals and + invariants. + +2022-01-28 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104263 + * tree-cfg.cc (gimple_purge_dead_abnormal_call_edges): + Purge edges also when !cfun->has_nonlocal_label + and !cfun->calls_setjmp. + +2022-01-28 Maciej W. Rozycki <macro@embecosm.com> + + * config/riscv/riscv.md: Document `auipc' and `bitmanip' `type' + attributes. + +2022-01-28 Jakub Jelinek <jakub@redhat.com> + + PR lto/104237 + * cfgrtl.cc (loc_equal): New function. + (unique_locus_on_edge_between_p): Use it. + +2022-01-28 Richard Biener <rguenther@suse.de> + + * cfganal.h (mark_dfs_back_edges): Provide API with struct + function argument. + * cfganal.cc (mark_dfs_back_edges): Take a struct function + to work on, add a wrapper passing cfun. + * graph.cc (draw_cfg_nodes_no_loops): Replace stray cfun + uses with fun which is already passed. + (draw_cfg_edges): Likewise. + (draw_cfg_nodes_for_loop): Do not use draw_cfg_nodes_for_loop + for fun != cfun. + +2022-01-27 Patrick Palka <ppalka@redhat.com> + + PR c++/99895 + * tree.cc (build_call_vec): Add const to second parameter. + * tree.h (build_call_vec): Likewise. + +2022-01-27 Martin Liska <mliska@suse.cz> + + PR web/104254 + * diagnostic.cc (diagnostic_initialize): + Initialize report_bug flag. + (diagnostic_action_after_output): + Explain that -freport-bug option can be used for pre-processed + file creation. Make the message shorter. + (error_recursion): Rename Internal to internal. + * diagnostic.h (struct diagnostic_context): New field. + * opts.cc (common_handle_option): Init the field here. + +2022-01-27 Kewen Lin <linkw@linux.ibm.com> + + PR target/103702 + * config/rs6000/rs6000.cc + (rs6000_cost_data::update_target_cost_per_stmt): Fix one wrong + assertion with early return. + +2022-01-27 Chung-Lin Tang <cltang@codesourcery.com> + + PR middle-end/103642 + * gimplify.cc (gimplify_scan_omp_clauses): Do not do indir_p handling + for non-pointer or non-reference-to-pointer cases. + +2022-01-27 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/104196 + * gimple-fold.h (rewrite_to_defined_overflow): Add IN_PLACE argument. + * gimple-fold.cc (rewrite_to_defined_overflow): Likewise. If true, + return NULL and emit needed stmts before and after stmt. + * tree-ssa-reassoc.cc (update_range_test): For inter-bb range opt + pick as operand_entry that will hold the merged test the one feeding + earliest condition, ensure that by swapping range->idx with some + other range's idx if needed. If seq is non-NULL, don't actually swap + it but instead rewrite stmts with undefined overflow in between + the two locations. + (maybe_optimize_range_tests): Set ops[]->id to bb->index with the + corresponding condition even if they have non-NULL ops[]->op. + Formatting fix. + +2022-01-26 Jakub Jelinek <jakub@redhat.com> + + PR target/104239 + * config/rs6000/emmintrin.h (_mm_sad_epu8): Use __asm__ instead of + asm. + * config/rs6000/smmintrin.h (_mm_minpos_epu16): Declare iterator + before for loop instead of for init clause. + * config/rs6000/bmi2intrin.h (_pext_u64): Likewise. + +2022-01-26 Jakub Jelinek <jakub@redhat.com> + + PR target/104239 + * config/rs6000/bmiintrin.h: Test _X86GPRINTRIN_H_INCLUDED instead of + _X86INTRIN_H_INCLUDED and adjust #error wording. + * config/rs6000/bmi2intrin.h: Likewise. + +2022-01-26 Jakub Jelinek <jakub@redhat.com> + + PR debug/104194 + * dwarf2out.cc (long_double_as_float128): New function. + (modified_type_die): For powerpc64le IEEE 754 quad long double + and complex long double emit those as DW_TAG_typedef to + _Float128 or complex _Float128 base type. + +2022-01-26 Marek Polacek <polacek@redhat.com> + + PR target/104213 + * gimple-ssa-warn-access.cc (pass_waccess::warn_invalid_pointer): Don't + warn when the SSA_NAME_VAR of REF has supressed -Wuse-after-free. + +2022-01-26 Martin Liska <mliska@suse.cz> + + * ipa-modref-tree.cc (modref_access_node::update): + Remove "--param param=foo" with "--param foo". + (modref_access_node::insert): Likewise. + (modref_access_node::insert_kill): Likewise. + * ipa-modref-tree.h (struct modref_ref_node): Likewise. + (struct modref_base_node): Likewise. + (struct modref_tree): Likewise. + +2022-01-26 Raoni Fassina Firmino <raoni@linux.ibm.com> + + PR target/94193 + * builtins.cc (expand_builtin_feclear_feraise_except): Add op0 + predicate check. + +2022-01-25 Martin Sebor <msebor@redhat.com> + + PR tree-optimization/104203 + * gimple-ssa-warn-access.cc (pass_data pass_data_waccess): Use + TV_WARN_ACCESS. + * pointer-query.cc (access_ref::merge_ref): Change return type. + Convert failure to a conservative success. + (access_ref::get_ref): Adjust to the change above. Short-circuit + PHI evaluation after first failure turned into conservative success. + * pointer-query.h (access_ref::merge_ref): Change return type. + * timevar.def (TV_WARN_ACCESS): New timer variable. + +2022-01-25 David Edelsohn <dje.gcc@gmail.com> + + * config/rs6000/aix.h (OPTION_GLIBC): Define as 0. + +2022-01-25 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104214 + * tree-ssa-loop-niter.cc (number_of_iterations_cond): Use + stronger guarantees for relational pointer compares when + rewriting BASE0 + STEP0 cmp BASE1 + STEP1 as + BASE0 + STEP0 - STEP1 cmp BASE1. + +2022-01-25 Jakub Jelinek <jakub@redhat.com> + + PR target/104172 + * config/rs6000/rs6000-internal.h (rs6000_passes_ieee128): Don't + declare. + * config/rs6000/rs6000.cc (rs6000_passes_ieee128, + ieee128_mangling_gcc_8_1): Remove. + (TARGET_ASM_GLOBALIZE_DECL_NAME): Don't redefine. + (rs6000_mangle_type): Return "u9__ieee128" instead of + ieee128_mangling_gcc_8_1 ? "U10__float128" : "u9__ieee128". + (rs6000_globalize_decl_name): Remove. + * config/rs6000/rs6000-call.cc (init_cumulative_args, + rs6000_function_arg_advance_1): Don't set rs6000_passes_ieee128. + +2022-01-24 Martin Sebor <msebor@redhat.com> + + * pointer-query.cc (pointer_query::dump): Remove duplicate + block. + +2022-01-24 Marek Polacek <polacek@redhat.com> + + PR preprocessor/104030 + * doc/invoke.texi: Update documentation for -Wbidi-chars. + +2022-01-24 Raoni Fassina Firmino <raoni@linux.ibm.com> + + PR target/94193 + * builtins.cc (expand_builtin_fegetround): New function. + (expand_builtin_feclear_feraise_except): New function. + (expand_builtin): Add cases for BUILT_IN_FEGETROUND, + BUILT_IN_FECLEAREXCEPT and BUILT_IN_FERAISEEXCEPT. + * config/rs6000/rs6000.md (fegetroundsi): New pattern. + (feclearexceptsi): New Pattern. + (feraiseexceptsi): New Pattern. + * doc/extend.texi: Add a new introductory paragraph about the + new builtins. + * doc/md.texi: (fegetround@var{m}): Document new optab. + (feclearexcept@var{m}): Document new optab. + (feraiseexcept@var{m}): Document new optab. + * optabs.def (fegetround_optab): New optab. + (feclearexcept_optab): New optab. + (feraiseexcept_optab): New optab. + +2022-01-24 Richard Biener <rguenther@suse.de> + Jiufu Guo <guojiufu@linux.ibm.com> + + PR tree-optimization/100740 + PR tree-optimization/101508 + PR tree-optimization/101972 + PR tree-optimization/102131 + * tree-ssa-loop-niter.cc (number_of_iterations_cond): Properly + constrain BASE0 + STEP0 cmp BASE1 + STEP1 to + BASE0 + STEP0 - STEP1 cmp BASE1 transform. + +2022-01-24 Jakub Jelinek <jakub@redhat.com> + + PR sanitizer/104158 + * opt-functions.awk (var_set): Handle EnumBitSet property. + * optc-gen.awk: Don't disallow RejectNegative if EnumBitSet is + specified. + * opts.h (enum cl_enum_var_value): New type. + * opts-common.cc (decode_cmdline_option): Use CLEV_* values. + Handle CLEV_BITSET. + (cmdline_handle_error): Handle CLEV_BITSET. + * opts.cc (test_enum_sets): Also test EnumBitSet requirements. + * doc/options.texi (EnumBitSet): Document. + * common.opt (fsanitize-coverage=): Use EnumBitSet instead of + EnumSet. + (trace-pc, trace-cmp): Drop Set properties. + +2022-01-24 Jakub Jelinek <jakub@redhat.com> + + PR sanitizer/104158 + * common.opt (flag_sanitize_coverage): Remove Variable entry. + (fsanitize-coverage=): Remove RejectNegative property, add + Var(flag_sanitize_coverage) and EnumSet properties. + (trace-pc): Add Set(1) property. + (trace-cmp): Add Set(2) property. + * opts.cc (common_handle_option): Don't handle + OPT_fsanitize_coverage_. + +2022-01-24 Jakub Jelinek <jakub@redhat.com> + + PR sanitizer/104158 + * opt-functions.awk (var_set): Handle EnumSet property. + * optc-gen.awk: Don't disallow RejectNegative if EnumSet is + specified. + * opt-read.awk: Handle Set property. + * opts.h (CL_ENUM_SET_SHIFT, CL_ERR_ENUM_SET_ARG): Define. + (struct cl_decoded_option): Mention enum in value description. + Add mask member. + (set_option): Add mask argument defaulted to 0. + * opts.cc (test_enum_sets): New function. + (opts_cc_tests): Call it. + * opts-common.cc (enum_arg_to_value): Change return argument + from bool to int, on success return index into the cl_enum_arg + array, on failure -1. Add len argument, if non-0, use strncmp + instead of strcmp. + (opt_enum_arg_to_value): Adjust caller. + (decode_cmdline_option): Handle EnumSet represented as + CLVC_ENUM with non-zero var_value. Initialize decoded->mask. + (decode_cmdline_options_to_array): CLear opt_array[0].mask. + (handle_option): Pass decoded->mask to set_options last argument. + (generate_option): Clear decoded->mask. + (generate_option_input_file): Likewise. + (cmdline_handle_error): Handle CL_ERR_ENUM_SET_ARG. + (set_option): Add mask argument, use it for CLVC_ENUM. + (control_warning_option): Adjust enum_arg_to_value caller. + * doc/options.texi: Document Set and EnumSet properties. + +2022-01-24 Jakub Jelinek <jakub@redhat.com> + + PR bootstrap/104170 + * config/linux.h (OPTION_GLIBC_P, OPTION_UCLIBC_P, + OPTION_BIONIC_P, OPTION_MUSL_P): Define. + (OPTION_GLIBC, OPTION_UCLIBC, OPTION_BIONIC, OPTION_MUSL): Redefine + using OPTION_*_P macros. + * config/alpha/linux.h (OPTION_GLIBC_P, OPTION_UCLIBC_P, + OPTION_BIONIC_P, OPTION_MUSL_P): Define. + (OPTION_GLIBC, OPTION_UCLIBC, OPTION_BIONIC, OPTION_MUSL): Redefine + using OPTION_*_P macros. + * config/rs6000/linux.h (OPTION_GLIBC_P, OPTION_UCLIBC_P, + OPTION_BIONIC_P, OPTION_MUSL_P): Define. + (OPTION_GLIBC, OPTION_UCLIBC, OPTION_BIONIC, OPTION_MUSL): Redefine + using OPTION_*_P macros. + * config/rs6000/linux64.h (OPTION_GLIBC_P, OPTION_UCLIBC_P, + OPTION_BIONIC_P, OPTION_MUSL_P): Define. + (OPTION_GLIBC, OPTION_UCLIBC, OPTION_BIONIC, OPTION_MUSL): Redefine + using OPTION_*_P macros. + * config/fuchsia.h (OPTION_MUSL_P): Redefine. + * config/glibc-stdint.h (OPTION_MUSL_P): Define if not defined. + * common/config/s390/s390-common.cc (s390_supports_split_stack): Re-add + ATTRIBUTE_UNUSED to opts parameter. If OPTION_GLIBC_P is defined, use + OPTION_GLIBC_P (opts) as condition, otherwise assume if (false). + * common/config/i386/i386-common.cc (ix86_supports_split_stack): If + OPTION_GLIBC_P is defined use !OPTION_GLIBC_P (opts) as condition, + otherwise assume if (true). + +2022-01-24 Kito Cheng <kito.cheng@sifive.com> + + * common/config/riscv/riscv-common.cc (riscv_subset_list::to_string): + Skip zicsr and zifencei if I-ext is 2.0. + +2022-01-24 Jia-Wei Chen <jiawei@iscas.ac.cn> + + * config.gcc: Modify default isa_spec version. + +2022-01-24 Jiufu Guo <guojiufu@linux.ibm.com> + + PR tree-optimization/102087 + * tree-ssa-loop-niter.cc (number_of_iterations_until_wrap): + Correct PLUS result type. + +2022-01-24 H.J. Lu <hjl.tools@gmail.com> + + PR target/104188 + * config/i386/predicates.md (bcst_mem_operand): Also check mode + of memory broadcast. + +2022-01-23 Andrew Pinski <apinski@marvell.com> + + PR target/64821 + * config/aarch64/aarch64-builtins.cc + (aarch64_general_gimple_fold_builtin): Handle + __builtin_aarch64_sqrt* and simplify into SQRT internal + function. + +2022-01-22 Jakub Jelinek <jakub@redhat.com> + + PR other/104176 + * opts-global.cc (handle_common_deferred_options): Quote + --enable-plugin in diagnostics to avoid -Werror=format-diag. + +2022-01-21 Michael Meissner <meissner@the-meissners.org> + + PR target/104136 + * config/rs6000/rs6000-protos.h (prefixed_xxsplti_p): Delete. + * config/rs6000/rs6000.cc (prefixed_xxsplti_p): Delete. + * config/rs6000/rs6000.md (prefixed attribute): Delete section + that sets the prefixed attribute for xxspltiw, xxspltidp, and + xxsplti32dx instructions. + (movsf_hardfloat): Explicitly set the prefixed attribute + when xxspltiw and xxspltidp instructions are generated. + (mov<mode>_hardfloat32): Likewise. + (mov<mode>_hardfloat64): Likewise. + * config/rs6000/vsx.md (vsx_mov<mode>_64bit): Explicitly set the + prefixed attribute for xxspltiw and xxspltidp instructions. + (vsx_mov<mode>_32bit): Likewise. + +2022-01-21 H.J. Lu <hjl.tools@gmail.com> + + PR bootstrap/104170 + * common/config/i386/i386-common.cc (ix86_supports_split_stack): + Return true only on glibc. + * config/i386/gnu-user-common.h (STACK_CHECK_STATIC_BUILTIN): + Revert commit c163647ffbc. + * config/i386/gnu.h (TARGET_LIBC_PROVIDES_SSP): Likewise. + +2022-01-21 Sören Tempel <soeren@soeren-tempel.net> + + * common/config/s390/s390-common.cc (s390_supports_split_stack): + Only support split-stack on glibc targets. + * config/i386/gnu-user-common.h (STACK_CHECK_STATIC_BUILTIN): Ditto. + * config/i386/gnu.h (defined): Ditto. + +2022-01-21 Bill Schmidt <wschmidt@linux.ibm.com> + + * config/rs6000/rs6000-overload.def (VEC_SLDW): Add instances for + vector float and vector double. + +2022-01-21 Bill Seurer <seurer@gcc.gnu.org> + + * config/rs6000/rs6000.cc (rs6000_get_function_versions_dispatcher): + Fix mention of ifunc in string. + +2022-01-21 Roger Sayle <roger@nextmovesoftware.com> + + PR middle-end/104140 + * tree-ssa-math-opts.cc (convert_mult_to_highpart): Check that the + operands of the widening multiplication are either both signed or + both unsigned, and abort the conversion if mismatched. + * doc/generic.texi (WIDEN_MULT_EXPR): Describe expression node. + (MULT_HIGHPART_EXPR): Clarify that operands must have the same + signedness. + * tree.def (MULT_HIGHPART_EXPR): Document both operands must have + integer types with the same precision and signedness. + (WIDEN_MULT_EXPR): Document that operands must have integer types + with the same precision, but possibly differing signedness. + * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Defend against + riscv_current_subset_list returning a NULL pointer (empty list). + +2022-01-21 Vladimir N. Makarov <vmakarov@redhat.com> + + PR target/103676 + * ira.h (struct target_ira): Add member + x_ira_exclude_class_mode_regs. + (ira_exclude_class_mode_regs): New macro. + * lra.h (lra_create_new_reg): Add arg exclude_start_hard_regs and + move from here ... + * lra-int.h: ... to here. + (lra_create_new_reg_with_unique_value): Add arg + exclude_start_hard_regs. + (class lra_reg): Add member exclude_start_hard_regs. + * lra-assigns.cc (find_hard_regno_for_1): Setup + impossible_start_hard_regs from exclude_start_hard_regs. + * lra-constraints.cc (get_reload_reg): Add arg exclude_start_hard_regs and pass + it lra_create_new_reg[_with_unique_value]. + (match_reload): Ditto. + (check_and_process_move): Pass NULL + exclude_start_hard_regs to lra_create_new_reg_with_unique_value. + (goal_alt_exclude_start_hard_regs): New static variable. + (process_addr_reg, simplify_operand_subreg): Pass NULL + exclude_start_hard_regs to lra_create_new_reg_with_unique_value + and get_reload_reg. + (process_alt_operands): Setup goal_alt_exclude_start_hard_regs. + Use this_alternative_exclude_start_hard_regs additionally to find + winning operand alternative. + (base_to_reg, base_plus_disp_to_reg, index_part_to_reg): Pass NULL + exclude_start_hard_regs to lra_create_new_reg. + (process_address_1, emit_inc): Ditto. + (curr_insn_transform): Pass exclude_start_hard_regs value to + lra_create_new_reg, get_reload_reg, match_reload. + (inherit_reload_reg, split_reg): Pass NULL exclude_start_hard_regs + to lra_create_new_reg. + (process_invariant_for_inheritance): Ditto. + * lra-remat.cc (update_scratch_ops): Ditto. + * lra.cc (lra_create_new_reg_with_unique_value): Add arg + exclude_start_hard_regs. Setup the corresponding member of + lra reg info. + (lra_create_new_reg): Add arg exclude_start_hard_regs and pass it + to lra_create_new_reg_with_unique_value. + (initialize_lra_reg_info_element): Initialize member + exclude_start_hard_regs. + (get_scratch_reg): Pass NULL to lra_create_new_reg. + * ira.cc (setup_prohibited_class_mode_regs): Rename to + setup_prohibited_and_exclude_class_mode_regs and calculate + ira_exclude_class_mode_regs. + +2022-01-21 Martin Liska <mliska@suse.cz> + + * configure.ac: Detect ld_is_mold and use it for + comdat_group=yes and gcc_cv_ld_hidden=yes. + * configure: Regenerate. + +2022-01-21 Richard Biener <rguenther@suse.de> + + PR tree-optimization/100089 + * tree-vect-slp.cc (vect_slp_region): Reject BB vectorization + of if-converted loops with unvectorized COND_EXPRs for + all but the unlimited cost models. + +2022-01-21 Ard Biesheuvel <ardb@kernel.org> + + * config/arm/arm-opts.h (enum stack_protector_guard): New. + * config/arm/arm-protos.h (arm_stack_protect_tls_canary_mem): + New. + * config/arm/arm.cc (TARGET_STACK_PROTECT_GUARD): Define. + (arm_option_override_internal): Handle and put in error checks. + for stack protector guard options. + (arm_option_reconfigure_globals): Likewise. + (arm_stack_protect_tls_canary_mem): New. + (arm_stack_protect_guard): New. + * config/arm/arm.md (stack_protect_set): New. + (stack_protect_set_tls): Likewise. + (stack_protect_test): Likewise. + (stack_protect_test_tls): Likewise. + (reload_tp_hard): Likewise. + * config/arm/arm.opt (-mstack-protector-guard): New + (-mstack-protector-guard-offset): New. + * doc/invoke.texi: Document new options. + +2022-01-21 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104156 + * tree-ssa-loop-unswitch.cc (tree_unswitch_outer_loop): + Collect and reset debug stmts with out-of-loop uses when + hoisting guards. + (find_loop_guard): Adjust. + (empty_bb_without_guard_p): Likewise. Ignore debug stmts. + (used_outside_loop_p): Push debug uses to a vector of + debug stmts to reset. + (hoist_guard): Adjust -fopt-info category. + +2022-01-21 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104152 + * tree-vect-slp.cc (vect_build_slp_tree_2): Add missing + can_duplicate_and_interleave_p check. + +2022-01-21 Jakub Jelinek <jakub@redhat.com> + + * gimple-ssa-warn-access.cc (pass_waccess::warn_invalid_pointer): + Avoid passing var to warning_at when the format string doesn't + refer to it. + +2022-01-21 Aldy Hernandez <aldyh@redhat.com> + + PR tree-optimization/103721 + * gimple-range-path.cc + (path_range_query::relations_may_be_invalidated): New. + (path_range_query::compute_ranges_in_block): Reset relations if + they may be invalidated. + (path_range_query::maybe_register_phi_relation): Exit if relations + may be invalidated on incoming edge. + (path_range_query::compute_phi_relations): Pass incoming PHI edge + to maybe_register_phi_relation. + * gimple-range-path.h (relations_may_be_invalidated): New. + (maybe_register_phi_relation): Pass edge instead of tree. + * tree-ssa-threadbackward.cc (back_threader::back_threader): + Mark DFS edges. + * value-relation.cc (path_oracle::path_oracle): Call + mark_dfs_back_edges. + (path_oracle::register_relation): Add SSA names to m_registered + bitmap. + (path_oracle::reset_path): Clear m_registered bitmap. + * value-relation.h (path_oracle::set_root_oracle): New. + +2022-01-21 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/102478 + * optabs.cc (prepare_cmp_insn): If !can_create_pseudo_p (), don't + force_reg constants and for -fnon-call-exceptions fail if copy_to_reg + would be needed. + +2022-01-20 Richard Biener <rguenther@suse.de> + + PR middle-end/100786 + * gimple-fold.cc (get_symbol_constant_value): Only return + values of compatible type to the symbol. + +2022-01-20 Andrew MacLeod <amacleod@redhat.com> + + * value-relation.cc (relation_oracle::valid_equivs): Query and add + if valid members of a set. + (equiv_oracle::register_equiv): Call valid_equivs rather than + bitmap direct operations. + (path_oracle::register_equiv): Ditto. + * value-relation.h (relation_oracle::valid_equivs): New prototype. + +2022-01-20 Richard Biener <rguenther@suse.de> + + PR target/100784 + * config/i386/i386.cc (ix86_gimple_fold_builtin): Check for + LHS before folding __builtin_ia32_shufpd and friends. + +2022-01-20 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/crypto.md (aes_op_protect): Allow moves from core + registers and from memory. + (aes_op_protect_misalign_load): New pattern. + (aes_op_protect_neon_vld1v16qi): New pattern. + +2022-01-20 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/crypto.md (crypto_<CRYPTO_AESMC:crypto_pattern>_protected): + New pattern. + (aarch32_crypto_aese_fused_protected): Likewise. + (aarch32_crypto_aesd_fused_protected): Likewise. + +2022-01-20 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/crypto.md (crypto_<CRYPTO_AES:crypto_pattern>): Convert + to define_expand. Add mitigation for the Cortex-A AES erratum + when enabled. + (*crypto_<CRYPTO_AES:crypto_pattern>_insn): New pattern, based + on original crypto_<CRYPTO_AES:crypto_pattern> insn. + (aes_op_protect): New pattern. + * config/arm/unspecs.md (unspec): Add UNSPEC_AES_PROTECT. + +2022-01-20 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/arm-cpus.in (quirk_aes_1742098): New quirk feature + (ALL_QUIRKS): Add it. + (cortex-a57, cortex-a72): Enable it. + (cortex-a57.cortex-a53, cortex-a72.cortex-a53): Likewise. + * config/arm/arm.opt (mfix-cortex-a57-aes-1742098): New command-line + option. + (mfix-cortex-a72-aes-1655431): New option alias. + * config/arm/arm.cc (arm_option_override): Handle default settings + for AES erratum switch. + * doc/invoke.texi (Arm Options): Document new options. + +2022-01-20 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/crypto.md (crypto_<CYRPTO_AES:crypto_pattern>): Use + <crypto_mode> rather than hard-coding the mode. + (crypto_<CRYPTO_AESMC:crypto_pattern>): Fix white space. + (crypto_<CRYPTO_AES:crypto_pattern>): Likewise. + (*aarch32_crypto_aese_fused): Likewise. + (*aarch32_crypto_aesd_fused): Likewise. + (crypto_<CRYPTO_BINARY:crypto_pattern>): Likewise. + (crypto_<CRYPTO_TERNARY:crypto_pattern>): Likewise. + (crypto_sha1h_lb): Likewise. + (crypto_vmullp64): Likewise. + (crypto_<CRYPTO_SELECTING:crypto_pattern>): Likewise. + (crypto_<CRYPTO_SELECTING:crypto_pattern>_lb): Likewise. + +2022-01-20 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/crypto.md (crypto_<CRYPTO_AESMC:crypto_pattern>): Add + iterator to pattern name to disambiguate. + (crypto_<CRYPTO_AES:crypto_pattern>): Likewise. + (crypto_<CRYPTO_BINARY:crypto_pattern>): Likewise. + (crypto_<CRYPTO_TERNARY:crypto_pattern>): Likewise. + (crypto_<CRYPTO_SELECTING:crypto_pattern>): Likewise. + (crypto_<CRYPTO_SELECTING:crypto_pattern>_lb): Likewise. + +2022-01-20 Martin Liska <mliska@suse.cz> + + PR bootstrap/104135 + * emit-rtl.cc (make_insn_raw): Fix -Wformat-diag warnings. + * rtl.cc: Partially disable -Wformat-diag for RTL checking + error messages. + +2022-01-20 Jakub Jelinek <jakub@redhat.com> + + PR debug/103874 + * dwarf2out.cc (index_rnglists): For !HAVE_AS_LEB128 and + block_num > 0, index entry even if !have_multiple_function_sections. + +2022-01-20 liuhongt <hongtao.liu@intel.com> + + PR target/103771 + * tree-vect-stmts.cc (supportable_narrowing_operation): Enhance + integral mode mask pack by multi steps which takes + vec_pack_sbool_trunc_optab as start when elements number is + less than BITS_PER_UNITS. + +2022-01-20 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104114 + * tree-vect-generic.cc (expand_vector_piecewise): Do not diagnose + single element vector decomposition. + +2022-01-19 Robin Dapp <rdapp@linux.ibm.com> + + * ifcvt.cc (noce_convert_multiple_sets_1): New function. + (noce_convert_multiple_sets): Call function a second time if we can + improve the first try. + +2022-01-19 Robin Dapp <rdapp@linux.ibm.com> + + * ifcvt.cc (cond_exec_get_condition): New parameter to allow getting the + reversed comparison. + (try_emit_cmove_seq): New function to facilitate creating a cmov + sequence. + (noce_convert_multiple_sets): Create two sequences and use the less + expensive one. + +2022-01-19 Robin Dapp <rdapp@linux.ibm.com> + + * rtl.h (struct rtx_comparison): New struct that holds an rtx + comparison. + * config/rs6000/rs6000.cc (rs6000_emit_minmax): Use struct instead of + single parameters. + (rs6000_emit_swsqrt): Likewise. + * expmed.cc (expand_sdiv_pow2): Likewise. + (emit_store_flag): Likewise. + * expr.cc (expand_cond_expr_using_cmove): Likewise. + (expand_expr_real_2): Likewise. + * ifcvt.cc (noce_emit_cmove): Add compare and reversed compare + parameters. + * optabs.cc (emit_conditional_move_1): New function. + (expand_doubleword_shift_condmove): Use struct. + (emit_conditional_move): Use struct and allow to call directly + without going through preparation steps. + * optabs.h (emit_conditional_move): Use struct. + +2022-01-19 Robin Dapp <rdapp@linux.ibm.com> + + * ifcvt.cc (bb_ok_for_noce_convert_multiple_sets): Estimate insns costs. + (noce_process_if_block): Use potential costs. + +2022-01-19 Robin Dapp <rdapp@linux.ibm.com> + + * ifcvt.cc (noce_convert_multiple_sets): Allow constants. + (bb_ok_for_noce_convert_multiple_sets): Likewise. + +2022-01-19 Robin Dapp <rdapp@linux.ibm.com> + + * ifcvt.cc (need_cmov_or_rewire): New function. + (noce_convert_multiple_sets): Call it. + +2022-01-19 David Malcolm <dmalcolm@redhat.com> + + * attribs.cc (attribute_c_tests): Rename to... + (attribs_cc_tests): ...this. + * bitmap.cc (bitmap_c_tests): Rename to... + (bitmap_cc_tests): ...this. + * cgraph.cc (cgraph_c_finalize): Rename to... + (cgraph_cc_finalize): ...this. + (cgraph_c_tests): Rename to... + (cgraph_cc_tests): ...this. + * cgraph.h (cgraph_c_finalize): Rename to... + (cgraph_cc_finalize): ...this. + (cgraphunit_c_finalize): Rename to... + (cgraphunit_cc_finalize): ...this. + * cgraphunit.cc (cgraphunit_c_finalize): Rename to... + (cgraphunit_cc_finalize): ...this. + * convert.cc (convert_c_tests): Rename to... + (convert_cc_tests): ...this. + * dbgcnt.cc (dbgcnt_c_tests): Rename to... + (dbgcnt_cc_tests): ...this. + * diagnostic-show-locus.cc (diagnostic_show_locus_c_tests): Rename to... + (diagnostic_show_locus_cc_tests): ...this. + * diagnostic.cc (diagnostic_c_tests): Rename to... + (diagnostic_cc_tests): ...this. + * dumpfile.cc (dumpfile_c_tests): Rename to... + (dumpfile_cc_tests): ...this. + * dwarf2out.cc (dwarf2out_c_finalize): Rename to... + (dwarf2out_cc_finalize): ...this. + * dwarf2out.h (dwarf2out_c_finalize): Rename to... + (dwarf2out_cc_finalize): ...this. + * edit-context.cc (edit_context_c_tests): Rename to... + (edit_context_cc_tests): ...this. + * et-forest.cc (et_forest_c_tests): Rename to... + (et_forest_cc_tests): ...this. + * fibonacci_heap.cc (fibonacci_heap_c_tests): Rename to... + (fibonacci_heap_cc_tests): ...this. + * fold-const.cc (fold_const_c_tests): Rename to... + (fold_const_cc_tests): ...this. + * function-tests.cc (function_tests_c_tests): Rename to... + (function_tests_cc_tests): ...this. + * gcse.cc (gcse_c_finalize): Rename to... + (gcse_cc_finalize): ...this. + * gcse.h (gcse_c_finalize): Rename to... + (gcse_cc_finalize): ...this. + * ggc-tests.cc (ggc_tests_c_tests): Rename to... + (ggc_tests_cc_tests): ...this. + * gimple-ssa-store-merging.cc (store_merging_c_tests): Rename to... + (store_merging_cc_tests): ...this. + * gimple.cc (gimple_c_tests): Rename to... + (gimple_cc_tests): ...this. + * hash-map-tests.cc (hash_map_tests_c_tests): Rename to... + (hash_map_tests_cc_tests): ...this. + * hash-set-tests.cc (hash_set_tests_c_tests): Rename to... + (hash_set_tests_cc_tests): ...this. + * input.cc (input_c_tests): Rename to... + (input_cc_tests): ...this. + * ipa-cp.cc (ipa_cp_c_finalize): Rename to... + (ipa_cp_cc_finalize): ...this. + * ipa-fnsummary.cc (ipa_fnsummary_c_finalize): Rename to... + (ipa_fnsummary_cc_finalize): ...this. + * ipa-fnsummary.h (ipa_fnsummary_c_finalize): Rename to... + (ipa_fnsummary_cc_finalize): ...this. + * ipa-modref-tree.cc (ipa_modref_tree_c_tests): Rename to... + (ipa_modref_tree_cc_tests): ...this. + * ipa-modref-tree.h (modref_c_tests): Delete bogus decl. + * ipa-modref.cc (ipa_modref_c_finalize): Rename to... + (ipa_modref_cc_finalize): ...this. + * ipa-modref.h (ipa_modref_c_finalize): Rename to... + (ipa_modref_cc_finalize): ...this. + * ipa-prop.h (ipa_cp_c_finalize): Rename to... + (ipa_cp_cc_finalize): ...this. + * ipa-reference.cc (ipa_reference_c_finalize): Rename to... + (ipa_reference_cc_finalize): ...this. + * ipa-reference.h (ipa_reference_c_finalize): Rename to... + (ipa_reference_cc_finalize): ...this. + * ira-costs.cc (ira_costs_c_finalize): Rename to... + (ira_costs_cc_finalize): ...this. + * ira.h (ira_costs_c_finalize): Rename to... + (ira_costs_cc_finalize): ...this. + * opt-suggestions.cc (opt_proposer_c_tests): Rename to... + (opt_suggestions_cc_tests): ...this. + * opts.cc (opts_c_tests): Rename to... + (opts_cc_tests): ...this. + * predict.cc (predict_c_tests): Rename to... + (predict_cc_tests): ...this. + * pretty-print.cc (pretty_print_c_tests): Rename to... + (pretty_print_cc_tests): ...this. + * read-rtl-function.cc (read_rtl_function_c_tests): Rename to... + (read_rtl_function_cc_tests): ...this. + * rtl-tests.cc (rtl_tests_c_tests): Rename to... + (rtl_tests_cc_tests): ...this. + * sbitmap.cc (sbitmap_c_tests): Rename to... + (sbitmap_cc_tests): ...this. + * selftest-run-tests.cc (selftest::run_tests): Update calls for + _c_ to _cc_ function renamings; fix names of attribs and + opt-suggestions tests. + * selftest.cc (selftest_c_tests): Rename to... + (selftest_cc_tests): ...this. + * selftest.h (attribute_c_tests): Rename to... + (attribs_cc_tests): ...this. + (bitmap_c_tests): Rename to... + (bitmap_cc_tests): ...this. + (cgraph_c_tests): Rename to... + (cgraph_cc_tests): ...this. + (convert_c_tests): Rename to... + (convert_cc_tests): ...this. + (diagnostic_c_tests): Rename to... + (diagnostic_cc_tests): ...this. + (diagnostic_show_locus_c_tests): Rename to... + (diagnostic_show_locus_cc_tests): ...this. + (dumpfile_c_tests): Rename to... + (dumpfile_cc_tests): ...this. + (edit_context_c_tests): Rename to... + (edit_context_cc_tests): ...this. + (et_forest_c_tests): Rename to... + (et_forest_cc_tests): ...this. + (fibonacci_heap_c_tests): Rename to... + (fibonacci_heap_cc_tests): ...this. + (fold_const_c_tests): Rename to... + (fold_const_cc_tests): ...this. + (function_tests_c_tests): Rename to... + (function_tests_cc_tests): ...this. + (ggc_tests_c_tests): Rename to... + (ggc_tests_cc_tests): ...this. + (gimple_c_tests): Rename to... + (gimple_cc_tests): ...this. + (hash_map_tests_c_tests): Rename to... + (hash_map_tests_cc_tests): ...this. + (hash_set_tests_c_tests): Rename to... + (hash_set_tests_cc_tests): ...this. + (input_c_tests): Rename to... + (input_cc_tests): ...this. + (opts_c_tests): Rename to... + (opts_cc_tests): ...this. + (predict_c_tests): Rename to... + (predict_cc_tests): ...this. + (pretty_print_c_tests): Rename to... + (pretty_print_cc_tests): ...this. + (read_rtl_function_c_tests): Rename to... + (read_rtl_function_cc_tests): ...this. + (rtl_tests_c_tests): Rename to... + (rtl_tests_cc_tests): ...this. + (sbitmap_c_tests): Rename to... + (sbitmap_cc_tests): ...this. + (selftest_c_tests): Rename to... + (selftest_cc_tests): ...this. + (simplify_rtx_c_tests): Rename to... + (simplify_rtx_cc_tests): ...this. + (spellcheck_c_tests): Rename to... + (spellcheck_cc_tests): ...this. + (spellcheck_tree_c_tests): Rename to... + (spellcheck_tree_cc_tests): ...this. + (sreal_c_tests): Rename to... + (sreal_cc_tests): ...this. + (store_merging_c_tests): Rename to... + (store_merging_cc_tests): ...this. + (tree_c_tests): Rename to... + (tree_cc_tests): ...this. + (tree_cfg_c_tests): Rename to... + (tree_cfg_cc_tests): ...this. + (typed_splay_tree_c_tests): Rename to... + (typed_splay_tree_cc_tests): ...this. + (vec_c_tests): Rename to... + (vec_cc_tests): ...this. + (vec_perm_indices_c_tests): Rename to... + (vec_perm_indices_cc_tests): ..this. + (opt_proposer_c_tests): Rename to... + (opt_suggestions_cc_tests): ...this. + (dbgcnt_c_tests): Rename to... + (dbgcnt_cc_tests): ...this. + (ipa_modref_tree_c_tests): Rename to... + (ipa_modref_tree_cc_tests): ...this. + * simplify-rtx.cc (simplify_rtx_c_tests): Rename to... + (simplify_rtx_cc_tests): ...this. + * spellcheck-tree.cc (spellcheck_tree_c_tests): Rename to... + (spellcheck_tree_cc_tests): ...this. + * spellcheck.cc (spellcheck_c_tests): Rename to... + (spellcheck_cc_tests): ...this. + * sreal.cc (sreal_c_tests): Rename to... + (sreal_cc_tests): ...this. + * toplev.cc (toplev::finalize): Update calls for _c_ to _cc_ + function renamings. + * tree-cfg.cc (tree_cfg_c_tests): Rename to... + (tree_cfg_cc_tests): ...this. + * tree.cc (tree_c_tests): Rename to... + (tree_cc_tests): ...this. + * typed-splay-tree.cc (typed_splay_tree_c_tests): Rename to... + (typed_splay_tree_cc_tests): ...this. + * vec-perm-indices.cc (vec_perm_indices_c_tests): Rename to... + (vec_perm_indices_cc_tests): ...this. + * vec.cc (vec_c_tests): Rename to... + (vec_cc_tests): ...this. + +2022-01-19 Andre Vieira <andre.simoesdiasvieira@arm.com> + + PR tree-optimization/103997 + * tree-vect-loop.cc (vect_analyze_loop): Fix mode skipping for epilogue + vectorization. + +2022-01-19 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/102860 + * match.pd (x %[fl] y -> x % y): New simplification for + unsigned integral types. + * optabs-tree.cc (optab_for_tree_code): Return unknown_optab + for {CEIL,FLOOR,ROUND}_{DIV,MOD}_EXPR with VECTOR_TYPE. + +2022-01-19 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104112 + * tree-vect-loop.cc (vect_find_reusable_accumulator): Check + for required intermediate vector types. + +2022-01-19 Jakub Jelinek <jakub@redhat.com> + + * config/rs6000/rs6000.cc (rs6000_machine_from_flags): Add default:. + +2022-01-19 Martin Liska <mliska@suse.cz> + + * configure.ac: Remove -Wno-error=format-diag. + * configure: Regenerate. + +2022-01-19 Martin Liska <mliska@suse.cz> + + * config/riscv/riscv.cc (riscv_handle_type_attribute): + Update one -Wformat-diag string in warning message. + +2022-01-19 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/104103 + * gimple-ssa-warn-access.cc (pass_waccess::check_call): Don't check + .ASAN_MARK calls. + +2022-01-19 Jakub Jelinek <jakub@redhat.com> + + PR c++/89074 + * fold-const.cc (address_compare): Consider different STRING_CSTs + with the same lengths that memcmp the same as equal, not different. + +2022-01-19 Jakub Jelinek <jakub@redhat.com> + + * config/i386/sse.md (*aes<aeswideklvariant>u*): Use %0 instead of + {%0}. + +2022-01-19 Martin Liska <mliska@suse.cz> + Thomas Schwinge <thomas@codesourcery.com> + + * config/nvptx/nvptx.cc (nvptx_goacc_validate_dims_1): Update + warning messages. + +2022-01-19 Sebastian Huber <sebastian.huber@embedded-brains.de> + + PR target/104090 + * config/rs6000/rs6000.cc (rs6000_machine_from_flags): Use also + rs6000_cpu. + +2022-01-19 Jakub Jelinek <jakub@redhat.com> + + PR target/104104 + * config/i386/sse.md + (<avx512>_<complexopname>_<mode><maskc_name><round_name>, + avx512fp16_<complexopname>sh_v8hf<mask_scalarc_name><round_scalarcz_name>, + avx512dq_mul<mode>3<mask_name>, <avx2_avx512>_permvar<mode><mask_name>, + avx2_perm<mode>_1<mask_name>, avx512f_perm<mode>_1<mask_name>, + avx512dq_rangep<mode><mask_name><round_saeonly_name>, + avx512dq_ranges<mode><mask_scalar_name><round_saeonly_scalar_name>, + <avx512>_getmant<mode><mask_name><round_saeonly_name>, + avx512f_vgetmant<mode><mask_scalar_name><round_saeonly_scalar_name>): + Use vxorps\t%x0, %x0, %x0 instead of vxorps\t{%x0, %x0, %x0}. + +2022-01-19 Martin Sebor <msebor@redhat.com> + + PR middle-end/104069 + * gimple-ssa-warn-access.cc (pointers_related_p): Return false for + an unknown result as documented. + +2022-01-18 Andrew Pinski <apinski@marvell.com> + + * ipa-split.cc (visit_bb): Fix comment before the + warning/error attribute checking code. + +2022-01-18 David Faust <david.faust@oracle.com> + + * config/bpf/coreout.cc (bpf_core_reloc_add): Do not account + for base strtab offset yet as it may change. + (output_asm_btfext_core_reloc): Do so here instead. + (output_btfext_core_sections): Likewise. + +2022-01-18 David Faust <david.faust@oracle.com> + + * config/bpf/coreout.cc (output_btfext_header): Account for + 4-byte record size in core_relo_len. + (output_btfext_core_sections): Only write record size once. + * config/bpf/coreout.h (btf_ext_section_header): Delete unused + member. + +2022-01-18 Maciej W. Rozycki <macro@embecosm.com> + + * common/config/riscv/riscv-common.cc + (riscv_subset_list::parse_multiletter_ext): Move pointer + arithmetic ahead of `free'. + +2022-01-18 Jason Merrill <jason@redhat.com> + + PR c++/104007 + * gimplify.cc (gimple_push_cleanup): Handle eh_only in conditional + context. + +2022-01-18 Sandra Loosemore <sandra@codesourcery.com> + + PR middle-end/103163 + * emit-rtl.cc (init_emit_regs): Initialize stack_limit_rtx here... + (init_emit_once): ...not here. + +2022-01-18 Martin Liska <mliska@suse.cz> + + * collect2.cc (scan_libraries): Fix -Wformat-diag issues. + * config/aarch64/aarch64-builtins.cc (aarch64_simd_expand_builtin): Likewise. + * config/arc/arc.md: Likewise. + * config/avr/avr.cc (avr_section_type_flags): Likewise. + * config/bfin/bfin.cc (bfin_option_override): Likewise. + (bfin_handle_longcall_attribute): Likewise. + * config/cris/cris.h (FUNCTION_PROFILER): Likewise. + * config/frv/frv.cc (frv_expand_builtin): Likewise. + * config/ia64/ia64-c.cc (ia64_hpux_handle_builtin_pragma): Likewise. + * config/iq2000/iq2000.cc (save_restore_insns): Likewise. + (iq2000_print_operand_address): Likewise. + (iq2000_print_operand): Likewise. + * config/m32c/m32c-pragma.cc (m32c_pragma_memregs): Likewise. + (m32c_pragma_address): Likewise. + * config/m68k/m68k.cc (m68k_handle_fndecl_attribute): Likewise. + * config/mips/mips.cc (mips_handle_interrupt_attr): Likewise. + (mips_set_compression_mode): Likewise. + * config/mmix/mmix.cc (mmix_function_profiler): Likewise. + (mmix_print_operand): Likewise. + (mmix_output_shiftvalue_op_from_str): Likewise. + (mmix_output_shifted_value): Likewise. + * config/msp430/driver-msp430.cc (msp430_select_hwmult_lib): Likewise. + * config/msp430/msp430.cc (msp430_option_override): Likewise. + (msp430_attr): Likewise. + (msp430_expand_delay_cycles): Likewise. + (msp430_expand_builtin): Likewise. + * config/rs6000/aix73.h: Likewise. + * config/rs6000/rtems.h (INVALID_64BIT): Likewise. + * config/rx/rx.cc (rx_expand_builtin_mvtc): Likewise. + (valid_psw_flag): Likewise. + * config/sh/sh.cc (parse_validate_atomic_model_option): Likewise. + * config/stormy16/stormy16.cc (xstormy16_function_profiler): Likewise. + (xstormy16_expand_builtin_va_start): Likewise. + (xstormy16_handle_below100_attribute): Likewise. + +2022-01-18 Martin Liska <mliska@suse.cz> + + * config/vms/vms-c.cc (vms_pragma_nostandard): Fix -Wformat-diag + warning. + (vms_pragma_standard): Likewise. + (vms_pragma_extern_prefix): Likewise. + +2022-01-18 Martin Liska <mliska@suse.cz> + + * config/xtensa/xtensa.cc (print_operand): Fix warnings. + (print_operand_address): Likewise. + (xtensa_multibss_section_type_flags): Likewise. + +2022-01-18 Martin Liska <mliska@suse.cz> + + * config/rs6000/rs6000-call.cc (rs6000_invalid_builtin): Change + wording of an error message. + +2022-01-18 Martin Liska <mliska@suse.cz> + + * config/v850/v850-c.cc (pop_data_area): Fix -Wformat-diag + warning. + (ghs_pragma_section): Likewise. + (ghs_pragma_interrupt): Likewise. + (ghs_pragma_starttda): Likewise. + (ghs_pragma_startsda): Likewise. + (ghs_pragma_startzda): Likewise. + (ghs_pragma_endtda): Likewise. + (ghs_pragma_endsda): Likewise. + (ghs_pragma_endzda): Likewise. + +2022-01-18 Martin Liska <mliska@suse.cz> + + * config/nds32/nds32-intrinsic.cc (nds32_expand_builtin_impl): + Fix warnings. + * config/nds32/nds32-intrinsic.md: Likewise. + * config/nds32/nds32-isr.cc (nds32_check_isr_attrs_conflict): Likewise. + * config/nds32/nds32.cc (nds32_print_operand): Likewise. + (nds32_insert_attributes): Likewise. + +2022-01-18 Martin Liska <mliska@suse.cz> + + * config/nvptx/nvptx.cc (nvptx_goacc_validate_dims_1): Wrap + keyword. + * config/nvptx/nvptx.md: Remove trailing dot. + +2022-01-18 Martin Liska <mliska@suse.cz> + + * common/config/riscv/riscv-common.cc (riscv_subset_list::add): + Wrap keywords with quotes and remove trailing dots. + (riscv_subset_list::parsing_subset_version): Likewise. + (riscv_subset_list::parse_std_ext): Likewise. + (riscv_subset_list::parse_multiletter_ext): Likewise. + * config/riscv/riscv.cc (riscv_handle_type_attribute): Likewise. + +2022-01-18 Andre Vieira <andre.simoesdiasvieira@arm.com> + + * tree-vect-loop.cc (vect_estimate_min_profitable_iters): Pass new + argument suggested_unroll_factor. + (vect_analyze_loop_costing): Likewise. + (_loop_vec_info::_loop_vec_info): Initialize new member + suggested_unroll_factor. + (vect_determine_partial_vectors_and_peeling): Make epilogue of unrolled + main loop use partial vectors. + (vect_analyze_loop_2): Pass and use new argument + suggested_unroll_factor. + (vect_analyze_loop_1): Change to intialize local + suggested_unroll_factor and use it. + (vectorizable_reduction): Don't use single_defuse_cycle when unrolling. + * tree-vectorizer.h (_loop_vec_info::_loop_vec_info): Add new member + suggested_unroll_factor. + (vector_costs::vector_costs): Add new member m_suggested_unroll_factor. + (vector_costs::suggested_unroll_factor): New getter function. + (finish_cost): Set return argument suggested_unroll_factor. + +2022-01-18 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/104038 + * doc/invoke.texi (relation-block-limit): New. + * params.opt (relation-block-limit): New. + * value-relation.cc (dom_oracle::register_relation): Check for NULL + record before invoking transitive registery. + (dom_oracle::set_one_relation): Check limit before creating record. + (dom_oracle::register_transitives): Stop when no record created. + * value-relation.h (relation_chain_head::m_num_relations): New. + +2022-01-18 Richard Biener <rguenther@suse.de> + + PR ipa/103989 + * ipa-inline.cc (inline_small_functions): Do not enqueue call + edges originating in functions compiled with -Og. + +2022-01-18 Richard Biener <rguenther@suse.de> + + PR ipa/103989 + * passes.def (pass_all_optimizations_g): Remove pass_modref + and pass_local_pure_const. + +2022-01-18 Martin Liska <mliska@suse.cz> + + * config/s390/s390.cc: Fix -Wformat-diag warnings. + +2022-01-18 Martin Liska <mliska@suse.cz> + + * config/s390/s390-c.cc (s390_expand_overloaded_builtin): Wrap + keyword in quotes. + (s390_resolve_overloaded_builtin): Remove trailing dot. + * config/s390/s390.cc (s390_const_operand_ok): Use - for range. + (s390_expand_builtin): Remove trailing dot. + (s390_emit_prologue): Likewise, use semicolon. + (s390_option_override_internal): Update keyword. + * varasm.cc (do_assemble_alias): Wrap keyword in quotes. + +2022-01-18 Martin Liska <mliska@suse.cz> + + * config/rs6000/rs6000-call.cc (rs6000_expand_builtin): Wrap + keywords and use %qs instead of %<%s%>. + +2022-01-18 Richard Biener <rguenther@suse.de> + + PR tree-optimization/103987 + * tree-ssa-dse.cc (dse_optimize_call): Properly guard modref + query with a pointer check. + +2022-01-18 Richard Sandiford <richard.sandiford@arm.com> + + PR target/104005 + * config/aarch64/aarch64.cc (aarch64_check_consecutive_mems): + When using MEM_EXPR, require the base to be a decl. + +2022-01-18 Richard Biener <rguenther@suse.de> + + * cgraph.h (struct cgraph_simd_clone_arg): Re-arrange fields to + avoid padding. + * function.h (struct function): Likewise. + +2022-01-18 Arnaud Charlet <charlet@adacore.com> + + * doc/install.texi: Update prerequisites for GNAT + +2022-01-18 Andrew Pinski <apinski@marvell.com> + + PR tree-optimization/101941 + * ipa-split.cc (visit_bb): Disallow function calls where + the function has either error or warning attribute. + +2022-01-18 Richard Biener <rguenther@suse.de> + + PR tree-optimization/104064 + * tree-vect-data-refs.cc (vect_analyze_data_ref_accesses): Check + DR_INIT fits in a signed HWI, represent the difference from the + first DR in unsigned. + +2022-01-17 Martin Liska <mliska@suse.cz> + + * Makefile.in: Rename .c names to .cc. + * config.gcc: Likewise. + * configure: Regenerate. Likewise. + * configure.ac: Likewise. + * gengtype.cc (set_gc_used): Likewise. + (source_dot_c_frul): Likewise. + (source_dot_cc_frul): Likewise. + (struct file_rule_st): Likewise. + (close_output_files): Likewise. + * config/avr/t-avr: Use CXXFLAGS_* and CXX_FOR_BUILD. + +2022-01-17 Martin Liska <mliska@suse.cz> + + * Makefile.in: Rename .c names to .cc. + * alias.h: Likewise. + * asan.cc: Likewise. + * auto-profile.h: Likewise. + * basic-block.h (struct basic_block_d): Likewise. + * btfout.cc: Likewise. + * builtins.cc (expand_builtin_longjmp): Likewise. + (validate_arg): Likewise. + (access_ref::offset_bounded): Likewise. + * caller-save.cc (reg_restore_code): Likewise. + (setup_save_areas): Likewise. + * calls.cc (initialize_argument_information): Likewise. + (expand_call): Likewise. + (emit_library_call_value_1): Likewise. + * cfg-flags.def (RTL): Likewise. + (SIBCALL): Likewise. + (CAN_FALLTHRU): Likewise. + * cfganal.cc (post_order_compute): Likewise. + * cfgcleanup.cc (try_simplify_condjump): Likewise. + (merge_blocks_move_predecessor_nojumps): Likewise. + (merge_blocks_move_successor_nojumps): Likewise. + (merge_blocks_move): Likewise. + (old_insns_match_p): Likewise. + (try_crossjump_bb): Likewise. + * cfgexpand.cc (expand_gimple_stmt): Likewise. + * cfghooks.cc (split_block_before_cond_jump): Likewise. + (profile_record_check_consistency): Likewise. + * cfghooks.h: Likewise. + * cfgrtl.cc (pass_free_cfg::execute): Likewise. + (rtl_can_merge_blocks): Likewise. + (try_redirect_by_replacing_jump): Likewise. + (make_pass_outof_cfg_layout_mode): Likewise. + (cfg_layout_can_merge_blocks_p): Likewise. + * cgraph.cc (release_function_body): Likewise. + (cgraph_node::get_fun): Likewise. + * cgraph.h (struct cgraph_node): Likewise. + (asmname_hasher::equal): Likewise. + (cgraph_inline_failed_type): Likewise. + (thunk_adjust): Likewise. + (dump_callgraph_transformation): Likewise. + (record_references_in_initializer): Likewise. + (ipa_discover_variable_flags): Likewise. + * cgraphclones.cc (GTY): Likewise. + * cgraphunit.cc (symbol_table::finalize_compilation_unit): Likewise. + * collect-utils.h (GCC_COLLECT_UTILS_H): Likewise. + * collect2-aix.h (GCC_COLLECT2_AIX_H): Likewise. + * collect2.cc (maybe_run_lto_and_relink): Likewise. + * combine-stack-adj.cc: Likewise. + * combine.cc (setup_incoming_promotions): Likewise. + (combine_simplify_rtx): Likewise. + (count_rtxs): Likewise. + * common.opt: Likewise. + * common/config/aarch64/aarch64-common.cc: Likewise. + * common/config/arm/arm-common.cc (arm_asm_auto_mfpu): Likewise. + * common/config/avr/avr-common.cc: Likewise. + * common/config/i386/i386-isas.h (struct _isa_names_table): Likewise. + * conditions.h: Likewise. + * config.gcc: Likewise. + * config/aarch64/aarch64-builtins.cc (aarch64_resolve_overloaded_memtag): Likewise. + * config/aarch64/aarch64-protos.h (aarch64_classify_address): Likewise. + (aarch64_get_extension_string_for_isa_flags): Likewise. + * config/aarch64/aarch64-sve-builtins.cc (function_builder::add_function): Likewise. + * config/aarch64/aarch64.cc (aarch64_regmode_natural_size): Likewise. + (aarch64_sched_first_cycle_multipass_dfa_lookahead): Likewise. + (aarch64_option_valid_attribute_p): Likewise. + (aarch64_short_vector_p): Likewise. + (aarch64_float_const_representable_p): Likewise. + * config/aarch64/aarch64.h (DBX_REGISTER_NUMBER): Likewise. + (ASM_OUTPUT_POOL_EPILOGUE): Likewise. + (GTY): Likewise. + * config/aarch64/cortex-a57-fma-steering.cc: Likewise. + * config/aarch64/driver-aarch64.cc (contains_core_p): Likewise. + * config/aarch64/t-aarch64: Likewise. + * config/aarch64/x-aarch64: Likewise. + * config/aarch64/x-darwin: Likewise. + * config/alpha/alpha-protos.h: Likewise. + * config/alpha/alpha.cc (alpha_scalar_mode_supported_p): Likewise. + * config/alpha/alpha.h (LONG_DOUBLE_TYPE_SIZE): Likewise. + (enum reg_class): Likewise. + * config/alpha/alpha.md: Likewise. + * config/alpha/driver-alpha.cc (AMASK_LOCKPFTCHOK): Likewise. + * config/alpha/x-alpha: Likewise. + * config/arc/arc-protos.h (arc_eh_uses): Likewise. + * config/arc/arc.cc (ARC_OPT): Likewise. + (arc_ccfsm_advance): Likewise. + (arc_arg_partial_bytes): Likewise. + (conditionalize_nonjump): Likewise. + * config/arc/arc.md: Likewise. + * config/arc/builtins.def: Likewise. + * config/arc/t-arc: Likewise. + * config/arm/arm-c.cc (arm_resolve_overloaded_builtin): Likewise. + (arm_pragma_target_parse): Likewise. + * config/arm/arm-protos.h (save_restore_target_globals): Likewise. + (arm_cpu_cpp_builtins): Likewise. + * config/arm/arm.cc (vfp3_const_double_index): Likewise. + (shift_op): Likewise. + (thumb2_final_prescan_insn): Likewise. + (arm_final_prescan_insn): Likewise. + (arm_asm_output_labelref): Likewise. + (arm_small_register_classes_for_mode_p): Likewise. + * config/arm/arm.h: Likewise. + * config/arm/arm.md: Likewise. + * config/arm/driver-arm.cc: Likewise. + * config/arm/symbian.h: Likewise. + * config/arm/t-arm: Likewise. + * config/arm/thumb1.md: Likewise. + * config/arm/x-arm: Likewise. + * config/avr/avr-c.cc (avr_register_target_pragmas): Likewise. + * config/avr/avr-fixed.md: Likewise. + * config/avr/avr-log.cc (avr_log_vadump): Likewise. + * config/avr/avr-mcus.def: Likewise. + * config/avr/avr-modes.def (FRACTIONAL_INT_MODE): Likewise. + * config/avr/avr-passes.def (INSERT_PASS_BEFORE): Likewise. + * config/avr/avr-protos.h (make_avr_pass_casesi): Likewise. + * config/avr/avr.cc (avr_option_override): Likewise. + (avr_build_builtin_va_list): Likewise. + (avr_mode_dependent_address_p): Likewise. + (avr_function_arg_advance): Likewise. + (avr_asm_output_aligned_decl_common): Likewise. + * config/avr/avr.h (RETURN_ADDR_RTX): Likewise. + (SUPPORTS_INIT_PRIORITY): Likewise. + * config/avr/avr.md: Likewise. + * config/avr/builtins.def: Likewise. + * config/avr/gen-avr-mmcu-specs.cc (IN_GEN_AVR_MMCU_TEXI): Likewise. + * config/avr/gen-avr-mmcu-texi.cc (IN_GEN_AVR_MMCU_TEXI): Likewise. + (main): Likewise. + * config/avr/t-avr: Likewise. + * config/bfin/bfin.cc (frame_related_constant_load): Likewise. + * config/bpf/bpf-protos.h (GCC_BPF_PROTOS_H): Likewise. + * config/bpf/bpf.h (enum reg_class): Likewise. + * config/bpf/t-bpf: Likewise. + * config/c6x/c6x-protos.h (GCC_C6X_PROTOS_H): Likewise. + * config/cr16/cr16-protos.h: Likewise. + * config/cris/cris.cc (cris_address_cost): Likewise. + (cris_side_effect_mode_ok): Likewise. + (cris_init_machine_status): Likewise. + (cris_emit_movem_store): Likewise. + * config/cris/cris.h (INDEX_REG_CLASS): Likewise. + (enum reg_class): Likewise. + (struct cum_args): Likewise. + * config/cris/cris.opt: Likewise. + * config/cris/sync.md: Likewise. + * config/csky/csky.cc (csky_expand_prologue): Likewise. + * config/darwin-c.cc: Likewise. + * config/darwin-f.cc: Likewise. + * config/darwin-sections.def (zobj_const_section): Likewise. + * config/darwin.cc (output_objc_section_asm_op): Likewise. + (fprintf): Likewise. + * config/darwin.h (GTY): Likewise. + * config/elfos.h: Likewise. + * config/epiphany/epiphany-sched.md: Likewise. + * config/epiphany/epiphany.cc (epiphany_function_value): Likewise. + * config/epiphany/epiphany.h (GTY): Likewise. + (NO_FUNCTION_CSE): Likewise. + * config/epiphany/mode-switch-use.cc: Likewise. + * config/epiphany/predicates.md: Likewise. + * config/epiphany/t-epiphany: Likewise. + * config/fr30/fr30-protos.h: Likewise. + * config/frv/frv-protos.h: Likewise. + * config/frv/frv.cc (TLS_BIAS): Likewise. + * config/frv/frv.h (ASM_OUTPUT_ALIGNED_LOCAL): Likewise. + * config/ft32/ft32-protos.h: Likewise. + * config/gcn/gcn-hsa.h (ASM_APP_OFF): Likewise. + * config/gcn/gcn.cc (gcn_init_libfuncs): Likewise. + * config/gcn/mkoffload.cc (copy_early_debug_info): Likewise. + * config/gcn/t-gcn-hsa: Likewise. + * config/gcn/t-omp-device: Likewise. + * config/h8300/h8300-protos.h (GCC_H8300_PROTOS_H): Likewise. + (same_cmp_following_p): Likewise. + * config/h8300/h8300.cc (F): Likewise. + * config/h8300/h8300.h (struct cum_arg): Likewise. + (BRANCH_COST): Likewise. + * config/i386/cygming.h (DEFAULT_PCC_STRUCT_RETURN): Likewise. + * config/i386/djgpp.h (TARGET_ASM_LTO_END): Likewise. + * config/i386/dragonfly.h (NO_PROFILE_COUNTERS): Likewise. + * config/i386/driver-i386.cc (detect_caches_intel): Likewise. + * config/i386/freebsd.h (NO_PROFILE_COUNTERS): Likewise. + * config/i386/i386-c.cc (ix86_target_macros): Likewise. + * config/i386/i386-expand.cc (get_mode_wider_vector): Likewise. + * config/i386/i386-options.cc (ix86_set_func_type): Likewise. + * config/i386/i386-protos.h (ix86_extract_perm_from_pool_constant): Likewise. + (ix86_register_pragmas): Likewise. + (ix86_d_has_stdcall_convention): Likewise. + (i386_pe_seh_init_sections): Likewise. + * config/i386/i386.cc (ix86_function_arg_regno_p): Likewise. + (ix86_function_value_regno_p): Likewise. + (ix86_compute_frame_layout): Likewise. + (legitimize_pe_coff_symbol): Likewise. + (output_pic_addr_const): Likewise. + * config/i386/i386.h (defined): Likewise. + (host_detect_local_cpu): Likewise. + (CONSTANT_ADDRESS_P): Likewise. + (DEFAULT_LARGE_SECTION_THRESHOLD): Likewise. + (struct machine_frame_state): Likewise. + * config/i386/i386.md: Likewise. + * config/i386/lynx.h (ASM_OUTPUT_ALIGN): Likewise. + * config/i386/mmx.md: Likewise. + * config/i386/sse.md: Likewise. + * config/i386/t-cygming: Likewise. + * config/i386/t-djgpp: Likewise. + * config/i386/t-gnu-property: Likewise. + * config/i386/t-i386: Likewise. + * config/i386/t-intelmic: Likewise. + * config/i386/t-omp-device: Likewise. + * config/i386/winnt-cxx.cc (i386_pe_type_dllimport_p): Likewise. + (i386_pe_adjust_class_at_definition): Likewise. + * config/i386/winnt.cc (gen_stdcall_or_fastcall_suffix): Likewise. + (i386_pe_mangle_decl_assembler_name): Likewise. + (i386_pe_encode_section_info): Likewise. + * config/i386/x-cygwin: Likewise. + * config/i386/x-darwin: Likewise. + * config/i386/x-i386: Likewise. + * config/i386/x-mingw32: Likewise. + * config/i386/x86-tune-sched-core.cc: Likewise. + * config/i386/x86-tune.def: Likewise. + * config/i386/xm-djgpp.h (STANDARD_STARTFILE_PREFIX_1): Likewise. + * config/ia64/freebsd.h: Likewise. + * config/ia64/hpux.h (REGISTER_TARGET_PRAGMAS): Likewise. + * config/ia64/ia64-protos.h (ia64_except_unwind_info): Likewise. + * config/ia64/ia64.cc (ia64_function_value_regno_p): Likewise. + (ia64_secondary_reload_class): Likewise. + (bundling): Likewise. + * config/ia64/ia64.h: Likewise. + * config/ia64/ia64.md: Likewise. + * config/ia64/predicates.md: Likewise. + * config/ia64/sysv4.h: Likewise. + * config/ia64/t-ia64: Likewise. + * config/iq2000/iq2000.h (FUNCTION_MODE): Likewise. + * config/iq2000/iq2000.md: Likewise. + * config/linux.h (TARGET_HAS_BIONIC): Likewise. + (if): Likewise. + * config/m32c/m32c.cc (m32c_function_needs_enter): Likewise. + * config/m32c/m32c.h (MAX_REGS_PER_ADDRESS): Likewise. + * config/m32c/t-m32c: Likewise. + * config/m32r/m32r-protos.h: Likewise. + * config/m32r/m32r.cc (m32r_print_operand): Likewise. + * config/m32r/m32r.h: Likewise. + * config/m32r/m32r.md: Likewise. + * config/m68k/m68k-isas.def: Likewise. + * config/m68k/m68k-microarchs.def: Likewise. + * config/m68k/m68k-protos.h (strict_low_part_peephole_ok): Likewise. + (m68k_epilogue_uses): Likewise. + * config/m68k/m68k.cc (m68k_call_tls_get_addr): Likewise. + (m68k_sched_adjust_cost): Likewise. + (m68k_sched_md_init): Likewise. + * config/m68k/m68k.h (__transfer_from_trampoline): Likewise. + (enum m68k_function_kind): Likewise. + * config/m68k/m68k.md: Likewise. + * config/m68k/m68kemb.h: Likewise. + * config/m68k/uclinux.h (ENDFILE_SPEC): Likewise. + * config/mcore/mcore-protos.h: Likewise. + * config/mcore/mcore.cc (mcore_expand_insv): Likewise. + (mcore_expand_prolog): Likewise. + * config/mcore/mcore.h (TARGET_MCORE): Likewise. + * config/mcore/mcore.md: Likewise. + * config/microblaze/microblaze-protos.h: Likewise. + * config/microblaze/microblaze.cc (microblaze_legitimate_pic_operand): Likewise. + (microblaze_function_prologue): Likewise. + (microblaze_function_epilogue): Likewise. + (microblaze_select_section): Likewise. + (microblaze_asm_output_mi_thunk): Likewise. + (microblaze_eh_return): Likewise. + * config/microblaze/microblaze.h: Likewise. + * config/microblaze/microblaze.md: Likewise. + * config/microblaze/t-microblaze: Likewise. + * config/mips/driver-native.cc: Likewise. + * config/mips/loongson2ef.md: Likewise. + * config/mips/mips-protos.h (mips_expand_vec_cmp_expr): Likewise. + * config/mips/mips.cc (mips_rtx_costs): Likewise. + (mips_output_filename): Likewise. + (mips_output_function_prologue): Likewise. + (mips_output_function_epilogue): Likewise. + (mips_output_mi_thunk): Likewise. + * config/mips/mips.h: Likewise. + * config/mips/mips.md: Likewise. + * config/mips/t-mips: Likewise. + * config/mips/x-native: Likewise. + * config/mmix/mmix-protos.h: Likewise. + * config/mmix/mmix.cc (mmix_option_override): Likewise. + (mmix_dbx_register_number): Likewise. + (mmix_expand_prologue): Likewise. + * config/mmix/mmix.h: Likewise. + * config/mmix/mmix.md: Likewise. + * config/mmix/predicates.md: Likewise. + * config/mn10300/mn10300.cc (mn10300_symbolic_operand): Likewise. + (mn10300_legitimate_pic_operand_p): Likewise. + * config/mn10300/mn10300.h (enum reg_class): Likewise. + (NO_FUNCTION_CSE): Likewise. + * config/moxie/moxie-protos.h: Likewise. + * config/moxie/uclinux.h (TARGET_LIBC_HAS_FUNCTION): Likewise. + * config/msp430/msp430-devices.cc (extract_devices_dir_from_exec_prefix): Likewise. + * config/msp430/msp430.cc (msp430_gimplify_va_arg_expr): Likewise. + (msp430_incoming_return_addr_rtx): Likewise. + * config/msp430/msp430.h (msp430_get_linker_devices_include_path): Likewise. + * config/msp430/t-msp430: Likewise. + * config/nds32/nds32-cost.cc (nds32_rtx_costs_speed_prefer): Likewise. + (nds32_rtx_costs_size_prefer): Likewise. + (nds32_init_rtx_costs): Likewise. + * config/nds32/nds32-doubleword.md: Likewise. + * config/nds32/nds32.cc (nds32_memory_move_cost): Likewise. + (nds32_builtin_decl): Likewise. + * config/nds32/nds32.h (enum nds32_16bit_address_type): Likewise. + (enum nds32_isr_nested_type): Likewise. + (enum reg_class): Likewise. + * config/nds32/predicates.md: Likewise. + * config/nds32/t-nds32: Likewise. + * config/nios2/nios2.cc (nios2_pragma_target_parse): Likewise. + * config/nvptx/nvptx-protos.h: Likewise. + * config/nvptx/nvptx.cc (nvptx_goacc_expand_var_decl): Likewise. + * config/nvptx/nvptx.h (TARGET_CPU_CPP_BUILTINS): Likewise. + * config/nvptx/t-nvptx: Likewise. + * config/nvptx/t-omp-device: Likewise. + * config/pa/elf.h: Likewise. + * config/pa/pa-linux.h (GLOBAL_ASM_OP): Likewise. + * config/pa/pa-netbsd.h (GLOBAL_ASM_OP): Likewise. + * config/pa/pa-openbsd.h (TARGET_ASM_GLOBALIZE_LABEL): Likewise. + * config/pa/pa-protos.h (pa_eh_return_handler_rtx): Likewise. + (pa_legitimize_reload_address): Likewise. + (pa_can_use_return_insn): Likewise. + * config/pa/pa.cc (mem_shadd_or_shadd_rtx_p): Likewise. + (som_output_text_section_asm_op): Likewise. + * config/pa/pa.h (PROFILE_BEFORE_PROLOGUE): Likewise. + * config/pa/pa.md: Likewise. + * config/pa/som.h: Likewise. + * config/pa/t-pa: Likewise. + * config/pdp11/pdp11.cc (decode_pdp11_d): Likewise. + * config/pdp11/pdp11.h: Likewise. + * config/pdp11/pdp11.md: Likewise. + * config/pdp11/t-pdp11: Likewise. + * config/pru/pru.md: Likewise. + * config/pru/t-pru: Likewise. + * config/riscv/riscv-protos.h (NUM_SYMBOL_TYPES): Likewise. + (riscv_gpr_save_operation_p): Likewise. + (riscv_d_register_target_info): Likewise. + (riscv_init_builtins): Likewise. + * config/riscv/riscv.cc (riscv_output_mi_thunk): Likewise. + * config/riscv/riscv.h (CSW_MAX_OFFSET): Likewise. + * config/riscv/t-riscv: Likewise. + * config/rl78/rl78.cc (rl78_asm_ctor_dtor): Likewise. + * config/rl78/t-rl78: Likewise. + * config/rs6000/aix.h: Likewise. + * config/rs6000/aix71.h (ASM_SPEC_COMMON): Likewise. + * config/rs6000/aix72.h (ASM_SPEC_COMMON): Likewise. + * config/rs6000/aix73.h (ASM_SPEC_COMMON): Likewise. + * config/rs6000/darwin.h (TARGET_ASM_GLOBALIZE_LABEL): Likewise. + * config/rs6000/driver-rs6000.cc: Likewise. + * config/rs6000/freebsd.h: Likewise. + * config/rs6000/freebsd64.h: Likewise. + * config/rs6000/lynx.h (ASM_OUTPUT_ALIGN): Likewise. + * config/rs6000/rbtree.cc: Likewise. + * config/rs6000/rbtree.h: Likewise. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Likewise. + * config/rs6000/rs6000-call.cc (rs6000_invalid_builtin): Likewise. + (rs6000_expand_builtin): Likewise. + (rs6000_init_builtins): Likewise. + * config/rs6000/rs6000-cpus.def: Likewise. + * config/rs6000/rs6000-gen-builtins.cc (write_init_ovld_table): Likewise. + * config/rs6000/rs6000-internal.h (ALTIVEC_REG_BIT): Likewise. + (quad_address_offset_p): Likewise. + * config/rs6000/rs6000-logue.cc (interesting_frame_related_regno): Likewise. + (rs6000_emit_epilogue): Likewise. + * config/rs6000/rs6000-overload.def: Likewise. + * config/rs6000/rs6000-p8swap.cc: Likewise. + * config/rs6000/rs6000-protos.h (GCC_RS6000_PROTOS_H): Likewise. + (rs6000_const_f32_to_i32): Likewise. + * config/rs6000/rs6000.cc (legitimate_lo_sum_address_p): Likewise. + (rs6000_debug_legitimize_address): Likewise. + (rs6000_mode_dependent_address): Likewise. + (rs6000_adjust_priority): Likewise. + (rs6000_c_mode_for_suffix): Likewise. + * config/rs6000/rs6000.h (defined): Likewise. + (LONG_DOUBLE_TYPE_SIZE): Likewise. + * config/rs6000/rs6000.md: Likewise. + * config/rs6000/sysv4.h: Likewise. + * config/rs6000/t-linux: Likewise. + * config/rs6000/t-linux64: Likewise. + * config/rs6000/t-rs6000: Likewise. + * config/rs6000/x-darwin: Likewise. + * config/rs6000/x-darwin64: Likewise. + * config/rs6000/x-rs6000: Likewise. + * config/rs6000/xcoff.h (ASM_OUTPUT_LABELREF): Likewise. + * config/rx/rx.cc (rx_expand_builtin): Likewise. + * config/s390/constraints.md: Likewise. + * config/s390/driver-native.cc: Likewise. + * config/s390/htmxlintrin.h: Likewise. + * config/s390/s390-builtins.def (B_DEF): Likewise. + (OB_DEF_VAR): Likewise. + * config/s390/s390-builtins.h: Likewise. + * config/s390/s390-c.cc: Likewise. + * config/s390/s390-opts.h: Likewise. + * config/s390/s390-protos.h (s390_check_symref_alignment): Likewise. + (s390_register_target_pragmas): Likewise. + * config/s390/s390.cc (s390_init_builtins): Likewise. + (s390_expand_plus_operand): Likewise. + (s390_expand_atomic): Likewise. + (s390_valid_target_attribute_inner_p): Likewise. + * config/s390/s390.h (LONG_DOUBLE_TYPE_SIZE): Likewise. + * config/s390/s390.md: Likewise. + * config/s390/t-s390: Likewise. + * config/s390/vx-builtins.md: Likewise. + * config/s390/x-native: Likewise. + * config/sh/divtab-sh4-300.cc (main): Likewise. + * config/sh/divtab-sh4.cc (main): Likewise. + * config/sh/divtab.cc (main): Likewise. + * config/sh/elf.h: Likewise. + * config/sh/sh-protos.h (sh_fsca_int2sf): Likewise. + * config/sh/sh.cc (SYMBOL_FLAG_FUNCVEC_FUNCTION): Likewise. + (sh_struct_value_rtx): Likewise. + (sh_remove_reg_dead_or_unused_notes): Likewise. + * config/sh/sh.h (MIN_UNITS_PER_WORD): Likewise. + * config/sh/t-sh: Likewise. + * config/sol2-protos.h (solaris_override_options): Likewise. + * config/sol2.h: Likewise. + * config/sparc/driver-sparc.cc: Likewise. + * config/sparc/freebsd.h: Likewise. + * config/sparc/sparc-protos.h (make_pass_work_around_errata): Likewise. + * config/sparc/sparc.cc (sparc_output_mi_thunk): Likewise. + (sparc_asan_shadow_offset): Likewise. + * config/sparc/sparc.h: Likewise. + * config/sparc/sparc.md: Likewise. + * config/sparc/t-sparc: Likewise. + * config/sparc/x-sparc: Likewise. + * config/stormy16/stormy16.cc (xstormy16_mode_dependent_address_p): Likewise. + * config/t-darwin: Likewise. + * config/t-dragonfly: Likewise. + * config/t-freebsd: Likewise. + * config/t-glibc: Likewise. + * config/t-linux: Likewise. + * config/t-netbsd: Likewise. + * config/t-openbsd: Likewise. + * config/t-pnt16-warn: Likewise. + * config/t-sol2: Likewise. + * config/t-vxworks: Likewise. + * config/t-winnt: Likewise. + * config/tilegx/t-tilegx: Likewise. + * config/tilegx/tilegx-c.cc: Likewise. + * config/tilegx/tilegx-protos.h (tilegx_function_profiler): Likewise. + * config/tilegx/tilegx.md: Likewise. + * config/tilepro/t-tilepro: Likewise. + * config/tilepro/tilepro-c.cc: Likewise. + * config/v850/t-v850: Likewise. + * config/v850/v850-protos.h: Likewise. + * config/v850/v850.cc (F): Likewise. + * config/v850/v850.h (enum reg_class): Likewise. + (SLOW_BYTE_ACCESS): Likewise. + * config/vax/vax.cc (vax_mode_dependent_address_p): Likewise. + * config/vax/vax.h (enum reg_class): Likewise. + * config/vax/vax.md: Likewise. + * config/visium/visium.cc (visium_legitimate_address_p): Likewise. + * config/visium/visium.h: Likewise. + * config/vms/t-vms: Likewise. + * config/vms/vms-crtlmap.map: Likewise. + * config/vms/vms-protos.h (vms_c_get_vms_ver): Likewise. + * config/vx-common.h: Likewise. + * config/x-darwin: Likewise. + * config/x-hpux: Likewise. + * config/x-linux: Likewise. + * config/x-netbsd: Likewise. + * config/x-openbsd: Likewise. + * config/x-solaris: Likewise. + * config/xtensa/xtensa-protos.h (xtensa_mem_offset): Likewise. + * config/xtensa/xtensa.cc (xtensa_option_override): Likewise. + * config/xtensa/xtensa.h: Likewise. + * configure.ac: Likewise. + * context.cc: Likewise. + * convert.h: Likewise. + * coretypes.h: Likewise. + * coverage.cc: Likewise. + * coverage.h: Likewise. + * cppdefault.h (struct default_include): Likewise. + * cprop.cc (local_cprop_pass): Likewise. + (one_cprop_pass): Likewise. + * cse.cc (hash_rtx_cb): Likewise. + (fold_rtx): Likewise. + * ctfc.h (ctfc_get_num_vlen_bytes): Likewise. + * data-streamer.h (bp_unpack_var_len_int): Likewise. + (streamer_write_widest_int): Likewise. + * dbgcnt.def: Likewise. + * dbxout.cc (dbxout_early_global_decl): Likewise. + (dbxout_common_check): Likewise. + * dbxout.h: Likewise. + * debug.h (struct gcc_debug_hooks): Likewise. + (dump_go_spec_init): Likewise. + * df-core.cc: Likewise. + * df-scan.cc (df_insn_info_delete): Likewise. + (df_insn_delete): Likewise. + * df.h (debug_df_chain): Likewise. + (can_move_insns_across): Likewise. + * dfp.cc (decimal_from_binary): Likewise. + * diagnostic-color.cc: Likewise. + * diagnostic-event-id.h: Likewise. + * diagnostic-show-locus.cc (test_one_liner_labels): Likewise. + * diagnostic.cc (bt_callback): Likewise. + (num_digits): Likewise. + * doc/avr-mmcu.texi: Likewise. + * doc/cfg.texi: Likewise. + * doc/contrib.texi: Likewise. + * doc/cppinternals.texi: Likewise. + * doc/extend.texi: Likewise. + * doc/generic.texi: Likewise. + * doc/gimple.texi: Likewise. + * doc/gty.texi: Likewise. + * doc/invoke.texi: Likewise. + * doc/loop.texi: Likewise. + * doc/lto.texi: Likewise. + * doc/match-and-simplify.texi: Likewise. + * doc/md.texi: Likewise. + * doc/optinfo.texi: Likewise. + * doc/options.texi: Likewise. + * doc/passes.texi: Likewise. + * doc/plugins.texi: Likewise. + * doc/rtl.texi: Likewise. + * doc/sourcebuild.texi: Likewise. + * doc/tm.texi: Likewise. + * doc/tm.texi.in: Likewise. + * doc/tree-ssa.texi: Likewise. + * dojump.cc (do_jump): Likewise. + * dojump.h: Likewise. + * dumpfile.cc (test_impl_location): Likewise. + (test_capture_of_dump_calls): Likewise. + * dumpfile.h (enum dump_kind): Likewise. + (class dump_location_t): Likewise. + (dump_enabled_p): Likewise. + (enable_rtl_dump_file): Likewise. + (dump_combine_total_stats): Likewise. + * dwarf2asm.cc (dw2_asm_output_delta_uleb128): Likewise. + * dwarf2ctf.h (ctf_debug_finish): Likewise. + * dwarf2out.cc (dwarf2out_begin_prologue): Likewise. + (struct loc_descr_context): Likewise. + (rtl_for_decl_location): Likewise. + (gen_subprogram_die): Likewise. + (gen_label_die): Likewise. + (is_trivial_indirect_ref): Likewise. + (dwarf2out_late_global_decl): Likewise. + (dwarf_file_hasher::hash): Likewise. + (dwarf2out_end_source_file): Likewise. + (dwarf2out_define): Likewise. + (dwarf2out_early_finish): Likewise. + * dwarf2out.h (struct dw_fde_node): Likewise. + (struct dw_discr_list_node): Likewise. + (output_loc_sequence_raw): Likewise. + * emit-rtl.cc (gen_raw_REG): Likewise. + (maybe_set_max_label_num): Likewise. + * emit-rtl.h (struct rtl_data): Likewise. + * errors.cc (internal_error): Likewise. + (trim_filename): Likewise. + * et-forest.cc: Likewise. + * except.cc (init_eh_for_function): Likewise. + * explow.cc (promote_ssa_mode): Likewise. + (get_dynamic_stack_size): Likewise. + * explow.h: Likewise. + * expmed.h: Likewise. + * expr.cc (safe_from_p): Likewise. + (expand_expr_real_2): Likewise. + (expand_expr_real_1): Likewise. + * file-prefix-map.cc (remap_filename): Likewise. + * final.cc (app_enable): Likewise. + (make_pass_compute_alignments): Likewise. + (final_scan_insn_1): Likewise. + (final_scan_insn): Likewise. + * fixed-value.h (fixed_from_string): Likewise. + * flag-types.h (NO_DEBUG): Likewise. + (DWARF2_DEBUG): Likewise. + (VMS_DEBUG): Likewise. + (BTF_DEBUG): Likewise. + (enum ctf_debug_info_levels): Likewise. + * fold-const.cc (const_binop): Likewise. + (fold_binary_loc): Likewise. + (fold_checksum_tree): Likewise. + * fp-test.cc: Likewise. + * function.cc (expand_function_end): Likewise. + * function.h (struct function): Likewise. + * fwprop.cc (should_replace_address): Likewise. + * gcc-main.cc: Likewise. + * gcc-rich-location.h (class gcc_rich_location): Likewise. + * gcc-symtab.h: Likewise. + * gcc.cc (MIN_FATAL_STATUS): Likewise. + (driver_handle_option): Likewise. + (quote_spec_arg): Likewise. + (driver::finalize): Likewise. + * gcc.h (set_input): Likewise. + * gcov-dump.cc: Likewise. + * gcov.cc (solve_flow_graph): Likewise. + * gcse-common.cc: Likewise. + * gcse.cc (make_pass_rtl_hoist): Likewise. + * genattr-common.cc: Likewise. + * genattrtab.cc (min_fn): Likewise. + (write_const_num_delay_slots): Likewise. + * genautomata.cc: Likewise. + * genconditions.cc (write_one_condition): Likewise. + * genconstants.cc: Likewise. + * genemit.cc (gen_exp): Likewise. + * generic-match-head.cc: Likewise. + * genextract.cc: Likewise. + * gengenrtl.cc (always_void_p): Likewise. + * gengtype-parse.cc (gtymarker_opt): Likewise. + * gengtype-state.cc (state_writer::state_writer): Likewise. + (write_state_trailer): Likewise. + (equals_type_number): Likewise. + (read_state): Likewise. + * gengtype.cc (open_base_files): Likewise. + (struct file_rule_st): Likewise. + (header_dot_h_frul): Likewise. + * gengtype.h: Likewise. + * genmatch.cc (main): Likewise. + * genmddeps.cc: Likewise. + * genmodes.cc (emit_mode_inner): Likewise. + (emit_mode_unit_size): Likewise. + * genpeep.cc (gen_peephole): Likewise. + * genpreds.cc (write_tm_preds_h): Likewise. + * genrecog.cc (validate_pattern): Likewise. + (write_header): Likewise. + (main): Likewise. + * gensupport.cc (change_subst_attribute): Likewise. + (traverse_c_tests): Likewise. + (add_predicate): Likewise. + (init_predicate_table): Likewise. + * gensupport.h (struct optab_pattern): Likewise. + (get_num_insn_codes): Likewise. + (maybe_eval_c_test): Likewise. + (struct pred_data): Likewise. + * ggc-internal.h: Likewise. + * gimple-fold.cc (maybe_fold_reference): Likewise. + (get_range_strlen_tree): Likewise. + * gimple-fold.h (gimple_stmt_integer_valued_real_p): Likewise. + * gimple-low.cc: Likewise. + * gimple-match-head.cc (directly_supported_p): Likewise. + * gimple-pretty-print.h: Likewise. + * gimple-ssa-sprintf.cc (format_percent): Likewise. + (adjust_range_for_overflow): Likewise. + * gimple-streamer.h: Likewise. + * gimple.h (struct GTY): Likewise. + (is_gimple_resx): Likewise. + * gimplify.cc (gimplify_expr): Likewise. + (gimplify_init_constructor): Likewise. + (omp_construct_selector_matches): Likewise. + (gimplify_omp_target_update): Likewise. + (gimplify_omp_ordered): Likewise. + (gimplify_va_arg_expr): Likewise. + * graphite-isl-ast-to-gimple.cc (should_copy_to_new_region): Likewise. + * haifa-sched.cc (increase_insn_priority): Likewise. + (try_ready): Likewise. + (sched_create_recovery_edges): Likewise. + * ifcvt.cc (find_if_case_1): Likewise. + (find_if_case_2): Likewise. + * inchash.h: Likewise. + * incpath.cc (add_env_var_paths): Likewise. + * input.cc (dump_location_info): Likewise. + (assert_loceq): Likewise. + (test_lexer_string_locations_concatenation_1): Likewise. + (test_lexer_string_locations_concatenation_2): Likewise. + (test_lexer_string_locations_concatenation_3): Likewise. + * input.h (BUILTINS_LOCATION): Likewise. + (class string_concat_db): Likewise. + * internal-fn.cc (expand_MUL_OVERFLOW): Likewise. + (expand_LOOP_VECTORIZED): Likewise. + * ipa-cp.cc (make_pass_ipa_cp): Likewise. + * ipa-fnsummary.cc (remap_freqcounting_preds_after_dup): Likewise. + (ipa_fn_summary_t::duplicate): Likewise. + (make_pass_ipa_fn_summary): Likewise. + * ipa-fnsummary.h (enum ipa_hints_vals): Likewise. + * ipa-free-lang-data.cc (fld_simplified_type): Likewise. + (free_lang_data_in_decl): Likewise. + * ipa-inline.cc (compute_inlined_call_time): Likewise. + (inline_always_inline_functions): Likewise. + * ipa-inline.h (free_growth_caches): Likewise. + (inline_account_function_p): Likewise. + * ipa-modref.cc (modref_access_analysis::analyze_stmt): Likewise. + (modref_eaf_analysis::analyze_ssa_name): Likewise. + * ipa-param-manipulation.cc (ipa_param_body_adjustments::mark_dead_statements): Likewise. + (ipa_param_body_adjustments::remap_with_debug_expressions): Likewise. + * ipa-prop.cc (ipa_set_node_agg_value_chain): Likewise. + * ipa-prop.h (IPA_UNDESCRIBED_USE): Likewise. + (unadjusted_ptr_and_unit_offset): Likewise. + * ipa-reference.cc (make_pass_ipa_reference): Likewise. + * ipa-reference.h (GCC_IPA_REFERENCE_H): Likewise. + * ipa-split.cc (consider_split): Likewise. + * ipa-sra.cc (isra_read_node_info): Likewise. + * ipa-utils.h (struct ipa_dfs_info): Likewise. + (recursive_call_p): Likewise. + (ipa_make_function_pure): Likewise. + * ira-build.cc (ira_create_allocno): Likewise. + (ira_flattening): Likewise. + * ira-color.cc (do_coloring): Likewise. + (update_curr_costs): Likewise. + * ira-conflicts.cc (process_regs_for_copy): Likewise. + * ira-int.h (struct ira_emit_data): Likewise. + (ira_prohibited_mode_move_regs): Likewise. + (ira_get_dup_out_num): Likewise. + (ira_destroy): Likewise. + (ira_tune_allocno_costs): Likewise. + (ira_implicitly_set_insn_hard_regs): Likewise. + (ira_build_conflicts): Likewise. + (ira_color): Likewise. + * ira-lives.cc (process_bb_node_lives): Likewise. + * ira.cc (class ira_spilled_reg_stack_slot): Likewise. + (setup_uniform_class_p): Likewise. + (def_dominates_uses): Likewise. + * ira.h (ira_nullify_asm_goto): Likewise. + * langhooks.cc (lhd_post_options): Likewise. + * langhooks.h (class substring_loc): Likewise. + (struct lang_hooks_for_tree_inlining): Likewise. + (struct lang_hooks_for_types): Likewise. + (struct lang_hooks): Likewise. + * libfuncs.h (synchronize_libfunc): Likewise. + * loop-doloop.cc (doloop_condition_get): Likewise. + * loop-init.cc (fix_loop_structure): Likewise. + * loop-invariant.cc: Likewise. + * lower-subreg.h: Likewise. + * lra-constraints.cc (curr_insn_transform): Likewise. + * lra-int.h (struct lra_insn_reg): Likewise. + (lra_undo_inheritance): Likewise. + (lra_setup_reload_pseudo_preferenced_hard_reg): Likewise. + (lra_split_hard_reg_for): Likewise. + (lra_coalesce): Likewise. + (lra_final_code_change): Likewise. + * lra-spills.cc (lra_final_code_change): Likewise. + * lra.cc (lra_process_new_insns): Likewise. + * lto-compress.h (struct lto_compression_stream): Likewise. + * lto-streamer-out.cc (DFS::DFS_write_tree_body): Likewise. + (write_symbol): Likewise. + * lto-streamer.h (enum LTO_tags): Likewise. + (lto_value_range_error): Likewise. + (lto_append_block): Likewise. + (lto_streamer_hooks_init): Likewise. + (stream_read_tree_ref): Likewise. + (lto_prepare_function_for_streaming): Likewise. + (select_what_to_stream): Likewise. + (omp_lto_input_declare_variant_alt): Likewise. + (cl_optimization_stream_in): Likewise. + * lto-wrapper.cc (append_compiler_options): Likewise. + * machmode.def: Likewise. + * machmode.h (struct int_n_data_t): Likewise. + * main.cc (main): Likewise. + * match.pd: Likewise. + * omp-builtins.def (BUILT_IN_GOMP_CRITICAL_NAME_END): Likewise. + (BUILT_IN_GOMP_LOOP_ULL_ORDERED_RUNTIME_NEXT): Likewise. + * omp-expand.cc (expand_omp_atomic_fetch_op): Likewise. + (make_pass_expand_omp_ssa): Likewise. + * omp-low.cc (struct omp_context): Likewise. + (struct omp_taskcopy_context): Likewise. + (lower_omp): Likewise. + * omp-oacc-neuter-broadcast.cc (omp_sese_active_worker_call): Likewise. + (mask_name): Likewise. + (omp_sese_dump_pars): Likewise. + (worker_single_simple): Likewise. + * omp-offload.cc (omp_finish_file): Likewise. + (execute_oacc_loop_designation): Likewise. + * optabs-query.cc (lshift_cheap_p): Likewise. + * optc-gen.awk: Likewise. + * optc-save-gen.awk: Likewise. + * optinfo-emit-json.cc (optrecord_json_writer::optrecord_json_writer): Likewise. + * opts-common.cc: Likewise. + * output.h (app_enable): Likewise. + (output_operand_lossage): Likewise. + (insn_current_reference_address): Likewise. + (get_insn_template): Likewise. + (output_quoted_string): Likewise. + * pass_manager.h (struct register_pass_info): Likewise. + * plugin.cc: Likewise. + * plugin.def (PLUGIN_ANALYZER_INIT): Likewise. + * plugin.h (invoke_plugin_callbacks): Likewise. + * pointer-query.cc (handle_mem_ref): Likewise. + * postreload-gcse.cc (alloc_mem): Likewise. + * predict.h (enum prediction): Likewise. + (add_reg_br_prob_note): Likewise. + * prefix.h: Likewise. + * profile.h (get_working_sets): Likewise. + * read-md.cc: Likewise. + * read-md.h (struct mapping): Likewise. + (class md_reader): Likewise. + (class noop_reader): Likewise. + * read-rtl-function.cc (function_reader::create_function): Likewise. + (function_reader::extra_parsing_for_operand_code_0): Likewise. + * read-rtl.cc (initialize_iterators): Likewise. + * real.cc: Likewise. + * real.h (struct real_value): Likewise. + (format_helper::format_helper): Likewise. + (real_hash): Likewise. + (real_can_shorten_arithmetic): Likewise. + * recog.cc (struct target_recog): Likewise. + (offsettable_nonstrict_memref_p): Likewise. + (constrain_operands): Likewise. + * recog.h (MAX_RECOG_ALTERNATIVES): Likewise. + (which_op_alt): Likewise. + (struct insn_gen_fn): Likewise. + * reg-notes.def (REG_NOTE): Likewise. + * reg-stack.cc: Likewise. + * regs.h (reg_is_parm_p): Likewise. + * regset.h: Likewise. + * reload.cc (push_reload): Likewise. + (find_reloads): Likewise. + (find_reloads_address_1): Likewise. + (find_replacement): Likewise. + (refers_to_regno_for_reload_p): Likewise. + (refers_to_mem_for_reload_p): Likewise. + * reload.h (push_reload): Likewise. + (deallocate_reload_reg): Likewise. + * reload1.cc (emit_input_reload_insns): Likewise. + * reorg.cc (relax_delay_slots): Likewise. + * rtl.def (UNKNOWN): Likewise. + (SEQUENCE): Likewise. + (BARRIER): Likewise. + (ASM_OPERANDS): Likewise. + (EQ_ATTR_ALT): Likewise. + * rtl.h (struct GTY): Likewise. + (LABEL_NAME): Likewise. + (LABEL_ALT_ENTRY_P): Likewise. + (SUBREG_BYTE): Likewise. + (get_stack_check_protect): Likewise. + (dump_rtx_statistics): Likewise. + (unwrap_const_vec_duplicate): Likewise. + (subreg_promoted_mode): Likewise. + (gen_lowpart_common): Likewise. + (operand_subword): Likewise. + (immed_wide_int_const): Likewise. + (decide_function_section): Likewise. + (active_insn_p): Likewise. + (delete_related_insns): Likewise. + (try_split): Likewise. + (val_signbit_known_clear_p): Likewise. + (simplifiable_subregs): Likewise. + (set_insn_deleted): Likewise. + (subreg_get_info): Likewise. + (remove_free_EXPR_LIST_node): Likewise. + (finish_subregs_of_mode): Likewise. + (get_mem_attrs): Likewise. + (lookup_constant_def): Likewise. + (rtx_to_tree_code): Likewise. + (hash_rtx): Likewise. + (condjump_in_parallel_p): Likewise. + (validate_subreg): Likewise. + (make_compound_operation): Likewise. + (schedule_ebbs): Likewise. + (print_inline_rtx): Likewise. + (fixup_args_size_notes): Likewise. + (expand_dec): Likewise. + (prepare_copy_insn): Likewise. + (mark_elimination): Likewise. + (valid_mode_changes_for_regno): Likewise. + (make_debug_expr_from_rtl): Likewise. + (delete_vta_debug_insns): Likewise. + (simplify_using_condition): Likewise. + (set_insn_locations): Likewise. + (fatal_insn_not_found): Likewise. + (word_register_operation_p): Likewise. + * rtlanal.cc (get_call_fndecl): Likewise. + (side_effects_p): Likewise. + (subreg_nregs): Likewise. + (rtx_cost): Likewise. + (canonicalize_condition): Likewise. + * rtlanal.h (rtx_properties::try_to_add_note): Likewise. + * run-rtl-passes.cc (run_rtl_passes): Likewise. + * sanitizer.def (BUILT_IN_ASAN_VERSION_MISMATCH_CHECK): Likewise. + * sched-deps.cc (add_dependence_1): Likewise. + * sched-ebb.cc (begin_move_insn): Likewise. + (add_deps_for_risky_insns): Likewise. + (advance_target_bb): Likewise. + * sched-int.h (reemit_notes): Likewise. + (struct _haifa_insn_data): Likewise. + (HID): Likewise. + (DEP_CANCELLED): Likewise. + (debug_ds): Likewise. + (number_in_ready): Likewise. + (schedule_ebbs_finish): Likewise. + (find_modifiable_mems): Likewise. + * sched-rgn.cc (debug_rgn_dependencies): Likewise. + * sel-sched-dump.cc (dump_lv_set): Likewise. + * sel-sched-dump.h: Likewise. + * sel-sched-ir.cc (sel_insn_rtx_cost): Likewise. + (setup_id_reg_sets): Likewise. + (has_dependence_p): Likewise. + (sel_num_cfg_preds_gt_1): Likewise. + (bb_ends_ebb_p): Likewise. + * sel-sched-ir.h (struct _list_node): Likewise. + (struct idata_def): Likewise. + (bb_next_bb): Likewise. + * sel-sched.cc (vinsn_writes_one_of_regs_p): Likewise. + (choose_best_pseudo_reg): Likewise. + (verify_target_availability): Likewise. + (can_speculate_dep_p): Likewise. + (sel_rank_for_schedule): Likewise. + * selftest-run-tests.cc (selftest::run_tests): Likewise. + * selftest.h (class auto_fix_quotes): Likewise. + * shrink-wrap.cc (handle_simple_exit): Likewise. + * shrink-wrap.h: Likewise. + * simplify-rtx.cc (simplify_context::simplify_associative_operation): Likewise. + (simplify_context::simplify_gen_vec_select): Likewise. + * spellcheck-tree.h: Likewise. + * spellcheck.h: Likewise. + * statistics.h (struct function): Likewise. + * stmt.cc (conditional_probability): Likewise. + * stmt.h: Likewise. + * stor-layout.h: Likewise. + * streamer-hooks.h: Likewise. + * stringpool.h: Likewise. + * symtab.cc (symbol_table::change_decl_assembler_name): Likewise. + * target.def (HOOK_VECTOR_END): Likewise. + (type.): Likewise. + * target.h (union cumulative_args_t): Likewise. + (by_pieces_ninsns): Likewise. + (class predefined_function_abi): Likewise. + * targhooks.cc (default_translate_mode_attribute): Likewise. + * timevar.def: Likewise. + * timevar.h (class timer): Likewise. + * toplev.h (enable_rtl_dump_file): Likewise. + * trans-mem.cc (collect_bb2reg): Likewise. + * tree-call-cdce.cc (gen_conditions_for_pow): Likewise. + * tree-cfg.cc (remove_bb): Likewise. + (verify_gimple_debug): Likewise. + (remove_edge_and_dominated_blocks): Likewise. + (push_fndecl): Likewise. + * tree-cfgcleanup.h (GCC_TREE_CFGCLEANUP_H): Likewise. + * tree-complex.cc (expand_complex_multiplication): Likewise. + (expand_complex_div_straight): Likewise. + * tree-core.h (enum tree_index): Likewise. + (enum operand_equal_flag): Likewise. + * tree-eh.cc (honor_protect_cleanup_actions): Likewise. + * tree-if-conv.cc (if_convertible_gimple_assign_stmt_p): Likewise. + * tree-inline.cc (initialize_inlined_parameters): Likewise. + * tree-inline.h (force_value_to_type): Likewise. + * tree-nested.cc (get_chain_decl): Likewise. + (walk_all_functions): Likewise. + * tree-object-size.h: Likewise. + * tree-outof-ssa.cc: Likewise. + * tree-parloops.cc (create_parallel_loop): Likewise. + * tree-pretty-print.cc (print_generic_expr_to_str): Likewise. + (dump_generic_node): Likewise. + * tree-profile.cc (tree_profiling): Likewise. + * tree-sra.cc (maybe_add_sra_candidate): Likewise. + * tree-ssa-address.cc: Likewise. + * tree-ssa-alias.cc: Likewise. + * tree-ssa-alias.h (ao_ref::max_size_known_p): Likewise. + (dump_alias_stats): Likewise. + * tree-ssa-ccp.cc: Likewise. + * tree-ssa-coalesce.h: Likewise. + * tree-ssa-live.cc (remove_unused_scope_block_p): Likewise. + * tree-ssa-loop-manip.cc (copy_phi_node_args): Likewise. + * tree-ssa-loop-unswitch.cc: Likewise. + * tree-ssa-math-opts.cc: Likewise. + * tree-ssa-operands.cc (class operands_scanner): Likewise. + * tree-ssa-pre.cc: Likewise. + * tree-ssa-reassoc.cc (optimize_ops_list): Likewise. + (debug_range_entry): Likewise. + * tree-ssa-sccvn.cc (eliminate_dom_walker::eliminate_stmt): Likewise. + * tree-ssa-sccvn.h (TREE_SSA_SCCVN_H): Likewise. + * tree-ssa-scopedtables.cc (add_expr_commutative): Likewise. + (equal_mem_array_ref_p): Likewise. + * tree-ssa-strlen.cc (is_strlen_related_p): Likewise. + * tree-ssa-strlen.h (get_range_strlen_dynamic): Likewise. + * tree-ssa-tail-merge.cc (stmt_local_def): Likewise. + * tree-ssa-ter.h: Likewise. + * tree-ssa-threadupdate.h (enum bb_dom_status): Likewise. + * tree-streamer-in.cc (lto_input_ts_block_tree_pointers): Likewise. + * tree-streamer-out.cc (pack_ts_block_value_fields): Likewise. + (write_ts_block_tree_pointers): Likewise. + * tree-streamer.h (struct streamer_tree_cache_d): Likewise. + (streamer_read_tree_bitfields): Likewise. + (streamer_write_integer_cst): Likewise. + * tree-vect-patterns.cc (apply_binop_and_append_stmt): Likewise. + (vect_synth_mult_by_constant): Likewise. + * tree-vect-stmts.cc (vectorizable_operation): Likewise. + * tree-vectorizer.cc: Likewise. + * tree-vectorizer.h (class auto_purge_vect_location): Likewise. + (vect_update_inits_of_drs): Likewise. + (vect_get_mask_type_for_stmt): Likewise. + (vect_rgroup_iv_might_wrap_p): Likewise. + (cse_and_gimplify_to_preheader): Likewise. + (vect_free_slp_tree): Likewise. + (vect_pattern_recog): Likewise. + (vect_stmt_dominates_stmt_p): Likewise. + * tree.cc (initialize_tree_contains_struct): Likewise. + (need_assembler_name_p): Likewise. + (type_with_interoperable_signedness): Likewise. + * tree.def (SWITCH_EXPR): Likewise. + * tree.h (TYPE_SYMTAB_ADDRESS): Likewise. + (poly_int_tree_p): Likewise. + (inlined_function_outer_scope_p): Likewise. + (tree_code_for_canonical_type_merging): Likewise. + * value-prof.cc: Likewise. + * value-prof.h (get_nth_most_common_value): Likewise. + (find_func_by_profile_id): Likewise. + * value-range.cc (vrp_operand_equal_p): Likewise. + * value-range.h: Likewise. + * var-tracking.cc: Likewise. + * varasm.cc (default_function_section): Likewise. + (function_section_1): Likewise. + (assemble_variable): Likewise. + (handle_vtv_comdat_section): Likewise. + * vec.h (struct vec_prefix): Likewise. + * vmsdbgout.cc (full_name): Likewise. + * vtable-verify.cc: Likewise. + * vtable-verify.h (struct vtv_graph_node): Likewise. + * xcoffout.cc: Likewise. + * xcoffout.h (DEBUG_SYMS_TEXT): Likewise. + +2022-01-17 Martin Liska <mliska@suse.cz> + + * adjust-alignment.c: Moved to... + * adjust-alignment.cc: ...here. + * alias.c: Moved to... + * alias.cc: ...here. + * alloc-pool.c: Moved to... + * alloc-pool.cc: ...here. + * asan.c: Moved to... + * asan.cc: ...here. + * attribs.c: Moved to... + * attribs.cc: ...here. + * auto-inc-dec.c: Moved to... + * auto-inc-dec.cc: ...here. + * auto-profile.c: Moved to... + * auto-profile.cc: ...here. + * bb-reorder.c: Moved to... + * bb-reorder.cc: ...here. + * bitmap.c: Moved to... + * bitmap.cc: ...here. + * btfout.c: Moved to... + * btfout.cc: ...here. + * builtins.c: Moved to... + * builtins.cc: ...here. + * caller-save.c: Moved to... + * caller-save.cc: ...here. + * calls.c: Moved to... + * calls.cc: ...here. + * ccmp.c: Moved to... + * ccmp.cc: ...here. + * cfg.c: Moved to... + * cfg.cc: ...here. + * cfganal.c: Moved to... + * cfganal.cc: ...here. + * cfgbuild.c: Moved to... + * cfgbuild.cc: ...here. + * cfgcleanup.c: Moved to... + * cfgcleanup.cc: ...here. + * cfgexpand.c: Moved to... + * cfgexpand.cc: ...here. + * cfghooks.c: Moved to... + * cfghooks.cc: ...here. + * cfgloop.c: Moved to... + * cfgloop.cc: ...here. + * cfgloopanal.c: Moved to... + * cfgloopanal.cc: ...here. + * cfgloopmanip.c: Moved to... + * cfgloopmanip.cc: ...here. + * cfgrtl.c: Moved to... + * cfgrtl.cc: ...here. + * cgraph.c: Moved to... + * cgraph.cc: ...here. + * cgraphbuild.c: Moved to... + * cgraphbuild.cc: ...here. + * cgraphclones.c: Moved to... + * cgraphclones.cc: ...here. + * cgraphunit.c: Moved to... + * cgraphunit.cc: ...here. + * collect-utils.c: Moved to... + * collect-utils.cc: ...here. + * collect2-aix.c: Moved to... + * collect2-aix.cc: ...here. + * collect2.c: Moved to... + * collect2.cc: ...here. + * combine-stack-adj.c: Moved to... + * combine-stack-adj.cc: ...here. + * combine.c: Moved to... + * combine.cc: ...here. + * common/common-targhooks.c: Moved to... + * common/common-targhooks.cc: ...here. + * common/config/aarch64/aarch64-common.c: Moved to... + * common/config/aarch64/aarch64-common.cc: ...here. + * common/config/alpha/alpha-common.c: Moved to... + * common/config/alpha/alpha-common.cc: ...here. + * common/config/arc/arc-common.c: Moved to... + * common/config/arc/arc-common.cc: ...here. + * common/config/arm/arm-common.c: Moved to... + * common/config/arm/arm-common.cc: ...here. + * common/config/avr/avr-common.c: Moved to... + * common/config/avr/avr-common.cc: ...here. + * common/config/bfin/bfin-common.c: Moved to... + * common/config/bfin/bfin-common.cc: ...here. + * common/config/bpf/bpf-common.c: Moved to... + * common/config/bpf/bpf-common.cc: ...here. + * common/config/c6x/c6x-common.c: Moved to... + * common/config/c6x/c6x-common.cc: ...here. + * common/config/cr16/cr16-common.c: Moved to... + * common/config/cr16/cr16-common.cc: ...here. + * common/config/cris/cris-common.c: Moved to... + * common/config/cris/cris-common.cc: ...here. + * common/config/csky/csky-common.c: Moved to... + * common/config/csky/csky-common.cc: ...here. + * common/config/default-common.c: Moved to... + * common/config/default-common.cc: ...here. + * common/config/epiphany/epiphany-common.c: Moved to... + * common/config/epiphany/epiphany-common.cc: ...here. + * common/config/fr30/fr30-common.c: Moved to... + * common/config/fr30/fr30-common.cc: ...here. + * common/config/frv/frv-common.c: Moved to... + * common/config/frv/frv-common.cc: ...here. + * common/config/gcn/gcn-common.c: Moved to... + * common/config/gcn/gcn-common.cc: ...here. + * common/config/h8300/h8300-common.c: Moved to... + * common/config/h8300/h8300-common.cc: ...here. + * common/config/i386/i386-common.c: Moved to... + * common/config/i386/i386-common.cc: ...here. + * common/config/ia64/ia64-common.c: Moved to... + * common/config/ia64/ia64-common.cc: ...here. + * common/config/iq2000/iq2000-common.c: Moved to... + * common/config/iq2000/iq2000-common.cc: ...here. + * common/config/lm32/lm32-common.c: Moved to... + * common/config/lm32/lm32-common.cc: ...here. + * common/config/m32r/m32r-common.c: Moved to... + * common/config/m32r/m32r-common.cc: ...here. + * common/config/m68k/m68k-common.c: Moved to... + * common/config/m68k/m68k-common.cc: ...here. + * common/config/mcore/mcore-common.c: Moved to... + * common/config/mcore/mcore-common.cc: ...here. + * common/config/microblaze/microblaze-common.c: Moved to... + * common/config/microblaze/microblaze-common.cc: ...here. + * common/config/mips/mips-common.c: Moved to... + * common/config/mips/mips-common.cc: ...here. + * common/config/mmix/mmix-common.c: Moved to... + * common/config/mmix/mmix-common.cc: ...here. + * common/config/mn10300/mn10300-common.c: Moved to... + * common/config/mn10300/mn10300-common.cc: ...here. + * common/config/msp430/msp430-common.c: Moved to... + * common/config/msp430/msp430-common.cc: ...here. + * common/config/nds32/nds32-common.c: Moved to... + * common/config/nds32/nds32-common.cc: ...here. + * common/config/nios2/nios2-common.c: Moved to... + * common/config/nios2/nios2-common.cc: ...here. + * common/config/nvptx/nvptx-common.c: Moved to... + * common/config/nvptx/nvptx-common.cc: ...here. + * common/config/or1k/or1k-common.c: Moved to... + * common/config/or1k/or1k-common.cc: ...here. + * common/config/pa/pa-common.c: Moved to... + * common/config/pa/pa-common.cc: ...here. + * common/config/pdp11/pdp11-common.c: Moved to... + * common/config/pdp11/pdp11-common.cc: ...here. + * common/config/pru/pru-common.c: Moved to... + * common/config/pru/pru-common.cc: ...here. + * common/config/riscv/riscv-common.c: Moved to... + * common/config/riscv/riscv-common.cc: ...here. + * common/config/rs6000/rs6000-common.c: Moved to... + * common/config/rs6000/rs6000-common.cc: ...here. + * common/config/rx/rx-common.c: Moved to... + * common/config/rx/rx-common.cc: ...here. + * common/config/s390/s390-common.c: Moved to... + * common/config/s390/s390-common.cc: ...here. + * common/config/sh/sh-common.c: Moved to... + * common/config/sh/sh-common.cc: ...here. + * common/config/sparc/sparc-common.c: Moved to... + * common/config/sparc/sparc-common.cc: ...here. + * common/config/tilegx/tilegx-common.c: Moved to... + * common/config/tilegx/tilegx-common.cc: ...here. + * common/config/tilepro/tilepro-common.c: Moved to... + * common/config/tilepro/tilepro-common.cc: ...here. + * common/config/v850/v850-common.c: Moved to... + * common/config/v850/v850-common.cc: ...here. + * common/config/vax/vax-common.c: Moved to... + * common/config/vax/vax-common.cc: ...here. + * common/config/visium/visium-common.c: Moved to... + * common/config/visium/visium-common.cc: ...here. + * common/config/xstormy16/xstormy16-common.c: Moved to... + * common/config/xstormy16/xstormy16-common.cc: ...here. + * common/config/xtensa/xtensa-common.c: Moved to... + * common/config/xtensa/xtensa-common.cc: ...here. + * compare-elim.c: Moved to... + * compare-elim.cc: ...here. + * config/aarch64/aarch64-bti-insert.c: Moved to... + * config/aarch64/aarch64-bti-insert.cc: ...here. + * config/aarch64/aarch64-builtins.c: Moved to... + * config/aarch64/aarch64-builtins.cc: ...here. + * config/aarch64/aarch64-c.c: Moved to... + * config/aarch64/aarch64-c.cc: ...here. + * config/aarch64/aarch64-d.c: Moved to... + * config/aarch64/aarch64-d.cc: ...here. + * config/aarch64/aarch64.c: Moved to... + * config/aarch64/aarch64.cc: ...here. + * config/aarch64/cortex-a57-fma-steering.c: Moved to... + * config/aarch64/cortex-a57-fma-steering.cc: ...here. + * config/aarch64/driver-aarch64.c: Moved to... + * config/aarch64/driver-aarch64.cc: ...here. + * config/aarch64/falkor-tag-collision-avoidance.c: Moved to... + * config/aarch64/falkor-tag-collision-avoidance.cc: ...here. + * config/aarch64/host-aarch64-darwin.c: Moved to... + * config/aarch64/host-aarch64-darwin.cc: ...here. + * config/alpha/alpha.c: Moved to... + * config/alpha/alpha.cc: ...here. + * config/alpha/driver-alpha.c: Moved to... + * config/alpha/driver-alpha.cc: ...here. + * config/arc/arc-c.c: Moved to... + * config/arc/arc-c.cc: ...here. + * config/arc/arc.c: Moved to... + * config/arc/arc.cc: ...here. + * config/arc/driver-arc.c: Moved to... + * config/arc/driver-arc.cc: ...here. + * config/arm/aarch-common.c: Moved to... + * config/arm/aarch-common.cc: ...here. + * config/arm/arm-builtins.c: Moved to... + * config/arm/arm-builtins.cc: ...here. + * config/arm/arm-c.c: Moved to... + * config/arm/arm-c.cc: ...here. + * config/arm/arm-d.c: Moved to... + * config/arm/arm-d.cc: ...here. + * config/arm/arm.c: Moved to... + * config/arm/arm.cc: ...here. + * config/arm/driver-arm.c: Moved to... + * config/arm/driver-arm.cc: ...here. + * config/avr/avr-c.c: Moved to... + * config/avr/avr-c.cc: ...here. + * config/avr/avr-devices.c: Moved to... + * config/avr/avr-devices.cc: ...here. + * config/avr/avr-log.c: Moved to... + * config/avr/avr-log.cc: ...here. + * config/avr/avr.c: Moved to... + * config/avr/avr.cc: ...here. + * config/avr/driver-avr.c: Moved to... + * config/avr/driver-avr.cc: ...here. + * config/avr/gen-avr-mmcu-specs.c: Moved to... + * config/avr/gen-avr-mmcu-specs.cc: ...here. + * config/avr/gen-avr-mmcu-texi.c: Moved to... + * config/avr/gen-avr-mmcu-texi.cc: ...here. + * config/bfin/bfin.c: Moved to... + * config/bfin/bfin.cc: ...here. + * config/bpf/bpf.c: Moved to... + * config/bpf/bpf.cc: ...here. + * config/bpf/coreout.c: Moved to... + * config/bpf/coreout.cc: ...here. + * config/c6x/c6x.c: Moved to... + * config/c6x/c6x.cc: ...here. + * config/cr16/cr16.c: Moved to... + * config/cr16/cr16.cc: ...here. + * config/cris/cris.c: Moved to... + * config/cris/cris.cc: ...here. + * config/csky/csky.c: Moved to... + * config/csky/csky.cc: ...here. + * config/darwin-c.c: Moved to... + * config/darwin-c.cc: ...here. + * config/darwin-d.c: Moved to... + * config/darwin-d.cc: ...here. + * config/darwin-driver.c: Moved to... + * config/darwin-driver.cc: ...here. + * config/darwin-f.c: Moved to... + * config/darwin-f.cc: ...here. + * config/darwin.c: Moved to... + * config/darwin.cc: ...here. + * config/default-c.c: Moved to... + * config/default-c.cc: ...here. + * config/default-d.c: Moved to... + * config/default-d.cc: ...here. + * config/dragonfly-d.c: Moved to... + * config/dragonfly-d.cc: ...here. + * config/epiphany/epiphany.c: Moved to... + * config/epiphany/epiphany.cc: ...here. + * config/epiphany/mode-switch-use.c: Moved to... + * config/epiphany/mode-switch-use.cc: ...here. + * config/epiphany/resolve-sw-modes.c: Moved to... + * config/epiphany/resolve-sw-modes.cc: ...here. + * config/fr30/fr30.c: Moved to... + * config/fr30/fr30.cc: ...here. + * config/freebsd-d.c: Moved to... + * config/freebsd-d.cc: ...here. + * config/frv/frv.c: Moved to... + * config/frv/frv.cc: ...here. + * config/ft32/ft32.c: Moved to... + * config/ft32/ft32.cc: ...here. + * config/gcn/driver-gcn.c: Moved to... + * config/gcn/driver-gcn.cc: ...here. + * config/gcn/gcn-run.c: Moved to... + * config/gcn/gcn-run.cc: ...here. + * config/gcn/gcn-tree.c: Moved to... + * config/gcn/gcn-tree.cc: ...here. + * config/gcn/gcn.c: Moved to... + * config/gcn/gcn.cc: ...here. + * config/gcn/mkoffload.c: Moved to... + * config/gcn/mkoffload.cc: ...here. + * config/glibc-c.c: Moved to... + * config/glibc-c.cc: ...here. + * config/glibc-d.c: Moved to... + * config/glibc-d.cc: ...here. + * config/h8300/h8300.c: Moved to... + * config/h8300/h8300.cc: ...here. + * config/host-darwin.c: Moved to... + * config/host-darwin.cc: ...here. + * config/host-hpux.c: Moved to... + * config/host-hpux.cc: ...here. + * config/host-linux.c: Moved to... + * config/host-linux.cc: ...here. + * config/host-netbsd.c: Moved to... + * config/host-netbsd.cc: ...here. + * config/host-openbsd.c: Moved to... + * config/host-openbsd.cc: ...here. + * config/host-solaris.c: Moved to... + * config/host-solaris.cc: ...here. + * config/i386/djgpp.c: Moved to... + * config/i386/djgpp.cc: ...here. + * config/i386/driver-i386.c: Moved to... + * config/i386/driver-i386.cc: ...here. + * config/i386/driver-mingw32.c: Moved to... + * config/i386/driver-mingw32.cc: ...here. + * config/i386/gnu-property.c: Moved to... + * config/i386/gnu-property.cc: ...here. + * config/i386/host-cygwin.c: Moved to... + * config/i386/host-cygwin.cc: ...here. + * config/i386/host-i386-darwin.c: Moved to... + * config/i386/host-i386-darwin.cc: ...here. + * config/i386/host-mingw32.c: Moved to... + * config/i386/host-mingw32.cc: ...here. + * config/i386/i386-builtins.c: Moved to... + * config/i386/i386-builtins.cc: ...here. + * config/i386/i386-c.c: Moved to... + * config/i386/i386-c.cc: ...here. + * config/i386/i386-d.c: Moved to... + * config/i386/i386-d.cc: ...here. + * config/i386/i386-expand.c: Moved to... + * config/i386/i386-expand.cc: ...here. + * config/i386/i386-features.c: Moved to... + * config/i386/i386-features.cc: ...here. + * config/i386/i386-options.c: Moved to... + * config/i386/i386-options.cc: ...here. + * config/i386/i386.c: Moved to... + * config/i386/i386.cc: ...here. + * config/i386/intelmic-mkoffload.c: Moved to... + * config/i386/intelmic-mkoffload.cc: ...here. + * config/i386/msformat-c.c: Moved to... + * config/i386/msformat-c.cc: ...here. + * config/i386/winnt-cxx.c: Moved to... + * config/i386/winnt-cxx.cc: ...here. + * config/i386/winnt-d.c: Moved to... + * config/i386/winnt-d.cc: ...here. + * config/i386/winnt-stubs.c: Moved to... + * config/i386/winnt-stubs.cc: ...here. + * config/i386/winnt.c: Moved to... + * config/i386/winnt.cc: ...here. + * config/i386/x86-tune-sched-atom.c: Moved to... + * config/i386/x86-tune-sched-atom.cc: ...here. + * config/i386/x86-tune-sched-bd.c: Moved to... + * config/i386/x86-tune-sched-bd.cc: ...here. + * config/i386/x86-tune-sched-core.c: Moved to... + * config/i386/x86-tune-sched-core.cc: ...here. + * config/i386/x86-tune-sched.c: Moved to... + * config/i386/x86-tune-sched.cc: ...here. + * config/ia64/ia64-c.c: Moved to... + * config/ia64/ia64-c.cc: ...here. + * config/ia64/ia64.c: Moved to... + * config/ia64/ia64.cc: ...here. + * config/iq2000/iq2000.c: Moved to... + * config/iq2000/iq2000.cc: ...here. + * config/linux.c: Moved to... + * config/linux.cc: ...here. + * config/lm32/lm32.c: Moved to... + * config/lm32/lm32.cc: ...here. + * config/m32c/m32c-pragma.c: Moved to... + * config/m32c/m32c-pragma.cc: ...here. + * config/m32c/m32c.c: Moved to... + * config/m32c/m32c.cc: ...here. + * config/m32r/m32r.c: Moved to... + * config/m32r/m32r.cc: ...here. + * config/m68k/m68k.c: Moved to... + * config/m68k/m68k.cc: ...here. + * config/mcore/mcore.c: Moved to... + * config/mcore/mcore.cc: ...here. + * config/microblaze/microblaze-c.c: Moved to... + * config/microblaze/microblaze-c.cc: ...here. + * config/microblaze/microblaze.c: Moved to... + * config/microblaze/microblaze.cc: ...here. + * config/mips/driver-native.c: Moved to... + * config/mips/driver-native.cc: ...here. + * config/mips/frame-header-opt.c: Moved to... + * config/mips/frame-header-opt.cc: ...here. + * config/mips/mips-d.c: Moved to... + * config/mips/mips-d.cc: ...here. + * config/mips/mips.c: Moved to... + * config/mips/mips.cc: ...here. + * config/mmix/mmix.c: Moved to... + * config/mmix/mmix.cc: ...here. + * config/mn10300/mn10300.c: Moved to... + * config/mn10300/mn10300.cc: ...here. + * config/moxie/moxie.c: Moved to... + * config/moxie/moxie.cc: ...here. + * config/msp430/driver-msp430.c: Moved to... + * config/msp430/driver-msp430.cc: ...here. + * config/msp430/msp430-c.c: Moved to... + * config/msp430/msp430-c.cc: ...here. + * config/msp430/msp430-devices.c: Moved to... + * config/msp430/msp430-devices.cc: ...here. + * config/msp430/msp430.c: Moved to... + * config/msp430/msp430.cc: ...here. + * config/nds32/nds32-cost.c: Moved to... + * config/nds32/nds32-cost.cc: ...here. + * config/nds32/nds32-fp-as-gp.c: Moved to... + * config/nds32/nds32-fp-as-gp.cc: ...here. + * config/nds32/nds32-intrinsic.c: Moved to... + * config/nds32/nds32-intrinsic.cc: ...here. + * config/nds32/nds32-isr.c: Moved to... + * config/nds32/nds32-isr.cc: ...here. + * config/nds32/nds32-md-auxiliary.c: Moved to... + * config/nds32/nds32-md-auxiliary.cc: ...here. + * config/nds32/nds32-memory-manipulation.c: Moved to... + * config/nds32/nds32-memory-manipulation.cc: ...here. + * config/nds32/nds32-pipelines-auxiliary.c: Moved to... + * config/nds32/nds32-pipelines-auxiliary.cc: ...here. + * config/nds32/nds32-predicates.c: Moved to... + * config/nds32/nds32-predicates.cc: ...here. + * config/nds32/nds32-relax-opt.c: Moved to... + * config/nds32/nds32-relax-opt.cc: ...here. + * config/nds32/nds32-utils.c: Moved to... + * config/nds32/nds32-utils.cc: ...here. + * config/nds32/nds32.c: Moved to... + * config/nds32/nds32.cc: ...here. + * config/netbsd-d.c: Moved to... + * config/netbsd-d.cc: ...here. + * config/netbsd.c: Moved to... + * config/netbsd.cc: ...here. + * config/nios2/nios2.c: Moved to... + * config/nios2/nios2.cc: ...here. + * config/nvptx/mkoffload.c: Moved to... + * config/nvptx/mkoffload.cc: ...here. + * config/nvptx/nvptx-c.c: Moved to... + * config/nvptx/nvptx-c.cc: ...here. + * config/nvptx/nvptx.c: Moved to... + * config/nvptx/nvptx.cc: ...here. + * config/openbsd-d.c: Moved to... + * config/openbsd-d.cc: ...here. + * config/or1k/or1k.c: Moved to... + * config/or1k/or1k.cc: ...here. + * config/pa/pa-d.c: Moved to... + * config/pa/pa-d.cc: ...here. + * config/pa/pa.c: Moved to... + * config/pa/pa.cc: ...here. + * config/pdp11/pdp11.c: Moved to... + * config/pdp11/pdp11.cc: ...here. + * config/pru/pru-passes.c: Moved to... + * config/pru/pru-passes.cc: ...here. + * config/pru/pru-pragma.c: Moved to... + * config/pru/pru-pragma.cc: ...here. + * config/pru/pru.c: Moved to... + * config/pru/pru.cc: ...here. + * config/riscv/riscv-builtins.c: Moved to... + * config/riscv/riscv-builtins.cc: ...here. + * config/riscv/riscv-c.c: Moved to... + * config/riscv/riscv-c.cc: ...here. + * config/riscv/riscv-d.c: Moved to... + * config/riscv/riscv-d.cc: ...here. + * config/riscv/riscv-shorten-memrefs.c: Moved to... + * config/riscv/riscv-shorten-memrefs.cc: ...here. + * config/riscv/riscv-sr.c: Moved to... + * config/riscv/riscv-sr.cc: ...here. + * config/riscv/riscv.c: Moved to... + * config/riscv/riscv.cc: ...here. + * config/rl78/rl78-c.c: Moved to... + * config/rl78/rl78-c.cc: ...here. + * config/rl78/rl78.c: Moved to... + * config/rl78/rl78.cc: ...here. + * config/rs6000/driver-rs6000.c: Moved to... + * config/rs6000/driver-rs6000.cc: ...here. + * config/rs6000/host-darwin.c: Moved to... + * config/rs6000/host-darwin.cc: ...here. + * config/rs6000/host-ppc64-darwin.c: Moved to... + * config/rs6000/host-ppc64-darwin.cc: ...here. + * config/rs6000/rbtree.c: Moved to... + * config/rs6000/rbtree.cc: ...here. + * config/rs6000/rs6000-c.c: Moved to... + * config/rs6000/rs6000-c.cc: ...here. + * config/rs6000/rs6000-call.c: Moved to... + * config/rs6000/rs6000-call.cc: ...here. + * config/rs6000/rs6000-d.c: Moved to... + * config/rs6000/rs6000-d.cc: ...here. + * config/rs6000/rs6000-gen-builtins.c: Moved to... + * config/rs6000/rs6000-gen-builtins.cc: ...here. + * config/rs6000/rs6000-linux.c: Moved to... + * config/rs6000/rs6000-linux.cc: ...here. + * config/rs6000/rs6000-logue.c: Moved to... + * config/rs6000/rs6000-logue.cc: ...here. + * config/rs6000/rs6000-p8swap.c: Moved to... + * config/rs6000/rs6000-p8swap.cc: ...here. + * config/rs6000/rs6000-pcrel-opt.c: Moved to... + * config/rs6000/rs6000-pcrel-opt.cc: ...here. + * config/rs6000/rs6000-string.c: Moved to... + * config/rs6000/rs6000-string.cc: ...here. + * config/rs6000/rs6000.c: Moved to... + * config/rs6000/rs6000.cc: ...here. + * config/rx/rx.c: Moved to... + * config/rx/rx.cc: ...here. + * config/s390/driver-native.c: Moved to... + * config/s390/driver-native.cc: ...here. + * config/s390/s390-c.c: Moved to... + * config/s390/s390-c.cc: ...here. + * config/s390/s390-d.c: Moved to... + * config/s390/s390-d.cc: ...here. + * config/s390/s390.c: Moved to... + * config/s390/s390.cc: ...here. + * config/sh/divtab-sh4-300.c: Moved to... + * config/sh/divtab-sh4-300.cc: ...here. + * config/sh/divtab-sh4.c: Moved to... + * config/sh/divtab-sh4.cc: ...here. + * config/sh/divtab.c: Moved to... + * config/sh/divtab.cc: ...here. + * config/sh/sh-c.c: Moved to... + * config/sh/sh-c.cc: ...here. + * config/sh/sh.c: Moved to... + * config/sh/sh.cc: ...here. + * config/sol2-c.c: Moved to... + * config/sol2-c.cc: ...here. + * config/sol2-cxx.c: Moved to... + * config/sol2-cxx.cc: ...here. + * config/sol2-d.c: Moved to... + * config/sol2-d.cc: ...here. + * config/sol2-stubs.c: Moved to... + * config/sol2-stubs.cc: ...here. + * config/sol2.c: Moved to... + * config/sol2.cc: ...here. + * config/sparc/driver-sparc.c: Moved to... + * config/sparc/driver-sparc.cc: ...here. + * config/sparc/sparc-c.c: Moved to... + * config/sparc/sparc-c.cc: ...here. + * config/sparc/sparc-d.c: Moved to... + * config/sparc/sparc-d.cc: ...here. + * config/sparc/sparc.c: Moved to... + * config/sparc/sparc.cc: ...here. + * config/stormy16/stormy16.c: Moved to... + * config/stormy16/stormy16.cc: ...here. + * config/tilegx/mul-tables.c: Moved to... + * config/tilegx/mul-tables.cc: ...here. + * config/tilegx/tilegx-c.c: Moved to... + * config/tilegx/tilegx-c.cc: ...here. + * config/tilegx/tilegx.c: Moved to... + * config/tilegx/tilegx.cc: ...here. + * config/tilepro/mul-tables.c: Moved to... + * config/tilepro/mul-tables.cc: ...here. + * config/tilepro/tilepro-c.c: Moved to... + * config/tilepro/tilepro-c.cc: ...here. + * config/tilepro/tilepro.c: Moved to... + * config/tilepro/tilepro.cc: ...here. + * config/v850/v850-c.c: Moved to... + * config/v850/v850-c.cc: ...here. + * config/v850/v850.c: Moved to... + * config/v850/v850.cc: ...here. + * config/vax/vax.c: Moved to... + * config/vax/vax.cc: ...here. + * config/visium/visium.c: Moved to... + * config/visium/visium.cc: ...here. + * config/vms/vms-c.c: Moved to... + * config/vms/vms-c.cc: ...here. + * config/vms/vms-f.c: Moved to... + * config/vms/vms-f.cc: ...here. + * config/vms/vms.c: Moved to... + * config/vms/vms.cc: ...here. + * config/vxworks-c.c: Moved to... + * config/vxworks-c.cc: ...here. + * config/vxworks.c: Moved to... + * config/vxworks.cc: ...here. + * config/winnt-c.c: Moved to... + * config/winnt-c.cc: ...here. + * config/xtensa/xtensa.c: Moved to... + * config/xtensa/xtensa.cc: ...here. + * context.c: Moved to... + * context.cc: ...here. + * convert.c: Moved to... + * convert.cc: ...here. + * coverage.c: Moved to... + * coverage.cc: ...here. + * cppbuiltin.c: Moved to... + * cppbuiltin.cc: ...here. + * cppdefault.c: Moved to... + * cppdefault.cc: ...here. + * cprop.c: Moved to... + * cprop.cc: ...here. + * cse.c: Moved to... + * cse.cc: ...here. + * cselib.c: Moved to... + * cselib.cc: ...here. + * ctfc.c: Moved to... + * ctfc.cc: ...here. + * ctfout.c: Moved to... + * ctfout.cc: ...here. + * data-streamer-in.c: Moved to... + * data-streamer-in.cc: ...here. + * data-streamer-out.c: Moved to... + * data-streamer-out.cc: ...here. + * data-streamer.c: Moved to... + * data-streamer.cc: ...here. + * dbgcnt.c: Moved to... + * dbgcnt.cc: ...here. + * dbxout.c: Moved to... + * dbxout.cc: ...here. + * dce.c: Moved to... + * dce.cc: ...here. + * ddg.c: Moved to... + * ddg.cc: ...here. + * debug.c: Moved to... + * debug.cc: ...here. + * df-core.c: Moved to... + * df-core.cc: ...here. + * df-problems.c: Moved to... + * df-problems.cc: ...here. + * df-scan.c: Moved to... + * df-scan.cc: ...here. + * dfp.c: Moved to... + * dfp.cc: ...here. + * diagnostic-color.c: Moved to... + * diagnostic-color.cc: ...here. + * diagnostic-show-locus.c: Moved to... + * diagnostic-show-locus.cc: ...here. + * diagnostic-spec.c: Moved to... + * diagnostic-spec.cc: ...here. + * diagnostic.c: Moved to... + * diagnostic.cc: ...here. + * dojump.c: Moved to... + * dojump.cc: ...here. + * dominance.c: Moved to... + * dominance.cc: ...here. + * domwalk.c: Moved to... + * domwalk.cc: ...here. + * double-int.c: Moved to... + * double-int.cc: ...here. + * dse.c: Moved to... + * dse.cc: ...here. + * dumpfile.c: Moved to... + * dumpfile.cc: ...here. + * dwarf2asm.c: Moved to... + * dwarf2asm.cc: ...here. + * dwarf2cfi.c: Moved to... + * dwarf2cfi.cc: ...here. + * dwarf2ctf.c: Moved to... + * dwarf2ctf.cc: ...here. + * dwarf2out.c: Moved to... + * dwarf2out.cc: ...here. + * early-remat.c: Moved to... + * early-remat.cc: ...here. + * edit-context.c: Moved to... + * edit-context.cc: ...here. + * emit-rtl.c: Moved to... + * emit-rtl.cc: ...here. + * errors.c: Moved to... + * errors.cc: ...here. + * et-forest.c: Moved to... + * et-forest.cc: ...here. + * except.c: Moved to... + * except.cc: ...here. + * explow.c: Moved to... + * explow.cc: ...here. + * expmed.c: Moved to... + * expmed.cc: ...here. + * expr.c: Moved to... + * expr.cc: ...here. + * fibonacci_heap.c: Moved to... + * fibonacci_heap.cc: ...here. + * file-find.c: Moved to... + * file-find.cc: ...here. + * file-prefix-map.c: Moved to... + * file-prefix-map.cc: ...here. + * final.c: Moved to... + * final.cc: ...here. + * fixed-value.c: Moved to... + * fixed-value.cc: ...here. + * fold-const-call.c: Moved to... + * fold-const-call.cc: ...here. + * fold-const.c: Moved to... + * fold-const.cc: ...here. + * fp-test.c: Moved to... + * fp-test.cc: ...here. + * function-tests.c: Moved to... + * function-tests.cc: ...here. + * function.c: Moved to... + * function.cc: ...here. + * fwprop.c: Moved to... + * fwprop.cc: ...here. + * gcc-ar.c: Moved to... + * gcc-ar.cc: ...here. + * gcc-main.c: Moved to... + * gcc-main.cc: ...here. + * gcc-rich-location.c: Moved to... + * gcc-rich-location.cc: ...here. + * gcc.c: Moved to... + * gcc.cc: ...here. + * gcov-dump.c: Moved to... + * gcov-dump.cc: ...here. + * gcov-io.c: Moved to... + * gcov-io.cc: ...here. + * gcov-tool.c: Moved to... + * gcov-tool.cc: ...here. + * gcov.c: Moved to... + * gcov.cc: ...here. + * gcse-common.c: Moved to... + * gcse-common.cc: ...here. + * gcse.c: Moved to... + * gcse.cc: ...here. + * genattr-common.c: Moved to... + * genattr-common.cc: ...here. + * genattr.c: Moved to... + * genattr.cc: ...here. + * genattrtab.c: Moved to... + * genattrtab.cc: ...here. + * genautomata.c: Moved to... + * genautomata.cc: ...here. + * gencfn-macros.c: Moved to... + * gencfn-macros.cc: ...here. + * gencheck.c: Moved to... + * gencheck.cc: ...here. + * genchecksum.c: Moved to... + * genchecksum.cc: ...here. + * gencodes.c: Moved to... + * gencodes.cc: ...here. + * genconditions.c: Moved to... + * genconditions.cc: ...here. + * genconfig.c: Moved to... + * genconfig.cc: ...here. + * genconstants.c: Moved to... + * genconstants.cc: ...here. + * genemit.c: Moved to... + * genemit.cc: ...here. + * genenums.c: Moved to... + * genenums.cc: ...here. + * generic-match-head.c: Moved to... + * generic-match-head.cc: ...here. + * genextract.c: Moved to... + * genextract.cc: ...here. + * genflags.c: Moved to... + * genflags.cc: ...here. + * gengenrtl.c: Moved to... + * gengenrtl.cc: ...here. + * gengtype-parse.c: Moved to... + * gengtype-parse.cc: ...here. + * gengtype-state.c: Moved to... + * gengtype-state.cc: ...here. + * gengtype.c: Moved to... + * gengtype.cc: ...here. + * genhooks.c: Moved to... + * genhooks.cc: ...here. + * genmatch.c: Moved to... + * genmatch.cc: ...here. + * genmddeps.c: Moved to... + * genmddeps.cc: ...here. + * genmddump.c: Moved to... + * genmddump.cc: ...here. + * genmodes.c: Moved to... + * genmodes.cc: ...here. + * genopinit.c: Moved to... + * genopinit.cc: ...here. + * genoutput.c: Moved to... + * genoutput.cc: ...here. + * genpeep.c: Moved to... + * genpeep.cc: ...here. + * genpreds.c: Moved to... + * genpreds.cc: ...here. + * genrecog.c: Moved to... + * genrecog.cc: ...here. + * gensupport.c: Moved to... + * gensupport.cc: ...here. + * gentarget-def.c: Moved to... + * gentarget-def.cc: ...here. + * genversion.c: Moved to... + * genversion.cc: ...here. + * ggc-common.c: Moved to... + * ggc-common.cc: ...here. + * ggc-none.c: Moved to... + * ggc-none.cc: ...here. + * ggc-page.c: Moved to... + * ggc-page.cc: ...here. + * ggc-tests.c: Moved to... + * ggc-tests.cc: ...here. + * gimple-builder.c: Moved to... + * gimple-builder.cc: ...here. + * gimple-expr.c: Moved to... + * gimple-expr.cc: ...here. + * gimple-fold.c: Moved to... + * gimple-fold.cc: ...here. + * gimple-iterator.c: Moved to... + * gimple-iterator.cc: ...here. + * gimple-laddress.c: Moved to... + * gimple-laddress.cc: ...here. + * gimple-loop-jam.c: Moved to... + * gimple-loop-jam.cc: ...here. + * gimple-low.c: Moved to... + * gimple-low.cc: ...here. + * gimple-match-head.c: Moved to... + * gimple-match-head.cc: ...here. + * gimple-pretty-print.c: Moved to... + * gimple-pretty-print.cc: ...here. + * gimple-ssa-backprop.c: Moved to... + * gimple-ssa-backprop.cc: ...here. + * gimple-ssa-evrp-analyze.c: Moved to... + * gimple-ssa-evrp-analyze.cc: ...here. + * gimple-ssa-evrp.c: Moved to... + * gimple-ssa-evrp.cc: ...here. + * gimple-ssa-isolate-paths.c: Moved to... + * gimple-ssa-isolate-paths.cc: ...here. + * gimple-ssa-nonnull-compare.c: Moved to... + * gimple-ssa-nonnull-compare.cc: ...here. + * gimple-ssa-split-paths.c: Moved to... + * gimple-ssa-split-paths.cc: ...here. + * gimple-ssa-sprintf.c: Moved to... + * gimple-ssa-sprintf.cc: ...here. + * gimple-ssa-store-merging.c: Moved to... + * gimple-ssa-store-merging.cc: ...here. + * gimple-ssa-strength-reduction.c: Moved to... + * gimple-ssa-strength-reduction.cc: ...here. + * gimple-ssa-warn-alloca.c: Moved to... + * gimple-ssa-warn-alloca.cc: ...here. + * gimple-ssa-warn-restrict.c: Moved to... + * gimple-ssa-warn-restrict.cc: ...here. + * gimple-streamer-in.c: Moved to... + * gimple-streamer-in.cc: ...here. + * gimple-streamer-out.c: Moved to... + * gimple-streamer-out.cc: ...here. + * gimple-walk.c: Moved to... + * gimple-walk.cc: ...here. + * gimple-warn-recursion.c: Moved to... + * gimple-warn-recursion.cc: ...here. + * gimple.c: Moved to... + * gimple.cc: ...here. + * gimplify-me.c: Moved to... + * gimplify-me.cc: ...here. + * gimplify.c: Moved to... + * gimplify.cc: ...here. + * godump.c: Moved to... + * godump.cc: ...here. + * graph.c: Moved to... + * graph.cc: ...here. + * graphds.c: Moved to... + * graphds.cc: ...here. + * graphite-dependences.c: Moved to... + * graphite-dependences.cc: ...here. + * graphite-isl-ast-to-gimple.c: Moved to... + * graphite-isl-ast-to-gimple.cc: ...here. + * graphite-optimize-isl.c: Moved to... + * graphite-optimize-isl.cc: ...here. + * graphite-poly.c: Moved to... + * graphite-poly.cc: ...here. + * graphite-scop-detection.c: Moved to... + * graphite-scop-detection.cc: ...here. + * graphite-sese-to-poly.c: Moved to... + * graphite-sese-to-poly.cc: ...here. + * graphite.c: Moved to... + * graphite.cc: ...here. + * haifa-sched.c: Moved to... + * haifa-sched.cc: ...here. + * hash-map-tests.c: Moved to... + * hash-map-tests.cc: ...here. + * hash-set-tests.c: Moved to... + * hash-set-tests.cc: ...here. + * hash-table.c: Moved to... + * hash-table.cc: ...here. + * hooks.c: Moved to... + * hooks.cc: ...here. + * host-default.c: Moved to... + * host-default.cc: ...here. + * hw-doloop.c: Moved to... + * hw-doloop.cc: ...here. + * hwint.c: Moved to... + * hwint.cc: ...here. + * ifcvt.c: Moved to... + * ifcvt.cc: ...here. + * inchash.c: Moved to... + * inchash.cc: ...here. + * incpath.c: Moved to... + * incpath.cc: ...here. + * init-regs.c: Moved to... + * init-regs.cc: ...here. + * input.c: Moved to... + * input.cc: ...here. + * internal-fn.c: Moved to... + * internal-fn.cc: ...here. + * intl.c: Moved to... + * intl.cc: ...here. + * ipa-comdats.c: Moved to... + * ipa-comdats.cc: ...here. + * ipa-cp.c: Moved to... + * ipa-cp.cc: ...here. + * ipa-devirt.c: Moved to... + * ipa-devirt.cc: ...here. + * ipa-fnsummary.c: Moved to... + * ipa-fnsummary.cc: ...here. + * ipa-icf-gimple.c: Moved to... + * ipa-icf-gimple.cc: ...here. + * ipa-icf.c: Moved to... + * ipa-icf.cc: ...here. + * ipa-inline-analysis.c: Moved to... + * ipa-inline-analysis.cc: ...here. + * ipa-inline-transform.c: Moved to... + * ipa-inline-transform.cc: ...here. + * ipa-inline.c: Moved to... + * ipa-inline.cc: ...here. + * ipa-modref-tree.c: Moved to... + * ipa-modref-tree.cc: ...here. + * ipa-modref.c: Moved to... + * ipa-modref.cc: ...here. + * ipa-param-manipulation.c: Moved to... + * ipa-param-manipulation.cc: ...here. + * ipa-polymorphic-call.c: Moved to... + * ipa-polymorphic-call.cc: ...here. + * ipa-predicate.c: Moved to... + * ipa-predicate.cc: ...here. + * ipa-profile.c: Moved to... + * ipa-profile.cc: ...here. + * ipa-prop.c: Moved to... + * ipa-prop.cc: ...here. + * ipa-pure-const.c: Moved to... + * ipa-pure-const.cc: ...here. + * ipa-ref.c: Moved to... + * ipa-ref.cc: ...here. + * ipa-reference.c: Moved to... + * ipa-reference.cc: ...here. + * ipa-split.c: Moved to... + * ipa-split.cc: ...here. + * ipa-sra.c: Moved to... + * ipa-sra.cc: ...here. + * ipa-utils.c: Moved to... + * ipa-utils.cc: ...here. + * ipa-visibility.c: Moved to... + * ipa-visibility.cc: ...here. + * ipa.c: Moved to... + * ipa.cc: ...here. + * ira-build.c: Moved to... + * ira-build.cc: ...here. + * ira-color.c: Moved to... + * ira-color.cc: ...here. + * ira-conflicts.c: Moved to... + * ira-conflicts.cc: ...here. + * ira-costs.c: Moved to... + * ira-costs.cc: ...here. + * ira-emit.c: Moved to... + * ira-emit.cc: ...here. + * ira-lives.c: Moved to... + * ira-lives.cc: ...here. + * ira.c: Moved to... + * ira.cc: ...here. + * jump.c: Moved to... + * jump.cc: ...here. + * langhooks.c: Moved to... + * langhooks.cc: ...here. + * lcm.c: Moved to... + * lcm.cc: ...here. + * lists.c: Moved to... + * lists.cc: ...here. + * loop-doloop.c: Moved to... + * loop-doloop.cc: ...here. + * loop-init.c: Moved to... + * loop-init.cc: ...here. + * loop-invariant.c: Moved to... + * loop-invariant.cc: ...here. + * loop-iv.c: Moved to... + * loop-iv.cc: ...here. + * loop-unroll.c: Moved to... + * loop-unroll.cc: ...here. + * lower-subreg.c: Moved to... + * lower-subreg.cc: ...here. + * lra-assigns.c: Moved to... + * lra-assigns.cc: ...here. + * lra-coalesce.c: Moved to... + * lra-coalesce.cc: ...here. + * lra-constraints.c: Moved to... + * lra-constraints.cc: ...here. + * lra-eliminations.c: Moved to... + * lra-eliminations.cc: ...here. + * lra-lives.c: Moved to... + * lra-lives.cc: ...here. + * lra-remat.c: Moved to... + * lra-remat.cc: ...here. + * lra-spills.c: Moved to... + * lra-spills.cc: ...here. + * lra.c: Moved to... + * lra.cc: ...here. + * lto-cgraph.c: Moved to... + * lto-cgraph.cc: ...here. + * lto-compress.c: Moved to... + * lto-compress.cc: ...here. + * lto-opts.c: Moved to... + * lto-opts.cc: ...here. + * lto-section-in.c: Moved to... + * lto-section-in.cc: ...here. + * lto-section-out.c: Moved to... + * lto-section-out.cc: ...here. + * lto-streamer-in.c: Moved to... + * lto-streamer-in.cc: ...here. + * lto-streamer-out.c: Moved to... + * lto-streamer-out.cc: ...here. + * lto-streamer.c: Moved to... + * lto-streamer.cc: ...here. + * lto-wrapper.c: Moved to... + * lto-wrapper.cc: ...here. + * main.c: Moved to... + * main.cc: ...here. + * mcf.c: Moved to... + * mcf.cc: ...here. + * mode-switching.c: Moved to... + * mode-switching.cc: ...here. + * modulo-sched.c: Moved to... + * modulo-sched.cc: ...here. + * multiple_target.c: Moved to... + * multiple_target.cc: ...here. + * omp-expand.c: Moved to... + * omp-expand.cc: ...here. + * omp-general.c: Moved to... + * omp-general.cc: ...here. + * omp-low.c: Moved to... + * omp-low.cc: ...here. + * omp-offload.c: Moved to... + * omp-offload.cc: ...here. + * omp-simd-clone.c: Moved to... + * omp-simd-clone.cc: ...here. + * opt-suggestions.c: Moved to... + * opt-suggestions.cc: ...here. + * optabs-libfuncs.c: Moved to... + * optabs-libfuncs.cc: ...here. + * optabs-query.c: Moved to... + * optabs-query.cc: ...here. + * optabs-tree.c: Moved to... + * optabs-tree.cc: ...here. + * optabs.c: Moved to... + * optabs.cc: ...here. + * opts-common.c: Moved to... + * opts-common.cc: ...here. + * opts-global.c: Moved to... + * opts-global.cc: ...here. + * opts.c: Moved to... + * opts.cc: ...here. + * passes.c: Moved to... + * passes.cc: ...here. + * plugin.c: Moved to... + * plugin.cc: ...here. + * postreload-gcse.c: Moved to... + * postreload-gcse.cc: ...here. + * postreload.c: Moved to... + * postreload.cc: ...here. + * predict.c: Moved to... + * predict.cc: ...here. + * prefix.c: Moved to... + * prefix.cc: ...here. + * pretty-print.c: Moved to... + * pretty-print.cc: ...here. + * print-rtl-function.c: Moved to... + * print-rtl-function.cc: ...here. + * print-rtl.c: Moved to... + * print-rtl.cc: ...here. + * print-tree.c: Moved to... + * print-tree.cc: ...here. + * profile-count.c: Moved to... + * profile-count.cc: ...here. + * profile.c: Moved to... + * profile.cc: ...here. + * read-md.c: Moved to... + * read-md.cc: ...here. + * read-rtl-function.c: Moved to... + * read-rtl-function.cc: ...here. + * read-rtl.c: Moved to... + * read-rtl.cc: ...here. + * real.c: Moved to... + * real.cc: ...here. + * realmpfr.c: Moved to... + * realmpfr.cc: ...here. + * recog.c: Moved to... + * recog.cc: ...here. + * ree.c: Moved to... + * ree.cc: ...here. + * reg-stack.c: Moved to... + * reg-stack.cc: ...here. + * regcprop.c: Moved to... + * regcprop.cc: ...here. + * reginfo.c: Moved to... + * reginfo.cc: ...here. + * regrename.c: Moved to... + * regrename.cc: ...here. + * regstat.c: Moved to... + * regstat.cc: ...here. + * reload.c: Moved to... + * reload.cc: ...here. + * reload1.c: Moved to... + * reload1.cc: ...here. + * reorg.c: Moved to... + * reorg.cc: ...here. + * resource.c: Moved to... + * resource.cc: ...here. + * rtl-error.c: Moved to... + * rtl-error.cc: ...here. + * rtl-tests.c: Moved to... + * rtl-tests.cc: ...here. + * rtl.c: Moved to... + * rtl.cc: ...here. + * rtlanal.c: Moved to... + * rtlanal.cc: ...here. + * rtlhash.c: Moved to... + * rtlhash.cc: ...here. + * rtlhooks.c: Moved to... + * rtlhooks.cc: ...here. + * rtx-vector-builder.c: Moved to... + * rtx-vector-builder.cc: ...here. + * run-rtl-passes.c: Moved to... + * run-rtl-passes.cc: ...here. + * sancov.c: Moved to... + * sancov.cc: ...here. + * sanopt.c: Moved to... + * sanopt.cc: ...here. + * sbitmap.c: Moved to... + * sbitmap.cc: ...here. + * sched-deps.c: Moved to... + * sched-deps.cc: ...here. + * sched-ebb.c: Moved to... + * sched-ebb.cc: ...here. + * sched-rgn.c: Moved to... + * sched-rgn.cc: ...here. + * sel-sched-dump.c: Moved to... + * sel-sched-dump.cc: ...here. + * sel-sched-ir.c: Moved to... + * sel-sched-ir.cc: ...here. + * sel-sched.c: Moved to... + * sel-sched.cc: ...here. + * selftest-diagnostic.c: Moved to... + * selftest-diagnostic.cc: ...here. + * selftest-rtl.c: Moved to... + * selftest-rtl.cc: ...here. + * selftest-run-tests.c: Moved to... + * selftest-run-tests.cc: ...here. + * selftest.c: Moved to... + * selftest.cc: ...here. + * sese.c: Moved to... + * sese.cc: ...here. + * shrink-wrap.c: Moved to... + * shrink-wrap.cc: ...here. + * simplify-rtx.c: Moved to... + * simplify-rtx.cc: ...here. + * sparseset.c: Moved to... + * sparseset.cc: ...here. + * spellcheck-tree.c: Moved to... + * spellcheck-tree.cc: ...here. + * spellcheck.c: Moved to... + * spellcheck.cc: ...here. + * sreal.c: Moved to... + * sreal.cc: ...here. + * stack-ptr-mod.c: Moved to... + * stack-ptr-mod.cc: ...here. + * statistics.c: Moved to... + * statistics.cc: ...here. + * stmt.c: Moved to... + * stmt.cc: ...here. + * stor-layout.c: Moved to... + * stor-layout.cc: ...here. + * store-motion.c: Moved to... + * store-motion.cc: ...here. + * streamer-hooks.c: Moved to... + * streamer-hooks.cc: ...here. + * stringpool.c: Moved to... + * stringpool.cc: ...here. + * substring-locations.c: Moved to... + * substring-locations.cc: ...here. + * symtab.c: Moved to... + * symtab.cc: ...here. + * target-globals.c: Moved to... + * target-globals.cc: ...here. + * targhooks.c: Moved to... + * targhooks.cc: ...here. + * timevar.c: Moved to... + * timevar.cc: ...here. + * toplev.c: Moved to... + * toplev.cc: ...here. + * tracer.c: Moved to... + * tracer.cc: ...here. + * trans-mem.c: Moved to... + * trans-mem.cc: ...here. + * tree-affine.c: Moved to... + * tree-affine.cc: ...here. + * tree-call-cdce.c: Moved to... + * tree-call-cdce.cc: ...here. + * tree-cfg.c: Moved to... + * tree-cfg.cc: ...here. + * tree-cfgcleanup.c: Moved to... + * tree-cfgcleanup.cc: ...here. + * tree-chrec.c: Moved to... + * tree-chrec.cc: ...here. + * tree-complex.c: Moved to... + * tree-complex.cc: ...here. + * tree-data-ref.c: Moved to... + * tree-data-ref.cc: ...here. + * tree-dfa.c: Moved to... + * tree-dfa.cc: ...here. + * tree-diagnostic.c: Moved to... + * tree-diagnostic.cc: ...here. + * tree-dump.c: Moved to... + * tree-dump.cc: ...here. + * tree-eh.c: Moved to... + * tree-eh.cc: ...here. + * tree-emutls.c: Moved to... + * tree-emutls.cc: ...here. + * tree-if-conv.c: Moved to... + * tree-if-conv.cc: ...here. + * tree-inline.c: Moved to... + * tree-inline.cc: ...here. + * tree-into-ssa.c: Moved to... + * tree-into-ssa.cc: ...here. + * tree-iterator.c: Moved to... + * tree-iterator.cc: ...here. + * tree-loop-distribution.c: Moved to... + * tree-loop-distribution.cc: ...here. + * tree-nested.c: Moved to... + * tree-nested.cc: ...here. + * tree-nrv.c: Moved to... + * tree-nrv.cc: ...here. + * tree-object-size.c: Moved to... + * tree-object-size.cc: ...here. + * tree-outof-ssa.c: Moved to... + * tree-outof-ssa.cc: ...here. + * tree-parloops.c: Moved to... + * tree-parloops.cc: ...here. + * tree-phinodes.c: Moved to... + * tree-phinodes.cc: ...here. + * tree-predcom.c: Moved to... + * tree-predcom.cc: ...here. + * tree-pretty-print.c: Moved to... + * tree-pretty-print.cc: ...here. + * tree-profile.c: Moved to... + * tree-profile.cc: ...here. + * tree-scalar-evolution.c: Moved to... + * tree-scalar-evolution.cc: ...here. + * tree-sra.c: Moved to... + * tree-sra.cc: ...here. + * tree-ssa-address.c: Moved to... + * tree-ssa-address.cc: ...here. + * tree-ssa-alias.c: Moved to... + * tree-ssa-alias.cc: ...here. + * tree-ssa-ccp.c: Moved to... + * tree-ssa-ccp.cc: ...here. + * tree-ssa-coalesce.c: Moved to... + * tree-ssa-coalesce.cc: ...here. + * tree-ssa-copy.c: Moved to... + * tree-ssa-copy.cc: ...here. + * tree-ssa-dce.c: Moved to... + * tree-ssa-dce.cc: ...here. + * tree-ssa-dom.c: Moved to... + * tree-ssa-dom.cc: ...here. + * tree-ssa-dse.c: Moved to... + * tree-ssa-dse.cc: ...here. + * tree-ssa-forwprop.c: Moved to... + * tree-ssa-forwprop.cc: ...here. + * tree-ssa-ifcombine.c: Moved to... + * tree-ssa-ifcombine.cc: ...here. + * tree-ssa-live.c: Moved to... + * tree-ssa-live.cc: ...here. + * tree-ssa-loop-ch.c: Moved to... + * tree-ssa-loop-ch.cc: ...here. + * tree-ssa-loop-im.c: Moved to... + * tree-ssa-loop-im.cc: ...here. + * tree-ssa-loop-ivcanon.c: Moved to... + * tree-ssa-loop-ivcanon.cc: ...here. + * tree-ssa-loop-ivopts.c: Moved to... + * tree-ssa-loop-ivopts.cc: ...here. + * tree-ssa-loop-manip.c: Moved to... + * tree-ssa-loop-manip.cc: ...here. + * tree-ssa-loop-niter.c: Moved to... + * tree-ssa-loop-niter.cc: ...here. + * tree-ssa-loop-prefetch.c: Moved to... + * tree-ssa-loop-prefetch.cc: ...here. + * tree-ssa-loop-split.c: Moved to... + * tree-ssa-loop-split.cc: ...here. + * tree-ssa-loop-unswitch.c: Moved to... + * tree-ssa-loop-unswitch.cc: ...here. + * tree-ssa-loop.c: Moved to... + * tree-ssa-loop.cc: ...here. + * tree-ssa-math-opts.c: Moved to... + * tree-ssa-math-opts.cc: ...here. + * tree-ssa-operands.c: Moved to... + * tree-ssa-operands.cc: ...here. + * tree-ssa-phiopt.c: Moved to... + * tree-ssa-phiopt.cc: ...here. + * tree-ssa-phiprop.c: Moved to... + * tree-ssa-phiprop.cc: ...here. + * tree-ssa-pre.c: Moved to... + * tree-ssa-pre.cc: ...here. + * tree-ssa-propagate.c: Moved to... + * tree-ssa-propagate.cc: ...here. + * tree-ssa-reassoc.c: Moved to... + * tree-ssa-reassoc.cc: ...here. + * tree-ssa-sccvn.c: Moved to... + * tree-ssa-sccvn.cc: ...here. + * tree-ssa-scopedtables.c: Moved to... + * tree-ssa-scopedtables.cc: ...here. + * tree-ssa-sink.c: Moved to... + * tree-ssa-sink.cc: ...here. + * tree-ssa-strlen.c: Moved to... + * tree-ssa-strlen.cc: ...here. + * tree-ssa-structalias.c: Moved to... + * tree-ssa-structalias.cc: ...here. + * tree-ssa-tail-merge.c: Moved to... + * tree-ssa-tail-merge.cc: ...here. + * tree-ssa-ter.c: Moved to... + * tree-ssa-ter.cc: ...here. + * tree-ssa-threadbackward.c: Moved to... + * tree-ssa-threadbackward.cc: ...here. + * tree-ssa-threadedge.c: Moved to... + * tree-ssa-threadedge.cc: ...here. + * tree-ssa-threadupdate.c: Moved to... + * tree-ssa-threadupdate.cc: ...here. + * tree-ssa-uncprop.c: Moved to... + * tree-ssa-uncprop.cc: ...here. + * tree-ssa-uninit.c: Moved to... + * tree-ssa-uninit.cc: ...here. + * tree-ssa.c: Moved to... + * tree-ssa.cc: ...here. + * tree-ssanames.c: Moved to... + * tree-ssanames.cc: ...here. + * tree-stdarg.c: Moved to... + * tree-stdarg.cc: ...here. + * tree-streamer-in.c: Moved to... + * tree-streamer-in.cc: ...here. + * tree-streamer-out.c: Moved to... + * tree-streamer-out.cc: ...here. + * tree-streamer.c: Moved to... + * tree-streamer.cc: ...here. + * tree-switch-conversion.c: Moved to... + * tree-switch-conversion.cc: ...here. + * tree-tailcall.c: Moved to... + * tree-tailcall.cc: ...here. + * tree-vect-data-refs.c: Moved to... + * tree-vect-data-refs.cc: ...here. + * tree-vect-generic.c: Moved to... + * tree-vect-generic.cc: ...here. + * tree-vect-loop-manip.c: Moved to... + * tree-vect-loop-manip.cc: ...here. + * tree-vect-loop.c: Moved to... + * tree-vect-loop.cc: ...here. + * tree-vect-patterns.c: Moved to... + * tree-vect-patterns.cc: ...here. + * tree-vect-slp-patterns.c: Moved to... + * tree-vect-slp-patterns.cc: ...here. + * tree-vect-slp.c: Moved to... + * tree-vect-slp.cc: ...here. + * tree-vect-stmts.c: Moved to... + * tree-vect-stmts.cc: ...here. + * tree-vector-builder.c: Moved to... + * tree-vector-builder.cc: ...here. + * tree-vectorizer.c: Moved to... + * tree-vectorizer.cc: ...here. + * tree-vrp.c: Moved to... + * tree-vrp.cc: ...here. + * tree.c: Moved to... + * tree.cc: ...here. + * tsan.c: Moved to... + * tsan.cc: ...here. + * typed-splay-tree.c: Moved to... + * typed-splay-tree.cc: ...here. + * ubsan.c: Moved to... + * ubsan.cc: ...here. + * valtrack.c: Moved to... + * valtrack.cc: ...here. + * value-prof.c: Moved to... + * value-prof.cc: ...here. + * var-tracking.c: Moved to... + * var-tracking.cc: ...here. + * varasm.c: Moved to... + * varasm.cc: ...here. + * varpool.c: Moved to... + * varpool.cc: ...here. + * vec-perm-indices.c: Moved to... + * vec-perm-indices.cc: ...here. + * vec.c: Moved to... + * vec.cc: ...here. + * vmsdbgout.c: Moved to... + * vmsdbgout.cc: ...here. + * vr-values.c: Moved to... + * vr-values.cc: ...here. + * vtable-verify.c: Moved to... + * vtable-verify.cc: ...here. + * web.c: Moved to... + * web.cc: ...here. + * xcoffout.c: Moved to... + * xcoffout.cc: ...here. + +2022-01-17 qing zhao <qing.zhao@oracle.com> + + * tree-ssa-uninit.c (warn_uninit): Delete the 4th parameter. Handle + .DEFERRED_INIT call with an anonymous SSA_NAME specially. + (check_defs): Handle .DEFERRED_INIT call with an anonymous SSA_NAME + specially. + (warn_uninit_phi_uses): Delete the 4th actual when call warn_uninit. + (warn_uninitialized_vars): Likewise. + (warn_uninitialized_phi): Likewise. + +2022-01-17 Jason Merrill <jason@redhat.com> + + * diagnostic.h (struct diagnostic_context): Add includes_seen. + * diagnostic.c (diagnostic_initialize): Initialize it. + (diagnostic_finish): Clean it up. + (includes_seen): New function. + (diagnostic_report_current_module): Use it. + +2022-01-17 Richard Biener <rguenther@suse.de> + + PR middle-end/101292 + * diagnostic-spec.c (copy_warning): Make sure to not + reference old hashtable content on possible resize. + * warning-control.cc (copy_warning): Likewise. + +2022-01-17 Jakub Jelinek <jakub@redhat.com> + + PR target/103973 + * tree-cfg.h (cond_only_block_p): Declare. + * tree-ssa-phiopt.c (cond_only_block_p): Move function to ... + * tree-cfg.c (cond_only_block_p): ... here. No longer static. + * optabs.def (spaceship_optab): New optab. + * internal-fn.def (SPACESHIP): New internal function. + * internal-fn.h (expand_SPACESHIP): Declare. + * internal-fn.c (expand_PHI): Formatting fix. + (expand_SPACESHIP): New function. + * tree-ssa-math-opts.c (optimize_spaceship): New function. + (math_opts_dom_walker::after_dom_children): Use it. + * config/i386/i386.md (spaceship<mode>3): New define_expand. + * config/i386/i386-protos.h (ix86_expand_fp_spaceship): Declare. + * config/i386/i386-expand.c (ix86_expand_fp_spaceship): New function. + * doc/md.texi (spaceship@var{m}3): Document. + +2022-01-17 Kewen Lin <linkw@linux.ibm.com> + + * config/rs6000/altivec.md (altivec_vreveti2): Remove. + * config/rs6000/vsx.md (*vsx_extract_si, *vsx_extract_si_<uns>float_df, + *vsx_extract_si_<uns>float_<mode>, *vsx_insert_extract_v4sf_p9): Use + known constant values to simplify code. + +2022-01-17 Haochen Gui <guihaoc@gcc.gnu.org> + + PR target/103124 + * config/rs6000/vsx.md (split pattern for TI to V1TI move): Defined. + +2022-01-16 wwwhhhyyy <hongyu.wang@intel.com> + + * config/i386/i386.h (TARGET_DEST_FALSE_DEP_FOR_GLC): New macro. + * config/i386/sse.md (<avx512>_<complexopname>_<mode><maskc_name><round_name>): + Insert zero-idiom in output template when attr enabled, set new attribute to + true for non-mask/maskz insn. + (avx512fp16_<complexopname>sh_v8hf<mask_scalarc_name><round_scalarcz_name>): + Likewise. + (avx512dq_mul<mode>3<mask_name>): Likewise. + (<avx2_avx512>_permvar<mode><mask_name>): Likewise. + (avx2_perm<mode>_1<mask_name>): Likewise. + (avx512f_perm<mode>_1<mask_name>): Likewise. + (avx512dq_rangep<mode><mask_name><round_saeonly_name>): Likewise. + (avx512dq_ranges<mode><mask_scalar_name><round_saeonly_scalar_name>): + Likewise. + (<avx512>_getmant<mode><mask_name><round_saeonly_name>): Likewise. + (avx512f_vgetmant<mode><mask_scalar_name><round_saeonly_scalar_name>): + Likewise. + * config/i386/subst.md (mask3_dest_false_dep_for_glc_cond): New + subst_attr. + (mask4_dest_false_dep_for_glc_cond): Likewise. + (mask6_dest_false_dep_for_glc_cond): Likewise. + (mask10_dest_false_dep_for_glc_cond): Likewise. + (maskc_dest_false_dep_for_glc_cond): Likewise. + (mask_scalar4_dest_false_dep_for_glc_cond): Likewise. + (mask_scalarc_dest_false_dep_for_glc_cond): Likewise. + * config/i386/x86-tune.def (X86_TUNE_DEST_FALSE_DEP_FOR_GLC): New + DEF_TUNE enabled for m_SAPPHIRERAPIDS and m_ALDERLAKE + +2022-01-15 Martin Sebor <msebor@redhat.com> + + PR c/63272 + * diagnostic-spec.c (nowarn_spec_t::nowarn_spec_t): Handle + -Wdangling-pointer. + * doc/invoke.texi (-Wdangling-pointer): Document new option. + * gimple-ssa-warn-access.cc (pass_waccess::clone): Set new member. + (pass_waccess::check_pointer_uses): New function. + (pass_waccess::gimple_call_return_arg): New function. + (pass_waccess::gimple_call_return_arg_ref): New function. + (pass_waccess::check_call_dangling): New function. + (pass_waccess::check_dangling_uses): New function overloads. + (pass_waccess::check_dangling_stores): New function. + (pass_waccess::check_dangling_stores): New function. + (pass_waccess::m_clobbers): New data member. + (pass_waccess::m_func): New data member. + (pass_waccess::m_run_number): New data member. + (pass_waccess::m_check_dangling_p): New data member. + (pass_waccess::check_alloca): Check m_early_checks_p. + (pass_waccess::check_alloc_size_call): Same. + (pass_waccess::check_strcat): Same. + (pass_waccess::check_strncat): Same. + (pass_waccess::check_stxcpy): Same. + (pass_waccess::check_stxncpy): Same. + (pass_waccess::check_strncmp): Same. + (pass_waccess::check_memop_access): Same. + (pass_waccess::check_read_access): Same. + (pass_waccess::check_builtin): Call check_pointer_uses. + (pass_waccess::warn_invalid_pointer): Add arguments. + (is_auto_decl): New function. + (pass_waccess::check_stmt): New function. + (pass_waccess::check_block): Call check_stmt. + (pass_waccess::execute): Call check_dangling_uses, + check_dangling_stores. Empty m_clobbers. + * passes.def (pass_warn_access): Invoke pass two more times. + +2022-01-15 Martin Sebor <msebor@redhat.com> + + PR tree-optimization/80532 + * common.opt (-Wuse-after-free): New options. + * diagnostic-spec.c (nowarn_spec_t::nowarn_spec_t): Handle + OPT_Wreturn_local_addr and OPT_Wuse_after_free_. + * diagnostic-spec.h (NW_DANGLING): New enumerator. + * doc/invoke.texi (-Wuse-after-free): Document new option. + * gimple-ssa-warn-access.cc (pass_waccess::check_call): Rename... + (pass_waccess::check_call_access): ...to this. + (pass_waccess::check): Rename... + (pass_waccess::check_block): ...to this. + (pass_waccess::check_pointer_uses): New function. + (pass_waccess::gimple_call_return_arg): New function. + (pass_waccess::warn_invalid_pointer): New function. + (pass_waccess::check_builtin): Handle free and realloc. + (gimple_use_after_inval_p): New function. + (get_realloc_lhs): New function. + (maybe_warn_mismatched_realloc): New function. + (pointers_related_p): New function. + (pass_waccess::check_call): Call check_pointer_uses. + (pass_waccess::execute): Compute and free dominance info. + +2022-01-15 Uroš Bizjak <ubizjak@gmail.com> + + * config/i386/i386-expand.c (ix86_expand_sse_movcc): Use + expand_simple_unop and expand_simple_binop instead of manually + constructing NOT, AND and IOR RTXes. Use vector_all_ones_operand + consistently. Eliminate common subexpressions and simplify code. + * config/i386/sse.md (<any_logic:code><MODEF:mode>3): New expander. + (<any_logic:code><MODEF:mode>3): Make public. + +2022-01-14 Eric Botcazou <ebotcazou@adacore.com> + + * ipa-param-manipulation.c (ipa_dump_adjusted_parameters): Dump + reverse flag as "reverse" for the sake of consistency. + * ipa-sra.c: Fix copyright year. + (ipa_sra_function_summaries::duplicate): Copy the reverse flag. + (dump_isra_access): Tweak dump line. + (isra_write_node_summary): Write the reverse flag. + (isra_read_node_info): Read it. + (pull_accesses_from_callee): Test its consistency and copy it. + +2022-01-14 Richard Sandiford <richard.sandiford@arm.com> + + PR middle-end/104026 + * tree-vect-loop.c (_loop_vec_info::_loop_vec_info): Initialize + partial_load_store_bias. + +2022-01-14 Martin Sebor <msebor@redhat.com> + + PR middle-end/101475 + * pointer-query.cc (handle_component_ref): Use the size of + the enclosing object if it's smaller than the member. + +2022-01-14 Martin Liska <mliska@suse.cz> + + * configure: Regenerate. + +2022-01-14 Uroš Bizjak <ubizjak@gmail.com> + + * config/i386/i386.md (*add<mode>_1_slp"): + Mark alternative 1 output operand earlyclobbered. + (*sub<mode>_1_slp): Ditto. + (*and<mode>_1_slp): Ditto. + (*<code><mode>_1_slp): Ditto. + (*neg<mode>_1_slp): Ditto. + (*one_cmpl<mode>_1_slp): Ditto. + (*ashl<mode>3_1_slp): Ditto. + (*<insn><mode>3_1_slp): Ditto. + (*<insn><mode>3_1_slp): Ditto. + +2022-01-14 Kewen Lin <linkw@linux.ibm.com> + + PR tree-optimization/104015 + * tree-vect-loop.c (vect_analyze_loop): Check + param_vect_partial_vector_usage for supports_partial_vectors. + +2022-01-14 Jakub Jelinek <jakub@redhat.com> + + PR c++/89074 + * fold-const.c (address_compare): Punt on comparison of address of + one object with address of end of another object if + folding_initializer. + +2022-01-14 Jakub Jelinek <jakub@redhat.com> + + PR target/98737 + * tree-ssa-forwprop.c (simplify_builtin_call): Canonicalize + __atomic_fetch_op (p, x, y) op x into __atomic_op_fetch (p, x, y) + and __atomic_op_fetch (p, x, y) iop x into + __atomic_fetch_op (p, x, y). + +2022-01-14 Claudiu Zissulescu <claziss@synopsys.com> + + * config/arc/arc.h (DWARF_FRAME_REGNUM): Update definition. + (DWARF_FRAME_RETURN_COLUMN): Use RETURN_ADDR_REGNUM macro. + (INCOMING_RETURN_ADDR_RTX): Likewise. + (DWARF_ALT_FRAME_RETURN_COLUMN): Define. + +2022-01-14 Claudiu Zissulescu <claziss@synopsys.com> + + * config/arc/arc.c (arc_compute_frame_size): Remove condition when + computin checking accumulator regs. + (arc_expand_prologue): Update comments. + (arc_expand_epilogue): Likewise. + +2022-01-14 Roger Sayle <roger@nextmovesoftware.com> + Uroš Bizjak <ubizjak@gmail.com> + + * config/i386/i386-expand.c (ix86_expand_v1ti_to_ti): Use force_reg. + (ix86_expand_ti_to_v1ti): Use force_reg. + (ix86_expand_v1ti_shift): Use force_reg. + (ix86_expand_v1ti_rotate): Use force_reg. + (ix86_expand_v1ti_ashiftrt): Provide new three operation + implementations for shifts by 111..126 bits. Use force_reg. + +2022-01-14 Martin Liska <mliska@suse.cz> + + * common/config/arm/arm-common.c (arm_target_mode): Fix + warning: unterminated quoting directive [-Wformat=]. + +2022-01-14 Siddhesh Poyarekar <siddhesh@gotplt.org> + + PR tree-optimization/104009 + * tree-object-size.c (compute_builtin_object_size): Bail out on + negative offset. + (plus_stmt_object_size): Return maximum of wholesize and minimum + of 0 for negative offset. + +2022-01-14 liuhongt <hongtao.liu@intel.com> + + PR target/104001 + PR target/94790 + PR target/104014 + * config/i386/i386.md (*xor2andn): Refine predicate of + operands[0] from nonimmediate_operand to + register_operand, remove TARGET_AVX512BW from condition. + +2022-01-14 David Malcolm <dmalcolm@redhat.com> + + * doc/extend.texi (Function Attributes): Note that "tainted_args" can + be used on field decls. + (Common Function Attributes): Add entry on "tainted_args" attribute. + +2022-01-13 Anthony Sharp <anthonysharp15@gmail.com> + Jason Merrill <jason@redhat.com> + + PR c++/70417 + * doc/invoke.texi: Documentation for Wmissing-template-keyword. + +2022-01-13 Uroš Bizjak <ubizjak@gmail.com> + + PR target/103861 + * config/i386/i386.md (*ashlqi_ext<mode>_2): New insn pattern. + (*<any_shiftrt:insn>qi_ext<mode>_2): Ditto. + * config/i386/mmx.md (<any_shift:insn>v2qi): + New insn_and_split pattern. + +2022-01-13 Robin Dapp <rdapp@linux.ibm.com> + + * internal-fn.c (expand_partial_load_optab_fn): Add bias. + (expand_partial_store_optab_fn): Likewise. + (internal_len_load_store_bias): New function. + * internal-fn.h (VECT_PARTIAL_BIAS_UNSUPPORTED): New define. + (internal_len_load_store_bias): New function. + * tree-vect-loop-manip.c (vect_set_loop_controls_directly): Set bias. + (vect_set_loop_condition_partial_vectors): Add header_seq parameter. + * tree-vect-loop.c (vect_verify_loop_lens): Verify bias. + (vect_estimate_min_profitable_iters): Account for bias. + (vect_get_loop_len): Add bias-adjusted length. + * tree-vect-stmts.c (vectorizable_store): Use. + (vectorizable_load): Use. + * tree-vectorizer.h (struct rgroup_controls): Add bias-adjusted length. + (LOOP_VINFO_PARTIAL_LOAD_STORE_BIAS): New macro. + * config/rs6000/vsx.md: Use const0 bias predicate. + * doc/md.texi: Document bias value. + +2022-01-13 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/83072 + PR tree-optimization/83073 + PR tree-optimization/97909 + * fold-const.c (expr_not_equal_to): Use a multi-range class. + +2022-01-13 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/96707 + * range-op.cc (operator_rshift::lhs_op1_relation): New. + +2022-01-13 Uroš Bizjak <ubizjak@gmail.com> + + * config/i386/mmx.md (negv2qi): Disparage GPR alternative a bit. + Disable for TARGET_PARTIAL_REG_STALL unless optimizing for size. + (negv2qi splitters): Use lowpart_subreg instead of + gen_lowpart to create subreg. + (<plusminus:insn>v2qi3): Disparage GPR alternative a bit. + Disable for TARGET_PARTIAL_REG_STALL unless optimizing for size. + (<plusminus:insn>v2qi3 splitters): Use lowpart_subreg instead of + gen_lowpart to create subreg. + * config/i386/i386.md (*subqi_ext<mode>_2): Move. + +2022-01-13 Uroš Bizjak <ubizjak@gmail.com> + + PR target/104003 + * config/i386/mmx.md (*xop_pcmov_<mode>): Use VI_16_32 mode iterator. + +2022-01-13 Martin Liska <mliska@suse.cz> + + * common/config/arm/arm-common.c (arm_target_mode): Wrap + keywords with %<, %> and remove trailing punctuation char. + (arm_canon_arch_option_1): Likewise. + (arm_asm_auto_mfpu): Likewise. + * config/arm/arm-builtins.c (arm_expand_builtin): Likewise. + * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Likewise. + (use_vfp_abi): Likewise. + (aapcs_vfp_is_call_or_return_candidate): Likewise. + (arm_handle_cmse_nonsecure_entry): Likewise. + (arm_handle_cmse_nonsecure_call): Likewise. + (thumb1_md_asm_adjust): Likewise. + +2022-01-13 Paul A. Clarke <pc@us.ibm.com> + + * config/rs6000/smmintrin.h (_mm_round_pd, _mm_round_ps, + _mm_round_sd, _mm_round_ss, _MM_FROUND_TO_NEAREST_INT, + _MM_FROUND_TO_ZERO, _MM_FROUND_TO_POS_INF, _MM_FROUND_TO_NEG_INF, + _MM_FROUND_CUR_DIRECTION, _MM_FROUND_RAISE_EXC, _MM_FROUND_NO_EXC, + _MM_FROUND_NINT, _MM_FROUND_FLOOR, _MM_FROUND_CEIL, _MM_FROUND_TRUNC, + _MM_FROUND_RINT, _MM_FROUND_NEARBYINT): New. + (_mm_ceil_pd, _mm_ceil_ps, _mm_ceil_sd, _mm_ceil_ss, _mm_floor_pd, + _mm_floor_ps, _mm_floor_sd, _mm_floor_ss): Convert from function to + macro. + +2022-01-13 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/103989 + * tree-inline.c (setup_one_parameter): Don't copy parms with + empty type. + +2022-01-13 Thomas Schwinge <thomas@codesourcery.com> + + * tree-streamer-out.c (pack_ts_base_value_fields): Don't pack + 'TYPE_ADDR_SPACE' for offloading. + * tree-streamer-in.c (unpack_ts_base_value_fields): Don't unpack + 'TYPE_ADDR_SPACE' for offloading. + +2022-01-13 Julian Brown <julian@codesourcery.com> + Thomas Schwinge <thomas@codesourcery.com> + + * omp-oacc-kernels-decompose.cc (add_wait): New function, split out + of... + (add_async_clauses_and_wait): ...here. Call new outlined function. + (decompose_kernels_region_body): Add wait at the end of + explicitly-asynchronous kernels regions. + +2022-01-13 Thomas Schwinge <thomas@codesourcery.com> + + PR middle-end/100280 + * omp-oacc-kernels-decompose.cc (maybe_build_inner_data_region): + Mark variables used in synthesized data clauses as addressable. + +2022-01-13 Martin Liska <mliska@suse.cz> + + * config/epiphany/epiphany.c (epiphany_mode_priority): + Use gcc_unreachable for not handled cases. + +2022-01-13 Martin Liska <mliska@suse.cz> + + * config/epiphany/epiphany.c (epiphany_handle_interrupt_attribute): + Use %qs format specifier. + (epiphany_override_options): Wrap keyword in %<, %>. + +2022-01-13 Haochen Jiang <haochen.jiang@intel.com> + + PR target/94790 + * config/i386/i386.md (*xor2andn): New define_insn_and_split. + +2022-01-13 Xionghu Luo <luoxhu@linux.ibm.com> + + * config/rs6000/altivec.md (sldoi_to_mov<mode>): New. + +2022-01-12 Uroš Bizjak <ubizjak@gmail.com> + + PR target/100637 + PR target/103861 + * config/i386/i386-expand.c (ix86_emit_vec_binop): New static function. + (ix86_expand_sse_movcc): Use ix86_emit_vec_binop instead of gen_rtx_X + when constructing vector logic RTXes. + (expand_vec_perm_pshufb2): Ditto. + * config/i386/mmx.md (negv2qi): Disparage GPR alternative a bit. + (<plusminus:insn>v2qi3): Ditto. + (vcond<mode><mode>): Re-enable for TARGET_SSE2. + (vcondu<mode><mode>): Ditto. + (vcond_mask_<mode><mode>): Ditto. + (one_cmpl<VI_32:mode>2): Remove expander. + (one_cmpl<VI_16_32:mode>2): Rename from one_cmplv2qi. + Use VI_16_32 mode iterator. + (one_cmpl<VI_16_32:mode>2 splitters): Use VI_16_32 mode iterator. + Use lowpart_subreg instead of gen_lowpart to create subreg. + (*andnot<VI_16_32:mode>3): Merge from "*andnot<VI_32:mode>" and + "*andnotv2qi3" insn patterns using VI_16_32 mode iterator. + Disparage GPR alternative a bit. Add CC clobber. + (*andnot<VI_16_32:mode>3 splitters): Use VI_16_32 mode iterator. + Use lowpart_subreg instead of gen_lowpart to create subreg. + (*<any_logic:code><VI_16_32:mode>3): Merge from + "*<any_logic:code><VI_32:mode>" and "*<any_logic:code>v2qi3" insn patterns + using VI_16_32 mode iterator. Disparage GPR alternative a bit. + Add CC clobber. + (*<any_logic:code><VI_16_32:mode>3 splitters):Use VI_16_32 mode + iterator. Use lowpart_subreg instead of gen_lowpart to create subreg. + +2022-01-12 Clément Chigot <clement.chigot@atos.net> + + * configure.ac: Check sizeof ino_t and dev_t. + (HOST_STAT_FOR_64BIT_INODES): New AC_DEFINE to provide stat + syscall being able to handle 64bit inodes. + * config.in: Regenerate. + * configure: Regenerate. + * incpath.c (HOST_STAT_FOR_64BIT_INODES): New define. + (remove_duplicates): Use it. + +2022-01-12 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/103551 + * tree-vrp.c (execute_ranger_vrp): Always set EDGE_EXECUTABLE. + +2022-01-12 Richard Biener <rguenther@suse.de> + + PR tree-optimization/103990 + * tree-pass.h (tail_merge_optimize): Drop unused argument. + * tree-ssa-tail-merge.c (tail_merge_optimize): Likewise. + * tree-ssa-pre.c (pass_pre::execute): Retain TODO_cleanup_cfg + and adjust call to tail_merge_optimize. + +2022-01-12 Andre Vieira <andre.simoesdiasvieira@arm.com> + + * tree-vect-loop.c (vect-analyze-loop): Handle scenario where target + does not add autovectorize_vector_modes. + +2022-01-12 Martin Liska <mliska@suse.cz> + + * config/aarch64/aarch64.c (aarch64_parse_boolean_options): Use + %qs where possible. + (aarch64_parse_sve_width_string): Likewise. + (aarch64_override_options_internal): Likewise. + (aarch64_print_hint_for_extensions): Likewise. + (aarch64_validate_sls_mitigation): Likewise. + (aarch64_handle_attr_arch): Likewise. + (aarch64_handle_attr_cpu): Likewise. + (aarch64_handle_attr_tune): Likewise. + (aarch64_handle_attr_isa_flags): Likewise. + +2022-01-12 Martin Liska <mliska@suse.cz> + + * config.gcc: Include elfos.h before ${tm_file}. + +2022-01-12 Hans-Peter Nilsson <hp@axis.com> + + * config/cris/cris.c: Quote identifiers in parameters to error + and internal_error, and remove extraneous spaces with punctuation. + * config/cris/cris.h (CRIS_ASSERT): When passing on stringified + expression to internal_error, pass it as a parameter instead of + appending it to the format part. + +2022-01-12 Hans-Peter Nilsson <hp@axis.com> + + * config/cris/cris.c (cris_postdbr_cmpelim): Parenthesize + parameter to as_a. + +2022-01-11 qing zhao <qing.zhao@oracle.com> + + * gimplify.c (gimple_add_init_for_auto_var): Delete the 3rd argument. + Change the 3rd argument of function .DEFERRED_INIT to the name of the + decl. + (gimplify_decl_expr): Delete the 3rd argument when call + gimple_add_init_for_auto_var. + * internal-fn.c (expand_DEFERRED_INIT): Update comments to reflect + the 3rd argument change of function .DEFERRED_INIT. + * tree-cfg.c (verify_gimple_call): Update comments and verification + to reflect the 3rd argument change of function .DEFERRED_INIT. + * tree-sra.c (generate_subtree_deferred_init): Delete the 3rd argument. + (sra_modify_deferred_init): Change the 3rd argument of function + .DEFERRED_INIT to the name of the decl. + +2022-01-11 Thomas Koenig <tkoenig@gcc.gnu.org> + + * flag-types.h (enum gfc_convert): Add flags for + conversion. + +2022-01-11 Michael Meissner <meissner@the-meissners.org> + + * config/rs6000/rs6000.c (rs6000_option_override_internal): Remove + checks for only C/C++ front ends before allowing the long double + format to change without a warning. + +2022-01-11 Richard Sandiford <richard.sandiford@arm.com> + + PR rtl-optimization/103974 + * ira-int.h (ira_subloop_allocnos_can_differ_p): Take an + extra argument, default true, that says whether old-reload + targets should be excluded. + * ira-color.c (color_pass): Pass false. + +2022-01-11 Uroš Bizjak <ubizjak@gmail.com> + + PR target/103861 + * config/i386/mmx.md (vcond<mode><mode>): + Use VI_16_32 mode iterator. Enable for TARGET_SSE4_1. + (vcondu<mode><mode>): Ditto. + (vcond_mask_<mode><mode>): Ditto. + (mmx_pblendvb_v8qi): Rename from mmx_pblendvb64. + (mmx_pblendvb_<mode>): Rename from mmx_pblendvb32. + Use VI_16_32 mode iterator. + * config/i386/i386-expand.c (ix86_expand_sse_movcc): + Update for rename. Handle V2QImode. + (expand_vec_perm_blend): Update for rename. + +2022-01-11 Jakub Jelinek <jakub@redhat.com> + + PR c++/101597 + * tree.def (OBJ_TYPE_REF): Document type of OBJ_TYPE_REF_TOKEN. + +2022-01-11 Siddhesh Poyarekar <siddhesh@gotplt.org> + + PR middle-end/70090 + * tree-object-size.c (size_valid_p): New function. + (size_for_offset): Remove OFFSET constness assertion. + (addr_object_size): Build dynamic expressions for object + sizes and use size_valid_p to decide if it is valid for the + given OBJECT_SIZE_TYPE. + (compute_builtin_object_size): Allow dynamic offsets when + computing size at O0. + (call_object_size): Call size_valid_p. + (plus_stmt_object_size): Allow non-constant offset and use + size_valid_p to decide if it is valid for the given + OBJECT_SIZE_TYPE. + +2022-01-11 Siddhesh Poyarekar <siddhesh@gotplt.org> + + PR middle-end/70090 + * tree-object-size.c (alloc_object_size): Make and return + non-constant size expression. + (call_object_size): Return expression or unknown based on + whether dynamic object size is requested. + +2022-01-11 Siddhesh Poyarekar <siddhesh@gotplt.org> + + PR middle-end/70090 + * tree-object-size.c: Include tree-dfa.h. + (parm_object_size): New function. + (collect_object_sizes_for): Call it. + +2022-01-11 Siddhesh Poyarekar <siddhesh@gotplt.org> + + PR middle-end/70090 + * builtins.c (fold_builtin_object_size): Adjust for dynamic size + expressions. + * tree-object-size.c: Include gimplify-me.h. + (struct object_size_info): New member UNKNOWNS. + (size_initval_p, size_usable_p, object_sizes_get_raw): New + functions. + (object_sizes_get): Return suitable gimple variable for + object size. + (bundle_sizes): New function. + (object_sizes_set): Use it and handle dynamic object size + expressions. + (object_sizes_set_temp): New function. + (size_for_offset): Adjust for dynamic size expressions. + (emit_phi_nodes, propagate_unknowns, gimplify_size_expressions): + New functions. + (compute_builtin_object_size): Call gimplify_size_expressions + for OST_DYNAMIC. + (dynamic_object_size): New function. + (cond_expr_object_size): Use it. + (phi_dynamic_object_size): New function. + (collect_object_sizes_for): Call it for OST_DYNAMIC. Adjust to + accommodate dynamic object sizes. + +2022-01-11 Siddhesh Poyarekar <siddhesh@gotplt.org> + Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/103961 + * tree-object-size.c (plus_stmt_object_size): Always avoid + computing offset for -1 size. + +2022-01-11 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/103821 + * range-op.cc (range_operator::fold_range): Only do precise ranges + when there are not too many subranges. + +2022-01-11 Richard Sandiford <richard.sandiford@arm.com> + + * ira-costs.c (ira_tune_allocno_costs): Fix missing rclass + definition in IRA_HARD_REGNO_ADD_COST_MULTIPLIER code. + +2022-01-11 Roger Sayle <roger@nextmovesoftware.com> + Richard Biener <rguenther@suse.de> + + * tree-ssa-math-opts.c (struct widen_mul_stats): Add a + highpart_mults_inserted field. + (convert_mult_to_highpart): New function to convert right shift + of a widening multiply into a MULT_HIGHPART_EXPR. + (math_opts_dom_walker::after_dom_children) [RSHIFT_EXPR]: + Call new convert_mult_to_highpart function. + (pass_optimize_widening_mul::execute): Add a statistics counter + for tracking "highpart multiplications inserted" events. + +2022-01-11 Xionghu Luo <luoxhu@linux.ibm.com> + + PR target/102239 + * config/rs6000/rs6000-protos.h (rs6000_is_valid_rotate_dot_mask): New + declare. + * config/rs6000/rs6000.c (rs6000_is_valid_rotate_dot_mask): New + function. + * config/rs6000/rs6000.md (*branch_anddi3_dot): New. + +2022-01-11 Olivier Hainque <hainque@adacore.com> + + * gcc.c (driver_handle_option): State --sysroot as + validated. + +2022-01-11 Kewen Lin <linkw@linux.ibm.com> + + * config/rs6000/rs6000.c (rs6000_disable_incompatible_switches): Remove + useless related to option -mno-power10. + +2022-01-11 Haochen Jiang <haochen.jiang@intel.com> + + PR target/53652 + * config/i386/sse.md (*andnot<mode>3): Extend predicate of + operands[1] from register_operand to vector_operand. + +2022-01-10 Uroš Bizjak <ubizjak@gmail.com> + + PR target/103861 + * config/i386/i386-expand.c (ix86_expand_int_sse_cmp): + Handle V2QImode. + * config/i386/mmx.md (<sat_plusminus:insn><mode>3): + Use VI1_16_32 mode iterator. + (*eq<mode>3): Ditto. + (*gt<mode>3): Ditto. + (*xop_maskcmp<mode>3): Ditto. + (*xop_maskcmp_uns<mode>3): Ditto. + (vec_cmp<mode><mode>): Ditto. + (vec_cmpu<mode><mode>): Ditto. + +2022-01-10 Richard Biener <rguenther@suse.de> + + PR tree-optimization/103948 + * tree-vect-generic.c (expand_vector_condition): Return true if + all ones vector is returned for true, all zeros vector for false + and the target defines corresponding vec_cmp{,u}MN named RTX pattern. + +2022-01-10 Paul A. Clarke <pc@us.ibm.com> + + * config/rs6000/smmintrin.h (_mm_blendv_epi8): Use vec_blendv + when _ARCH_PWR10. Use signed types. + (_mm_blendv_ps): Use vec_blendv when _ARCH_PWR10. + (_mm_blendv_pd): Likewise. + +2022-01-10 Andre Vieira <andre.simoesdiasvieira@arm.com> + + * tree-vectorizer.c (better_epilogue_loop_than_p): Round factors up for + epilogue costing. + * tree-vect-loop.c (vect_analyze_loop): Re-analyze all modes for + epilogues, unless we are guaranteed that we can't have partial vectors. + * genopinit.c: (partial_vectors_supported): Generate new function. + +2022-01-10 Jakub Jelinek <jakub@redhat.com> + + PR target/102024 + * config/i386/i386.c (classify_argument): Add zero_width_bitfields + argument, when seeing DECL_FIELD_CXX_ZERO_WIDTH_BIT_FIELD bitfields, + always ignore them, when seeing other zero sized bitfields, either + set zero_width_bitfields to 1 and ignore it or if equal to 2 process + it. Pass it to recursive calls. Add wrapper + with old arguments and diagnose ABI differences for C structures + with zero width bitfields. Formatting fixes. + +2022-01-10 Richard Sandiford <richard.sandiford@arm.com> + + PR rtl-optimization/98782 + * ira-int.h (ira_soft_conflict): Declare. + * ira-color.c (max_soft_conflict_loop_depth): New constant. + (ira_soft_conflict): New function. + (spill_soft_conflicts): Likewise. + (assign_hard_reg): Use them to handle the case described by + the comment above ira_soft_conflict. + (improve_allocation): Likewise. + * ira.c (check_allocation): Allow allocnos with "soft" conflicts + to share the same register. + +2022-01-10 Richard Sandiford <richard.sandiford@arm.com> + + PR rtl-optimization/98782 + * ira-int.h (ira_caller_save_cost): New function. + (ira_caller_save_loop_spill_p): Likewise. + * ira-build.c (ira_propagate_hard_reg_costs): Test whether it is + cheaper to spill a call-clobbered register throughout a loop rather + than spill it around each individual call. If so, treat all + call-clobbered registers as conflicts and... + (propagate_allocno_info): ...do not propagate call information + from the child to the parent. + * ira-color.c (move_spill_restore): Update accordingly. + * ira-costs.c (ira_tune_allocno_costs): Use ira_caller_save_cost. + +2022-01-10 Richard Sandiford <richard.sandiford@arm.com> + + PR rtl-optimization/98782 + * ira-int.h (ira_allocno::might_conflict_with_parent_p): New field. + (ALLOCNO_MIGHT_CONFLICT_WITH_PARENT_P): New macro. + (ira_single_region_allocno_p): New function. + (ira_total_conflict_hard_regs): Likewise. + * ira-build.c (ira_create_allocno): Initialize + ALLOCNO_MIGHT_CONFLICT_WITH_PARENT_P. + (ira_propagate_hard_reg_costs): New function. + (propagate_allocno_info): Use it. Try to avoid propagating + hard register conflicts to parent allocnos if we can handle + the conflicts by spilling instead. Limit the propagated + register costs to the cost of spilling throughout the child loop. + * ira-color.c (color_pass): Use ira_single_region_allocno_p to + test whether a child and parent allocno can share the same + register. + (move_spill_restore): Adjust for the new behavior of + propagate_allocno_info. + +2022-01-10 Richard Sandiford <richard.sandiford@arm.com> + + PR rtl-optimization/98782 + * ira-int.h (ira_subloop_allocnos_can_differ_p): New function, + extracted from... + * ira-color.c (color_pass): ...here. + +2022-01-10 Richard Sandiford <richard.sandiford@arm.com> + + PR rtl-optimization/98782 + * ira-color.c (color_pass): Add comments to describe the spill costs. + (move_spill_restore): Likewise. Fix reversed calculation. + +2022-01-10 Richard Sandiford <richard.sandiford@arm.com> + + PR rtl-optimization/98782 + * ira-int.h (ira_loop_border_costs): New class. + * ira-color.c (ira_loop_border_costs::ira_loop_border_costs): + New constructor. + (calculate_allocno_spill_cost): Use ira_loop_border_costs. + (color_pass): Likewise. + (move_spill_restore): Likewise. + +2022-01-10 Eric Botcazou <ebotcazou@adacore.com> + + PR target/103465 + * coretypes.h (unwind_info_type): Swap UI_SEH and UI_TARGET. + +2022-01-10 Richard Biener <rguenther@suse.de> + + PR tree-optimization/100359 + * tree-ssa-loop-ivcanon.c (try_unroll_loop_completely): + Allow non-growing peeling with !allow_peel and UL_ALL. + +2022-01-08 Roger Sayle <roger@nextmovesoftware.com> + + * config/i386/i386-expand.c (ix86_expand_vector_move): Add + special case for TImode to V1TImode moves, going via V2DImode. + +2022-01-08 Jakub Jelinek <jakub@redhat.com> + + PR c++/89074 + * match.pd ((ptr) (x p+ y) p+ z -> (ptr) (x p+ (y + z))): New GENERIC + simplification. + +2022-01-08 David Malcolm <dmalcolm@redhat.com> + + * doc/analyzer.texi + (Special Functions for Debugging the Analyzer): Document + __analyzer_dump_escaped. + +2022-01-08 David Malcolm <dmalcolm@redhat.com> + + * doc/analyzer.texi (Other Debugging Techniques): Document + region::is_named_decl_p. + +2022-01-07 Andrew Pinski <apinski@marvell.com> + + PR target/102941 + * config/arm/aarch-common.c (arm_md_asm_adjust): + Use a temp if !REG_P. + +2022-01-07 Uroš Bizjak <ubizjak@gmail.com> + + * config/i386/mmx.md (*move<V_32:mode>_internal): Add isa attribute. + (*movv2qi_internal): Remve sse2 requirement for alternatives 4,5. + +2022-01-07 liuhongt <hongtao.liu@intel.com> + + PR rtl-optimization/103750 + * fwprop.c (forward_propagate_into): Allow propagations from + inner loop to outer loop. + +2022-01-07 Roger Sayle <roger@nextmovesoftware.com> + + * config/nvptx/nvptx.md (*cnot<mode>2): New define_insn. + +2022-01-07 Haochen Gui <guihaoc@gcc.gnu.org> + + * config/rs6000/rs6000.md (rs6000_mffscrni): Define. + (rs6000_set_fpscr_rn): Change the type of operand[0] from DI to SI. + Call gen_rs6000_mffscrni when operand[0] is a const_0_to_3_operand. + +2022-01-07 liuhongt <hongtao.liu@intel.com> + + * config/i386/sse.md + (*<avx512>_eq<mode>3<mask_scalar_merge_name>_1): Extend to + UNSPEC_PCMP_UNSIGNED. + +2022-01-07 liuhongt <hongtao.liu@intel.com> + + PR target/103753 + * config/i386/i386-expand.c (ix86_expand_vector_set): Not use + gen_avx2_pblendph_1 when elt == 0. + * config/i386/sse.md (avx2_pblendph): Rename to .. + (avx2_pblend<ssemodesuffix>_1).. this, and extend to V16HI. + (*avx2_pblendw): Rename to .. + (*avx2_pblend<ssemodesuffix>): .. this, and extend to V16HF. + (avx2_pblendw): Rename to .. + (*avx2_pblend<ssemodesuffix>): .. this, and extend to V16HF. + (blendsuf): Removed. + (sse4_1_pblend<blendsuf>): Renamed to .. + (sse4_1_pblend<ssemodesuffix>): .. this. + +2022-01-06 H.J. Lu <hjl.tools@gmail.com> + + PR target/103925 + * config/i386/i386.c (ix86_output_indirect_function_return): + Generate INT3 after indirect jmp for -mharden-sls=indirect-jmp. + +2022-01-06 H.J. Lu <hjl.tools@gmail.com> + + PR target/102952 + * config/i386/i386-opts.h (harden_sls): Replace + harden_sls_indirect_branch with harden_sls_indirect_jmp. + * config/i386/i386.c (ix86_output_jmp_thunk_or_indirect): + Likewise. + (ix86_output_indirect_jmp): Likewise. + (ix86_output_call_insn): Likewise. + * config/i386/i386.opt: Replace indirect-branch with + indirect-jmp. Replace harden_sls_indirect_branch with + harden_sls_indirect_jmp. + * doc/invoke.texi (-harden-sls=): Replace indirect-branch with + indirect-jmp. + +2022-01-06 Uroš Bizjak <ubizjak@gmail.com> + + * config/i386/i386.c (ix86_output_ssemov) <MODE_DI>: + Add %q modifier for operands in general registers. + <MODE_SI>: Add %q modifier for operands in general registers. + * config/i386/i386.md (*movhi_internal): Change type attribute of + xmm-gpr interunit alternatives 9,10 to ssemov and mode attribute + to SImode for non-avx512fp16 targets. + (*movhf_internal): Ditto for xmm-gpr interunit alternatives 6,8. + * config/i386/mmx.md (*movv2qi_internal): + Ditto for xmm-gpr interunit alternatives 8,9. + +2022-01-06 Kito Cheng <kito.cheng@sifive.com> + + * common/config/riscv/riscv-common.c (riscv_implied_info): Add + vector extensions. + (riscv_ext_version_table): Add version info for vector extensions. + (riscv_ext_flag_table): Add option mask for vector extensions. + * config/riscv/riscv-opts.h (MASK_VECTOR_EEW_32): New. + (MASK_VECTOR_EEW_64): New. + (MASK_VECTOR_EEW_FP_32): New. + (MASK_VECTOR_EEW_FP_64): New. + (MASK_ZVL32B): New. + (MASK_ZVL64B): New. + (MASK_ZVL128B): New. + (MASK_ZVL256B): New. + (MASK_ZVL512B): New. + (MASK_ZVL1024B): New. + (MASK_ZVL2048B): New. + (MASK_ZVL4096B): New. + (MASK_ZVL8192B): New. + (MASK_ZVL16384B): New. + (MASK_ZVL32768B): New. + (MASK_ZVL65536B): New. + (TARGET_ZVL32B): New. + (TARGET_ZVL64B): New. + (TARGET_ZVL128B): New. + (TARGET_ZVL256B): New. + (TARGET_ZVL512B): New. + (TARGET_ZVL1024B): New. + (TARGET_ZVL2048B): New. + (TARGET_ZVL4096B): New. + (TARGET_ZVL8192B): New. + (TARGET_ZVL16384B): New. + (TARGET_ZVL32768B): New. + (TARGET_ZVL65536B): New. + * config/riscv/riscv.opt (Mask(VECTOR)): New. + (riscv_vector_eew_flags): New. + (riscv_zvl_flags): New. + +2022-01-06 Kito Cheng <kito.cheng@sifive.com> + + * common/config/riscv/riscv-common.c + (riscv_subset_list::parse_multiletter_ext): Allow ext. name has + digit. + +2022-01-06 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/103899 + * expr.c (expand_expr_real_1): Add a workaround for bogus uninit + warning by moving context variable to the only spot where it is used + and moving gcc_assert into if body. + +2022-01-06 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/103908 + * ifcvt.c (bb_valid_for_noce_process_p): Punt on bbs ending with + asm goto. + +2022-01-05 Bill Schmidt <wschmidt@linux.ibm.com> + + PR target/103622 + * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): + Skip over instances with undefined function types. + +2022-01-05 Andrew Pinski <apinski@marvell.com> + + PR target/103910 + * config/i386/i386.h (x86_mfence): Mark with GTY. + +2022-01-05 Uroš Bizjak <ubizjak@gmail.com> + + PR target/103861 + * config/i386/mmx.md (VI_16_32): New mode iterator. + (VI1_16_32): Ditto. + (mmxvecsize): Handle V2QI mode. + (<smaxmin:code><mode>3): Rename from <smaxmin:code>v4qi3. + Use VI1_16_32 mode iterator. + (<umaxmin:code><mode>3): Rename from <umaxmin:code>v4qi3. + Use VI1_16_32 mode iterator. + (abs<mode>2): Use VI_16_32 mode iterator. + (uavgv2qi3_ceil): New insn pattern. + +2022-01-05 Martin Sebor <msebor@redhat.com> + + * gimple-ssa-warn-access.cc (pass_waccess::maybe_warn_memmodel): Use + %qs to avoid -Wformat-diag. + +2022-01-05 Uroš Bizjak <ubizjak@gmail.com> + + PR target/103915 + * config/i386/mmx.md (one_cmplv2qi2): Change + alternatives 1,2 type from sselog to sselog1. + +2022-01-05 Uroš Bizjak <ubizjak@gmail.com> + + PR target/103905 + * config/i386/i386-expand.c (expand_vec_perm_pshufb): Fix number of + narrow mode remapped elements for !one_operand_p case. + +2022-01-05 Richard Biener <rguenther@suse.de> + + PR tree-optimization/103816 + * tree-vect-data-refs.c (vect_analyze_group_access_1): Also + check DR_GROUP_GAP compute for overflow and representability. + +2022-01-05 Jakub Jelinek <jakub@redhat.com> + + PR fortran/103691 + * gimple-fold.c (fold_stmt_1): Don't call maybe_fold_reference + for DEBUG stmts with ADDR_EXPR gimple_debug_bind_get_value, + it can do unwanted rhs folding like &a[0] into &2.0 etc. + +2022-01-05 Kewen Lin <linkw@linux.ibm.com> + + PR ipa/102059 + * config/rs6000/rs6000.c (TARGET_NEED_IPA_FN_TARGET_INFO): New macro. + (TARGET_UPDATE_IPA_FN_TARGET_INFO): Likewise. + (rs6000_need_ipa_fn_target_info): New function. + (rs6000_update_ipa_fn_target_info): Likewise. + (rs6000_can_inline_p): Adjust for ipa function summary target info. + * config/rs6000/rs6000.h (RS6000_FN_TARGET_INFO_HTM): New macro. + * ipa-fnsummary.c (ipa_dump_fn_summary): Adjust for ipa function + summary target info. + (analyze_function_body): Adjust for ipa function summary target info + and call hook rs6000_need_ipa_fn_target_info and + rs6000_update_ipa_fn_target_info. + (ipa_merge_fn_summary_after_inlining): Adjust for ipa function summary + target info. + (inline_read_section): Likewise. + (ipa_fn_summary_write): Likewise. + * ipa-fnsummary.h (ipa_fn_summary::target_info): New member. + * doc/tm.texi: Regenerate. + * doc/tm.texi.in (TARGET_UPDATE_IPA_FN_TARGET_INFO): Document new hook. + (TARGET_NEED_IPA_FN_TARGET_INFO): Likewise. + * target.def (update_ipa_fn_target_info): New hook. + (need_ipa_fn_target_info): Likewise. + * targhooks.c (default_need_ipa_fn_target_info): New function. + (default_update_ipa_fn_target_info): Likewise. + * targhooks.h (default_update_ipa_fn_target_info): New declare. + (default_need_ipa_fn_target_info): Likewise. + +2022-01-04 Martin Sebor <msebor@redhat.com> + + PR middle-end/99612 + * builtins.c (get_memmodel): Move warning code to + gimple-ssa-warn-access.cc. + (expand_builtin_atomic_compare_exchange): Same. + (expand_ifn_atomic_compare_exchange): Same. + (expand_builtin_atomic_load): Same. + (expand_builtin_atomic_store): Same. + (expand_builtin_atomic_clear): Same. + * doc/extend.texi (__atomic_exchange_n): Update valid memory + models. + * gimple-ssa-warn-access.cc (memmodel_to_uhwi): New function. + (struct memmodel_pair): New struct. + (memmodel_name): New function. + (pass_waccess::maybe_warn_memmodel): New function. + (pass_waccess::check_atomic_memmodel): New function. + (pass_waccess::check_atomic_builtin): Handle memory model. + * input.c (expansion_point_location_if_in_system_header): Return + original location if expansion location is in a system header. + +2022-01-04 Uroš Bizjak <ubizjak@gmail.com> + + PR target/103861 + * config/i386/mmx.md (one_cmplv2qi3): New insn pattern. + (one_cmplv2qi3 splitters): New post-reload splitters. + (*andnotv2qi3): New insn pattern. + (andnotv2qi3 splitters): New post-reload splitters. + (<any_logic:code>v2qi3): New insn pattern. + (<any_logic:insn>v2qi3 splitters): New post-reload splitters. + +2022-01-04 Richard Biener <rguenther@suse.de> + + PR tree-optimization/103800 + * tree-vect-loop.c (vectorizable_phi): Remove assert and + expand comment. + +2022-01-04 Richard Biener <rguenther@suse.de> + + PR tree-optimization/103690 + * tree-pass.h (tail_merge_optimize): Adjust. + * tree-ssa-tail-merge.c (tail_merge_optimize): Pass in whether + to re-split critical edges, move CFG cleanup ... + * tree-ssa-pre.c (pass_pre::execute): ... here, before + simple_dce_from_worklist and delay freeing inserted_exprs from + ... + (fini_pre): .. here. + +2022-01-04 Roger Sayle <roger@nextmovesoftware.com> + + * config/nvptx/nvptx.h (STORE_FLAG_VALUE): Change to 1. + * config/nvptx/nvptx.md (movbi): Use P1 constraint for true. + (setcc_from_bi): Remove SImode specific pattern. + (setcc<mode>_from_bi): Provide more general HSDIM pattern. + (extendbi<mode>2, zeroextendbi<mode>2): Provide instructions + for sign- and zero-extending BImode predicates to integers. + (setcc_int<mode>): Remove previous (-1-based) instructions. + (cstorebi4): Remove BImode to SImode specific expander. + (cstore<mode>4): Fix indentation. Expand using setccsi_from_bi. + (cstore<mode>4): For both integer and floating point modes. + +2022-01-04 Olivier Hainque <hainque@adacore.com> + + * gcc.c (driver_handle_option): do_save --sysroot. + +2022-01-04 Richard Biener <rguenther@suse.de> + + PR tree-optimization/103864 + PR tree-optimization/103544 + * tree-vect-slp.c (vect_analyze_slp_instance): Exclude + reductions wrapped in conversions from SLP handling. + (vect_analyze_slp): Revert PR103544 change. + +2022-01-04 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/103860 + * shrink-wrap.c (try_shrink_wrapping): Don't call can_get_prologue + uselessly for blocks for which it has been called already. + +2022-01-04 Cui,Lili <lili.cui@intel.com> + + * common/config/i386/cpuinfo.h (get_intel_cpu): Add new model values + to Alderlake and Rocketlake. + +2022-01-04 Chung-Lin Tang <cltang@codesourcery.com> + + PR middle-end/103643 + * gimplify.c (gimplify_omp_affinity): Adjust gimplify_expr of entire + OMP_CLAUSE_DECL to use 'is_gimple_lvalue, fb_lvalue' + +2022-01-04 liuhongt <hongtao.liu@intel.com> + + PR target/103895 + * config/i386/sse.md (*bit_and_float_vector_all_ones): + Force_reg operand 1 to avoid ICE. + +2022-01-04 Jason Merrill <jason@redhat.com> + + * tree-pretty-print.c (do_niy): Add spc parameter. + (NIY): Pass it. + (print_call_name): Add spc local variable. + +2022-01-03 Uroš Bizjak <ubizjak@gmail.com> + + PR target/103894 + * config/i386/mmx.md (mov<V_32:mode>): Remove TARGET_SSE2 constraint. + (mov<V_32:mode>_internal): Ditto. + (*push<V_32:mode>_rex64): Ditto. + (movmisalign<V_32:mode>): Ditto. + (*push<V_32:mode>_rex64 splitter): Enable for + TARGET_64BIT && TARGET_SSE. + (*push<V_32:mode>2): Remove insn pattern. + +2022-01-03 Andrew Pinski <apinski@marvell.com> + + PR c/33193 + * doc/extend.texi: Extend the documentation about Complex + types for casting and also rewrite the __real__/__imag__ + expression portion to use tables. + Move __builtin_complex to the Complex type section. + +2022-01-03 Jakub Jelinek <jakub@redhat.com> + + PR target/98737 + * internal-fn.def (ATOMIC_ADD_FETCH_CMP_0, ATOMIC_SUB_FETCH_CMP_0, + ATOMIC_AND_FETCH_CMP_0, ATOMIC_OR_FETCH_CMP_0, ATOMIC_XOR_FETCH_CMP_0): + New internal fns. + * internal-fn.h (ATOMIC_OP_FETCH_CMP_0_EQ, ATOMIC_OP_FETCH_CMP_0_NE, + ATOMIC_OP_FETCH_CMP_0_LT, ATOMIC_OP_FETCH_CMP_0_LE, + ATOMIC_OP_FETCH_CMP_0_GT, ATOMIC_OP_FETCH_CMP_0_GE): New enumerators. + * internal-fn.c (expand_ATOMIC_ADD_FETCH_CMP_0, + expand_ATOMIC_SUB_FETCH_CMP_0, expand_ATOMIC_AND_FETCH_CMP_0, + expand_ATOMIC_OR_FETCH_CMP_0, expand_ATOMIC_XOR_FETCH_CMP_0): New + functions. + * optabs.def (atomic_add_fetch_cmp_0_optab, + atomic_sub_fetch_cmp_0_optab, atomic_and_fetch_cmp_0_optab, + atomic_or_fetch_cmp_0_optab, atomic_xor_fetch_cmp_0_optab): New + direct optabs. + * builtins.h (expand_ifn_atomic_op_fetch_cmp_0): Declare. + * builtins.c (expand_ifn_atomic_op_fetch_cmp_0): New function. + * tree-ssa-ccp.c: Include internal-fn.h. + (optimize_atomic_bit_test_and): Add . before internal fn call + in function comment. Change return type from void to bool and + return true only if successfully replaced. + (optimize_atomic_op_fetch_cmp_0): New function. + (pass_fold_builtins::execute): Use optimize_atomic_op_fetch_cmp_0 + for BUILT_IN_ATOMIC_{ADD,SUB,AND,OR,XOR}_FETCH_{1,2,4,8,16} and + BUILT_IN_SYNC_{ADD,SUB,AND,OR,XOR}_AND_FETCH_{1,2,4,8,16}, + for *XOR* ones only if optimize_atomic_bit_test_and failed. + * config/i386/sync.md (atomic_<plusminus_mnemonic>_fetch_cmp_0<mode>, + atomic_<logic>_fetch_cmp_0<mode>): New define_expand patterns. + (atomic_add_fetch_cmp_0<mode>_1, atomic_sub_fetch_cmp_0<mode>_1, + atomic_<logic>_fetch_cmp_0<mode>_1): New define_insn patterns. + * doc/md.texi (atomic_add_fetch_cmp_0<mode>, + atomic_sub_fetch_cmp_0<mode>, atomic_and_fetch_cmp_0<mode>, + atomic_or_fetch_cmp_0<mode>, atomic_xor_fetch_cmp_0<mode>): Document + new named patterns. + +2022-01-03 Richard Biener <rguenther@suse.de> + + PR middle-end/103851 + * tree-cfg.c (move_sese_region_to_fn): Always release SSA names. + +2022-01-03 Jakub Jelinek <jakub@redhat.com> + + PR c++/94716 + * symtab.c: Include fold-const.h. + (symtab_node::equal_address_to): If folding_initializer is true, + handle it like memory_accessed. Simplify. + +2022-01-03 Martin Liska <mliska@suse.cz> + + * doc/extend.texi: Use ; for function declarations. + +2022-01-03 Jakub Jelinek <jakub@redhat.com> + + PR c++/103600 + * symtab.c (symtab_node::equal_address_to): Return 0 if one of + VAR_DECLs has "non overlapping" attribute and rs1 != rs2. + +2022-01-03 Jakub Jelinek <jakub@redhat.com> + + * gcc.c (process_command): Update copyright notice dates. + * gcov-dump.c (print_version): Ditto. + * gcov.c (print_version): Ditto. + * gcov-tool.c (print_version): Ditto. + * gengtype.c (create_file): Ditto. + * doc/cpp.texi: Bump @copying's copyright year. + * doc/cppinternals.texi: Ditto. + * doc/gcc.texi: Ditto. + * doc/gccint.texi: Ditto. + * doc/gcov.texi: Ditto. + * doc/install.texi: Ditto. + * doc/invoke.texi: Ditto. + +2022-01-02 Uroš Bizjak <ubizjak@gmail.com> + + PR target/103861 + * config/i386/i386.h (VALID_SSE2_REG_MODE): Add V2QImode. + (VALID_INT_MODE_P): Ditto. + * config/i386/i386.c (ix86_secondary_reload): Handle + V2QImode reloads from SSE register to memory. + (vector_mode_supported_p): Always return true for V2QImode. + * config/i386/i386.md (*subqi_ext<mode>_2): New insn pattern. + (*negqi_ext<mode>_2): Ditto. + * config/i386/mmx.md (movv2qi): New expander. + (movmisalignv2qi): Ditto. + (*movv2qi_internal): New insn pattern. + (*pushv2qi2): Ditto. + (negv2qi2 and splitters): Ditto. + (<plusminus:insn>v2qi3 and splitters): Ditto. + +2022-01-02 John David Anglin <danglin@gcc.gnu.org> + + * config/pa/pa.md (atomic_storeq): Use optab_libfunc to access + sync_lock_test_and_set libfunc. Call convert_memory_address to + convert memory address to Pmode. + (atomic_storehi, atomic_storesi, atomic_storedi): Likewise. + + +Copyright (C) 2022 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright +notice and this notice are preserved. |