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| author | Cui,Lili <lili.cui@intel.com> | 2021-04-12 09:59:25 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2021-04-12 15:39:52 +0800 |
| commit | f2be08339b77d3495e210d6b5d9cea927f437720 (patch) | |
| tree | e85ec8e50827a315e712055ce13bef627b1646be /contrib/gcc-changelog/git_commit.py | |
| parent | a0ecde220da1edf7062ec429aa2c7a5b4103e92f (diff) | |
| download | gcc-f2be08339b77d3495e210d6b5d9cea927f437720.zip gcc-f2be08339b77d3495e210d6b5d9cea927f437720.tar.gz gcc-f2be08339b77d3495e210d6b5d9cea927f437720.tar.bz2 | |
Change march=alderlake ISA list and add m_ALDERLAKE to m_CORE_AVX2
Alder Lake Intel Hybrid Technology will not support Intel® AVX-512. ISA
features such as Intel® AVX, AVX-VNNI, Intel® AVX2, and UMONITOR/UMWAIT/TPAUSE
are supported.
gcc/ChangeLog
* config/i386/i386.h (PTA_ALDERLAKE): Change alderlake ISA list.
* config/i386/i386-options.c (m_CORE_AVX2): Add m_ALDERLAKE.
* common/config/i386/cpuinfo.h (get_intel_cpu): Add AlderLake model.
* doc/invoke.texi: Change alderlake ISA list.
Diffstat (limited to 'contrib/gcc-changelog/git_commit.py')
0 files changed, 0 insertions, 0 deletions