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| author | Wilco Dijkstra <wilco.dijkstra@arm.com> | 2024-07-02 17:37:04 +0100 |
|---|---|---|
| committer | Wilco Dijkstra <wilco.dijkstra@arm.com> | 2024-07-05 13:03:35 +0100 |
| commit | 100d353e545564931efaac90a089a4e8f3d42e6e (patch) | |
| tree | e7b73450450e04b4c784e4fe14428cc7c71911b1 /configure.in | |
| parent | 9f5620aed3976716e20e13c285dade56578d5bab (diff) | |
| download | gcc-releases/gcc-14.zip gcc-releases/gcc-14.tar.gz gcc-releases/gcc-14.tar.bz2 | |
Arm: Fix disassembly error in Thumb-1 relaxed load/store [PR115188]releases/gcc-14
A Thumb-1 memory operand allows single-register LDMIA/STMIA. This doesn't get
printed as LDR/STR with writeback in unified syntax, resulting in strange
assembler errors if writeback is selected. To work around this, use the 'Uw'
constraint that blocks writeback. Also use a new 'mem_and_no_t1_wback_op'
which is a general memory operand that disallows writeback in Thumb-1.
A few other patterns were using 'm' for Thumb-1 in a similar way, update these
to also use 'mem_and_no_t1_wback_op' and 'Uw'.
gcc:
PR target/115188
* config/arm/arm.md (unaligned_loadsi): Use 'Uw' constraint and
'mem_and_no_t1_wback_op'.
(unaligned_loadhiu): Likewise.
(unaligned_storesi): Likewise.
(unaligned_storehi): Likewise.
* config/arm/predicates.md (mem_and_no_t1_wback_op): Add new predicate.
* config/arm/sync.md (arm_atomic_load<mode>): Use 'Uw' constraint.
(arm_atomic_store<mode>): Likewise.
gcc/testsuite:
PR target/115188
* gcc.target/arm/pr115188.c: Add new test.
(cherry picked from commit d04c5537f5ae4a3acd3f5135347d7e2d8c218811)
Diffstat (limited to 'configure.in')
0 files changed, 0 insertions, 0 deletions