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author | Pan Li <pan2.li@intel.com> | 2023-08-01 14:42:31 +0800 |
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committer | Pan Li <pan2.li@intel.com> | 2023-08-01 15:51:38 +0800 |
commit | 85699f1d23aa71cbfeb13d72ec987e5217d410c2 (patch) | |
tree | 2baf10ed03cfe8fbfc2a7ebc80b2cb4b3a9d8a60 /ar-lib | |
parent | 01b0c36ba0c3bbe6ce0b0c77297e16d9531aac69 (diff) | |
download | gcc-85699f1d23aa71cbfeb13d72ec987e5217d410c2.zip gcc-85699f1d23aa71cbfeb13d72ec987e5217d410c2.tar.gz gcc-85699f1d23aa71cbfeb13d72ec987e5217d410c2.tar.bz2 |
RISC-V: Support RVV VFSUB and VFRSUB rounding mode intrinsic API
This patch would like to support the rounding mode API for both the
VFSUB and VFRSUB as below samples.
* __riscv_vfsub_vv_f32m1_rm
* __riscv_vfsub_vv_f32m1_rm_m
* __riscv_vfsub_vf_f32m1_rm
* __riscv_vfsub_vf_f32m1_rm_m
* __riscv_vfrsub_vf_f32m1_rm
* __riscv_vfrsub_vf_f32m1_rm_m
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class reverse_binop_frm): Add new template for reversed frm.
(vfsub_frm_obj): New obj.
(vfrsub_frm_obj): Likewise.
* config/riscv/riscv-vector-builtins-bases.h:
(vfsub_frm): New declaration.
(vfrsub_frm): Likewise.
* config/riscv/riscv-vector-builtins-functions.def
(vfsub_frm): New function define.
(vfrsub_frm): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-single-rsub.c: New test.
* gcc.target/riscv/rvv/base/float-point-single-sub.c: New test.
Diffstat (limited to 'ar-lib')
0 files changed, 0 insertions, 0 deletions