Add TIGERLAKE and COOPERLAKE to GCC.

2019-08-20  Lili Cui  <lili.cui@intel.com>

gcc/
	* common/config/i386/i386-common.c
	(processor_names): Add tigerlake and cooperlake.
	(processor_alias_table): Add tigerlake and cooperlake.
	* config.gcc: Add -march=tigerlake and cooperlake.
	* config/i386/driver-i386.c
	(host_detect_local_cpu): Detect tigerlake and cooperlake.
	Add "has_avx" to classify processor.
	* config/i386/i386-builtins.c (processor_model):
	Add M_INTEL_COREI7_TIGERLAKE and M_INTEL_COREI7_COOPERLAKE.
	(arch_names_table): Add tigerlake and cooperlake.
	(get_builtin_code_for_version) : Handle PROCESSOR_TIGERLAKE and
	PROCESSOR_COOPERLAKE.
	* config/i386/i386-c.c
	(ix86_target_macros_internal): Handle tigerlake and cooperlake.
	* config/i386/i386-options.c
	(m_TIGERLAKE)  : Define.
	(m_COOPERLAKE) : Ditto.
	(m_CORE_AVX512): Ditto.
	(processor_cost_table): Add cascadelake.
	(ix86_option_override_internal): Hadle PTA_MOVDIRI, PTA_MOVDIR64B.
	* config/i386/i386.h
	(ix86_size_cost) : Define TARGET_TIGERLAKE and TARGET_COOPERLAKE.
	(processor_type) : Add PROCESSOR_TIGERLAKE and PROCESSOR_COOPERLAKE.
	(PTA_MOVDIRI): Ditto.
	(PTA_MOVDIR64B): Ditto.
	(PTA_COOPERLAKE) : Ditto.
	(PTA_TIGERLAKE)  : Ditto.
	(processor_type) : Add PROCESSOR_TIGERLAKE and PROCESSOR_COOPERLAKE.
	* doc/extend.texi: Add tigerlake and cooperlake.
	* doc/invoke.texi: Add tigerlake and cooperlake.

gcc/testsuite/
	* gcc.target/i386/funcspec-56.inc: Handle new march.
	* g++.target/i386/mv16.C: Handle new march

libgcc/
	* config/i386/cpuinfo.h: Add INTEL_COREI7_TIGERLAKE and
	INTEL_COREI7_COOPERLAKE.

From-SVN: r274693

15 files changed, 171 insertions, 31 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 662e650..5879431 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,36 @@
+2019-08-20  Lili Cui  <lili.cui@intel.com>
+
+	* common/config/i386/i386-common.c
+	(processor_names): Add tigerlake and cooperlake.
+	(processor_alias_table): Add tigerlake and cooperlake.
+	* config.gcc: Add -march=tigerlake and cooperlake.
+	* config/i386/driver-i386.c
+	(host_detect_local_cpu): Detect tigerlake and cooperlake.
+	Add "has_avx" to classify processor.
+	* config/i386/i386-builtins.c (processor_model) :
+	Add M_INTEL_COREI7_TIGERLAKE and M_INTEL_COREI7_COOPERLAKE.
+	(arch_names_table): Add tigerlake and cooperlake.
+	(get_builtin_code_for_version) : Handle PROCESSOR_TIGERLAKE
+	and PROCESSOR_COOPERLAKE.
+	* config/i386/i386-c.c
+	(ix86_target_macros_internal): Handle tigerlake and cooperlake.
+	* config/i386/i386-options.c
+	(m_TIGERLAKE)  : Define.
+	(m_COOPERLAKE) : Ditto.
+	(m_CORE_AVX512): Ditto.
+	(processor_cost_table): Add cascadelake.
+	(ix86_option_override_internal): Hadle PTA_MOVDIRI, PTA_MOVDIR64B.
+	* config/i386/i386.h
+	(ix86_size_cost) : Define TARGET_TIGERLAKE and TARGET_COOPERLAKE.
+	(processor_type) : Add PROCESSOR_TIGERLAKE and PROCESSOR_COOPERLAKE.
+	(PTA_MOVDIRI): Ditto.
+	(PTA_MOVDIR64B): Ditto.
+	(PTA_COOPERLAKE) : Ditto.
+	(PTA_TIGERLAKE)  : Ditto.
+	(processor_type) : Add PROCESSOR_TIGERLAKE and PROCESSOR_COOPERLAKE.
+	* doc/extend.texi: Add tigerlake and cooperlake.
+	* doc/invoke.texi: Add tigerlake and cooperlake.
+
 2019-08-20  Gerald Pfeifer  <gerald@pfeifer.com>
 
 	* doc/install.texi (Specific, alpha): Remove note to use
diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
index 1f77f7d..5cb1dcc 100644
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -1566,6 +1566,8 @@ const char *const processor_names[] =
   "icelake-client",
   "icelake-server",
   "cascadelake",
+  "tigerlake",
+  "cooperlake",
   "intel",
   "geode",
   "k6",
@@ -1648,6 +1650,8 @@ const pta processor_alias_table[] =
     PTA_ICELAKE_SERVER},
   {"cascadelake", PROCESSOR_CASCADELAKE, CPU_HASWELL,
     PTA_CASCADELAKE},
+  {"tigerlake", PROCESSOR_TIGERLAKE, CPU_HASWELL, PTA_TIGERLAKE},
+  {"cooperlake", PROCESSOR_COOPERLAKE, CPU_HASWELL, PTA_COOPERLAKE},
   {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
   {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
   {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 40cbc52..11a8ac7 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -664,7 +664,8 @@ bdver3 bdver4 znver1 znver2 btver1 btver2 k8 k8-sse3 opteron \
 opteron-sse3 nocona core2 corei7 corei7-avx core-avx-i core-avx2 atom \
 slm nehalem westmere sandybridge ivybridge haswell broadwell bonnell \
 silvermont knl knm skylake-avx512 cannonlake icelake-client icelake-server \
-skylake goldmont goldmont-plus tremont cascadelake x86-64 native"
+skylake goldmont goldmont-plus tremont cascadelake tigerlake cooperlake x86-64 \
+native"
 
 # Additional x86 processors supported by --with-cpu=.  Each processor
 # MUST be separated by exactly one space.
diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c
index a9d8981..8e8b4d2 100644
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -863,36 +863,45 @@ const char *host_detect_local_cpu (int argc, const char **argv)
 	  if (arch)
 	    {
 	      /* This is unknown family 0x6 CPU.  */
-	      /* Assume Ice Lake Server.  */
-	      if (has_wbnoinvd)
-		cpu = "icelake-server";
-	      /* Assume Ice Lake.  */
-	      else if (has_gfni)
-		cpu = "icelake-client";
-	      /* Assume Cannon Lake.  */
-	      else if (has_avx512vbmi)
-		cpu = "cannonlake";
-	      /* Assume Knights Mill.  */
-	      else if (has_avx5124vnniw)
-		cpu = "knm";
-	      /* Assume Knights Landing.  */
-	      else if (has_avx512er)
-		cpu = "knl";
-	      /* Assume Skylake with AVX-512.  */
-	      else if (has_avx512f)
-		cpu = "skylake-avx512";
-	      /* Assume Skylake.  */
-	      else if (has_clflushopt)
-		cpu = "skylake";
-	      /* Assume Broadwell.  */
-	      else if (has_adx)
-		cpu = "broadwell";
-	      else if (has_avx2)
+	      if (has_avx)
+	      {
+		/* Assume Tiger Lake */
+		if (has_avx512vp2intersect)
+		  cpu = "tigerlake";
+		/* Assume Cooper Lake */
+		else if (has_avx512bf16)
+		  cpu = "cooperlake";
+		/* Assume Ice Lake Server.  */
+		else if (has_wbnoinvd)
+		  cpu = "icelake-server";
+		/* Assume Ice Lake.  */
+		else if (has_avx512bitalg)
+		  cpu = "icelake-client";
+		/* Assume Cannon Lake.  */
+		else if (has_avx512vbmi)
+		  cpu = "cannonlake";
+		/* Assume Knights Mill.  */
+		else if (has_avx5124vnniw)
+		  cpu = "knm";
+		/* Assume Knights Landing.  */
+		else if (has_avx512er)
+		  cpu = "knl";
+		/* Assume Skylake with AVX-512.  */
+		else if (has_avx512f)
+		  cpu = "skylake-avx512";
+		/* Assume Skylake.  */
+		else if (has_clflushopt)
+		  cpu = "skylake";
+		/* Assume Broadwell.  */
+		else if (has_adx)
+		  cpu = "broadwell";
+		else if (has_avx2)
 		/* Assume Haswell.  */
-		cpu = "haswell";
-	      else if (has_avx)
+		  cpu = "haswell";
+		else
 		/* Assume Sandy Bridge.  */
-		cpu = "sandybridge";
+		  cpu = "sandybridge";	      
+	      }
 	      else if (has_sse4_2)
 		{
 		  if (has_gfni)
diff --git a/gcc/config/i386/i386-builtins.c b/gcc/config/i386/i386-builtins.c
index 9736a75..5b388ec 100644
--- a/gcc/config/i386/i386-builtins.c
+++ b/gcc/config/i386/i386-builtins.c
@@ -1972,7 +1972,9 @@ enum processor_model
   M_INTEL_COREI7_ICELAKE_CLIENT,
   M_INTEL_COREI7_ICELAKE_SERVER,
   M_AMDFAM17H_ZNVER2,
-  M_INTEL_COREI7_CASCADELAKE
+  M_INTEL_COREI7_CASCADELAKE,
+  M_INTEL_COREI7_TIGERLAKE,
+  M_INTEL_COREI7_COOPERLAKE
 };
 
 struct _arch_names_table
@@ -2001,6 +2003,8 @@ static const _arch_names_table arch_names_table[] =
   {"icelake-client", M_INTEL_COREI7_ICELAKE_CLIENT},
   {"icelake-server", M_INTEL_COREI7_ICELAKE_SERVER},
   {"cascadelake", M_INTEL_COREI7_CASCADELAKE},
+  {"tigerlake", M_INTEL_COREI7_TIGERLAKE},
+  {"cooperlake", M_INTEL_COREI7_COOPERLAKE},
   {"bonnell", M_INTEL_BONNELL},
   {"silvermont", M_INTEL_SILVERMONT},
   {"goldmont", M_INTEL_GOLDMONT},
@@ -2194,6 +2198,14 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
 	      arg_str = "cascadelake";
 	      priority = P_PROC_AVX512F;
 	      break;
+	    case PROCESSOR_TIGERLAKE:
+	      arg_str = "tigerlake";
+	      priority = P_PROC_AVX512F;
+	      break;
+	    case PROCESSOR_COOPERLAKE:
+	      arg_str = "cooperlake";
+	      priority = P_PROC_AVX512F;
+	      break;
 	    case PROCESSOR_BONNELL:
 	      arg_str = "bonnell";
 	      priority = P_PROC_SSSE3;
diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c
index ec5f15b..3f054ca 100644
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@@ -222,6 +222,13 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
       def_or_undef (parse_in, "__cascadelake");
       def_or_undef (parse_in, "__cascadelake__");
       break;
+    case PROCESSOR_TIGERLAKE:
+      def_or_undef (parse_in, "__tigerlake");
+      def_or_undef (parse_in, "__tigerlake__");
+      break;
+    case PROCESSOR_COOPERLAKE:
+      def_or_undef (parse_in, "__cooperlake");
+      def_or_undef (parse_in, "__cooperlake__");
     /* use PROCESSOR_max to not set/unset the arch macro.  */
     case PROCESSOR_max:
       break;
@@ -370,6 +377,12 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
     case PROCESSOR_CASCADELAKE:
       def_or_undef (parse_in, "__tune_cascadelake__");
       break;
+    case PROCESSOR_TIGERLAKE:
+      def_or_undef (parse_in, "__tune_tigerlake__");
+      break;
+    case PROCESSOR_COOPERLAKE:
+      def_or_undef (parse_in, "__tune_cooperlake__");
+      break;
     case PROCESSOR_INTEL:
     case PROCESSOR_GENERIC:
       break;
diff --git a/gcc/config/i386/i386-options.c b/gcc/config/i386/i386-options.c
index a1741c0..703e44e 100644
--- a/gcc/config/i386/i386-options.c
+++ b/gcc/config/i386/i386-options.c
@@ -121,8 +121,11 @@ along with GCC; see the file COPYING3.  If not see
 #define m_ICELAKE_CLIENT (HOST_WIDE_INT_1U<<PROCESSOR_ICELAKE_CLIENT)
 #define m_ICELAKE_SERVER (HOST_WIDE_INT_1U<<PROCESSOR_ICELAKE_SERVER)
 #define m_CASCADELAKE (HOST_WIDE_INT_1U<<PROCESSOR_CASCADELAKE)
+#define m_TIGERLAKE (HOST_WIDE_INT_1U<<PROCESSOR_TIGERLAKE)
+#define m_COOPERLAKE (HOST_WIDE_INT_1U<<PROCESSOR_COOPERLAKE)
 #define m_CORE_AVX512 (m_SKYLAKE_AVX512 | m_CANNONLAKE \
-		       | m_ICELAKE_CLIENT | m_ICELAKE_SERVER | m_CASCADELAKE)
+		       | m_ICELAKE_CLIENT | m_ICELAKE_SERVER | m_CASCADELAKE \
+		       | m_TIGERLAKE | m_COOPERLAKE)
 #define m_CORE_AVX2 (m_HASWELL | m_SKYLAKE | m_CORE_AVX512)
 #define m_CORE_ALL (m_CORE2 | m_NEHALEM  | m_SANDYBRIDGE | m_CORE_AVX2)
 #define m_GOLDMONT (HOST_WIDE_INT_1U<<PROCESSOR_GOLDMONT)
@@ -627,6 +630,8 @@ static const struct processor_costs *processor_cost_table[] =
   &skylake_cost,
   &skylake_cost,
   &skylake_cost,
+  &skylake_cost,
+  &skylake_cost,
   &intel_cost,
   &geode_cost,
   &k6_cost,
@@ -2049,6 +2054,12 @@ ix86_option_override_internal (bool main_args_p,
 	    && !(opts->x_ix86_isa_flags2_explicit
 		 & OPTION_MASK_ISA_AVX512BF16))
 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX512BF16;
+        if (((processor_alias_table[i].flags & PTA_MOVDIRI) != 0)
+            && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_MOVDIRI))
+          opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVDIRI;
+        if (((processor_alias_table[i].flags & PTA_MOVDIR64B) != 0)
+            && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_MOVDIR64B))
+          opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVDIR64B;
 	if (((processor_alias_table[i].flags & PTA_SGX) != 0)
 	    && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_SGX))
 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX;
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index e0a77e1..167b73e 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -440,6 +440,8 @@ extern const struct processor_costs ix86_size_cost;
 #define TARGET_ICELAKE_CLIENT (ix86_tune == PROCESSOR_ICELAKE_CLIENT)
 #define TARGET_ICELAKE_SERVER (ix86_tune == PROCESSOR_ICELAKE_SERVER)
 #define TARGET_CASCADELAKE (ix86_tune == PROCESSOR_CASCADELAKE)
+#define TARGET_TIGERLAKE (ix86_tune == PROCESSOR_TIGERLAKE)
+#define TARGET_COOPERLAKE (ix86_tune == PROCESSOR_COOPERLAKE)
 #define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL)
 #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
@@ -2303,6 +2305,8 @@ enum processor_type
   PROCESSOR_ICELAKE_CLIENT,
   PROCESSOR_ICELAKE_SERVER,
   PROCESSOR_CASCADELAKE,
+  PROCESSOR_TIGERLAKE,
+  PROCESSOR_COOPERLAKE,
   PROCESSOR_INTEL,
   PROCESSOR_GEODE,
   PROCESSOR_K6,
@@ -2402,6 +2406,8 @@ const wide_int_bitmask PTA_AVX512VP2INTERSECT (0, HOST_WIDE_INT_1U << 9);
 const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 9);
 const wide_int_bitmask PTA_PTWRITE (0, HOST_WIDE_INT_1U << 10);
 const wide_int_bitmask PTA_AVX512BF16 (0, HOST_WIDE_INT_1U << 11);
+const wide_int_bitmask PTA_MOVDIRI(0, HOST_WIDE_INT_1U << 13);
+const wide_int_bitmask PTA_MOVDIR64B(0, HOST_WIDE_INT_1U << 14);
 
 const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
   | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
@@ -2422,6 +2428,7 @@ const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
   | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
   | PTA_CLWB;
 const wide_int_bitmask PTA_CASCADELAKE = PTA_SKYLAKE_AVX512 | PTA_AVX512VNNI;
+const wide_int_bitmask PTA_COOPERLAKE = PTA_CASCADELAKE | PTA_AVX512BF16;
 const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F
   | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
   | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA;
@@ -2430,6 +2437,8 @@ const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI
   | PTA_RDPID | PTA_CLWB;
 const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG
   | PTA_WBNOINVD;
+const wide_int_bitmask PTA_TIGERLAKE = PTA_ICELAKE_CLIENT | PTA_MOVDIRI
+  | PTA_MOVDIR64B | PTA_AVX512VP2INTERSECT;
 const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
   | PTA_AVX512F | PTA_AVX512CD;
 const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 2ba9b74..235be99 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -21489,6 +21489,12 @@ Intel Core i7 Ice Lake Server CPU.
 @item cascadelake
 Intel Core i7 Cascadelake CPU.
 
+@item tigerlake
+Intel Core i7 Tigerlake CPU.
+
+@item cooperlake
+Intel Core i7 Cooperlake CPU.
+
 @item bonnell
 Intel Atom Bonnell CPU.
 
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index ca11179..08e6b52 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -27559,6 +27559,22 @@ SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
 BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
 AVX512VL, AVX512BW, AVX512DQ, AVX512CD and AVX512VNNI instruction set support.
 
+@item cooperlake
+Intel cooperlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
+BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB,
+AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VNNI and AVX512BF16 instruction
+set support.
+
+@item tigerlake
+Intel Tigerlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
+BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
+AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP,
+RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ,
+VAES, PCONFIG, WBNOINVD, MOVDIRI, MOVDIR64B and  AVX512VP2INTERSECT instruction
+set support.
+
 @item k6
 AMD K6 CPU with MMX instruction set support.
 
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 1aeccfd..7f24b8d 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2019-08-20  Lili Cui  <lili.cui@intel.com>
+
+	* gcc.target/i386/funcspec-56.inc: Handle new march.
+	* g++.target/i386/mv16.C: Handle new march
+
 2019-08-20  Bernd Edlinger  <bernd.edlinger@hotmail.de>
 
 	PR middle-end/89544
diff --git a/gcc/testsuite/g++.target/i386/mv16.C b/gcc/testsuite/g++.target/i386/mv16.C
index 81e1511..422b9cd 100644
--- a/gcc/testsuite/g++.target/i386/mv16.C
+++ b/gcc/testsuite/g++.target/i386/mv16.C
@@ -72,6 +72,14 @@ int __attribute__ ((target("arch=cascadelake"))) foo () {
   return 19;
 }
 
+int __attribute__ ((target("arch=tigerlake"))) foo () {
+  return 20;
+}
+
+int __attribute__ ((target("arch=cooperlake"))) foo () {
+  return 21;
+}
+
 int main ()
 {
   int val = foo ();
@@ -100,6 +108,10 @@ int main ()
     assert (val == 18);
   else if (__builtin_cpu_is ("cascadelake"))
     assert (val == 19);
+  else if (__builtin_cpu_is ("tigerlake"))
+    assert (val == 20);
+  else if (__builtin_cpu_is ("cooperlake"))
+    assert (val == 21);
   else
     assert (val == 0);
 
diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
index 0eb83a7..200d272 100644
--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
@@ -151,6 +151,8 @@ extern void test_arch_cannonlake (void)		__attribute__((__target__("arch=cannonl
 extern void test_arch_icelake_client (void)	__attribute__((__target__("arch=icelake-client")));
 extern void test_arch_icelake_server (void)	__attribute__((__target__("arch=icelake-server")));
 extern void test_arch_cascadelake (void)	__attribute__((__target__("arch=cascadelake")));
+extern void test_arch_tigerlake (void)          __attribute__((__target__("arch=tigerlake")));
+extern void test_arch_cooperlake (void)         __attribute__((__target__("arch=cooperlake")));
 extern void test_arch_k8 (void)			__attribute__((__target__("arch=k8")));
 extern void test_arch_k8_sse3 (void)		__attribute__((__target__("arch=k8-sse3")));
 extern void test_arch_opteron (void)		__attribute__((__target__("arch=opteron")));
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 33b6fa8..c793ea4 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,8 @@
+2019-08-20  Lili Cui  <lilicui@intel.com>
+
+	* config/i386/cpuinfo.h: Add INTEL_COREI7_TIGERLAKE and
+	INTEL_COREI7_COOPERLAKE.
+
 2019-07-31  Matt Thomas  <matt@3am-software.com>
 	    Nick Hudson <nick@nthcliff.demon.co.uk>
 	    Matthew Green <mrg@eterna.com.au>
diff --git a/libgcc/config/i386/cpuinfo.h b/libgcc/config/i386/cpuinfo.h
index 68ca466..67209d5 100644
--- a/libgcc/config/i386/cpuinfo.h
+++ b/libgcc/config/i386/cpuinfo.h
@@ -77,6 +77,8 @@ enum processor_subtypes
   INTEL_COREI7_ICELAKE_SERVER,
   AMDFAM17H_ZNVER2,
   INTEL_COREI7_CASCADELAKE,
+  INTEL_COREI7_TIGERLAKE,
+  INTEL_COREI7_COOPERLAKE,
   CPU_SUBTYPE_MAX
 };