testsuite: powerpc fold-vec and sse updates.

Recent code generation changes have affected the count of some instructions.
This patch updates the instruction count for fold-vec-extract on P7 and P8.

Also, some of SSE emulation intrinsics only work on LE systems.

gcc/testsuite/ChangeLog:

	* gcc.target/powerpc/fold-vec-extract-char.p7.c: Adjust addi count.
	* gcc.target/powerpc/fold-vec-extract-double.p7.c: Same.
	* gcc.target/powerpc/fold-vec-extract-float.p7.c: Same.
	* gcc.target/powerpc/fold-vec-extract-float.p8.c: Same.
	* gcc.target/powerpc/fold-vec-extract-int.p7.c: Same.
	* gcc.target/powerpc/fold-vec-extract-int.p8.c: Same.
	* gcc.target/powerpc/fold-vec-extract-short.p7.c: Same.
	* gcc.target/powerpc/fold-vec-extract-short.p8.c: Same.
	* gcc.target/powerpc/sse-andnps-1.c: Restrict to LE.
	* gcc.target/powerpc/sse-movhps-1.c: Restrict to LE.
	* gcc.target/powerpc/sse-movlps-1.c: Restrict to LE.
	* gcc.target/powerpc/sse2-andnpd-1.c: Restrict to LE.

12 files changed, 16 insertions, 12 deletions

diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c
index 42599c2..29a8aa8 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c
@@ -11,7 +11,7 @@
 /* one extsb (extend sign-bit) instruction generated for each test against
    unsigned types */
 
-/* { dg-final { scan-assembler-times {\maddi\M} 6 } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 9 } } */
 /* { dg-final { scan-assembler-times {\mli\M} 6 } } */
 /* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */
 /* -m32 target uses rlwinm in place of rldicl. */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
index cbf6cff..3cae644 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
@@ -13,7 +13,8 @@
 /* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */
 /* { dg-final { scan-assembler-times {\mli\M} 1 } } */
 /* -m32 target has an 'add' in place of one of the 'addi'. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } } */
 /* -m32 target has a rlwinm in place of a rldic .  */
 /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
 /* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
index c9abb6c..59a4979 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
@@ -12,7 +12,8 @@
 /* { dg-final { scan-assembler-times {\mxscvspdp\M} 1 } } */
 /* { dg-final { scan-assembler-times {\mli\M} 1 } } */
 /* -m32 as an add in place of an addi. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */
 /* -m32 uses rlwinm in place of rldic */
 /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
index 68eeeed..4b1d75e 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
@@ -26,7 +26,7 @@
 /* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 1 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 2 { target ilp32 } } } */
 
 
 #include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
index 418762e..3729a16 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
@@ -10,7 +10,8 @@
 // P7 variables:  li, addi, stxvw4x, lwa/lwz
 
 /* { dg-final { scan-assembler-times {\mli\M} 6 } } */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 } } */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */
 /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 3 } } */
 /* { dg-final { scan-assembler-times {\mlwz\M|\mlwa\M|\mlwzx\M|\mlwax\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c
index d1e3b62..75eaf25 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c
@@ -30,7 +30,7 @@
 /* { dg-final { scan-assembler-times {\mstxvw4x\M} 6 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times {\madd\M} 3 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times {\mlwz\M} 6 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 6 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 9 { target ilp32 } } } */
 
 
 
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c
index 46e943f..a495d9f 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c
@@ -10,7 +10,8 @@
 // P7 (be) constants:            li, addi,              stxvw4x, lha/lhz
 
 /* { dg-final { scan-assembler-times {\mli\M} 6 } } */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 } } */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 3 } } */
 /* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M} 6 } } */
 /* { dg-final { scan-assembler-times "lhz|lha|lhzx|lhax" 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c
index 00685ac..0ddecb4 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c
@@ -32,7 +32,7 @@
 /* add and rlwinm instructions only on the variable tests. */
 /* { dg-final { scan-assembler-times {\madd\M} 3 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times "rlwinm" 3 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 6 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 9 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times {\mlha\M|\mlhz\M} 6 { target ilp32 } } } */
 
 
diff --git a/gcc/testsuite/gcc.target/powerpc/sse-andnps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-andnps-1.c
index 7b0dc01..3b45ca4 100644
--- a/gcc/testsuite/gcc.target/powerpc/sse-andnps-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/sse-andnps-1.c
@@ -1,4 +1,4 @@
-/* { dg-do run } */
+/* { dg-do run { target le } } */
 /* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */
 /* { dg-require-effective-target p8vector_hw } */
 
diff --git a/gcc/testsuite/gcc.target/powerpc/sse-movhps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-movhps-1.c
index f94c5aa..a0666e5 100644
--- a/gcc/testsuite/gcc.target/powerpc/sse-movhps-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/sse-movhps-1.c
@@ -1,4 +1,4 @@
-/* { dg-do run } */
+/* { dg-do run { target le } } */
 /* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */
 /* { dg-require-effective-target p8vector_hw } */
 
diff --git a/gcc/testsuite/gcc.target/powerpc/sse-movlps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-movlps-1.c
index 3d1b79a..281d49c 100644
--- a/gcc/testsuite/gcc.target/powerpc/sse-movlps-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/sse-movlps-1.c
@@ -1,4 +1,4 @@
-/* { dg-do run } */
+/* { dg-do run { target le } } */
 /* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */
 /* { dg-require-effective-target p8vector_hw } */
 
diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-andnpd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-andnpd-1.c
index 212bc00..1a0e6cb 100644
--- a/gcc/testsuite/gcc.target/powerpc/sse2-andnpd-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/sse2-andnpd-1.c
@@ -1,4 +1,4 @@
-/* { dg-do run } */
+/* { dg-do run { target le } } */
 /* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */
 /* { dg-require-effective-target p8vector_hw } */