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| author | Roger Sayle <roger@nextmovesoftware.com> | 2022-03-16 23:15:20 +0000 |
|---|---|---|
| committer | Roger Sayle <roger@nextmovesoftware.com> | 2022-03-16 23:15:20 +0000 |
| commit | 732e4a75fe792182f171bba348a665e8b8d21176 (patch) | |
| tree | ce7846c4ab67015e05b2df0b0261d47291d9582f | |
| parent | 2f26b26721d5f8a6ac874fc23e18e1b03d207990 (diff) | |
| download | gcc-732e4a75fe792182f171bba348a665e8b8d21176.zip gcc-732e4a75fe792182f171bba348a665e8b8d21176.tar.gz gcc-732e4a75fe792182f171bba348a665e8b8d21176.tar.bz2 | |
PR target/94680: Clear upper bits of V2DF using movq (like V2DI).
This simple i386 patch unblocks a more significant change. The testcase
gcc.target/i386/sse2-pr94680.c isn't quite testing what's intended, and
alas the fix for PR target/94680 doesn't (yet) handle V2DF mode.
For the first test from sse2-pr94680.c, below
v2df foo_v2df (v2df x) {
return __builtin_shuffle (x, (v2df) { 0, 0 }, (v2di) { 0, 2 });
}
GCC on x86_64-pc-linux-gnu with -O2 currently generates:
movhpd .LC0(%rip), %xmm0
ret
.LC0:
.long 0
.long 0
which passes the test as it contains a mov insn and no xor.
Alas reading a zero from the constant pool isn't quite the
desired implementation. With this patch we now generate:
movq %xmm0, %xmm0
ret
The same code as we generate for V2DI, and add a stricter
test case. This implementation generalizes the sse2_movq128
to V2DI and V2DF modes using a VI8F_128 mode iterator and
renames it *sse2_movq128_<mode>. A new define_expand is
introduced for sse2_movq128 so that the exisiting builtin
interface (CODE_FOR_sse2_movq128) remains the same.
2022-03-16 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
PR target/94680
* config/i386/sse.md (sse2_movq128): New define_expand to
preserve previous named instruction.
(*sse2_movq128_<mode>): Renamed from sse2_movq128, and
generalized to VI8F_128 (both V2DI and V2DF).
gcc/testsuite/ChangeLog
PR target/94680
* gcc.target/i386/sse2-pr94680-2.c: New stricter V2DF test case.
| -rw-r--r-- | gcc/config/i386/sse.md | 15 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/sse2-pr94680-2.c | 13 |
2 files changed, 25 insertions, 3 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index e9292e6..4c9c069 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1586,13 +1586,22 @@ (set_attr "memory" "store") (set_attr "mode" "<sseinsnmode>")]) -(define_insn "sse2_movq128" - [(set (match_operand:V2DI 0 "register_operand" "=v") +(define_expand "sse2_movq128" + [(set (match_operand:V2DI 0 "register_operand") (vec_concat:V2DI (vec_select:DI - (match_operand:V2DI 1 "nonimmediate_operand" "vm") + (match_operand:V2DI 1 "nonimmediate_operand") (parallel [(const_int 0)])) (const_int 0)))] + "TARGET_SSE2") + +(define_insn "*sse2_movq128_<mode>" + [(set (match_operand:VI8F_128 0 "register_operand" "=v") + (vec_concat:VI8F_128 + (vec_select:<ssescalarmode> + (match_operand:VI8F_128 1 "nonimmediate_operand" "vm") + (parallel [(const_int 0)])) + (match_operand:<ssescalarmode> 2 Â"const0_operand" "C")))] "TARGET_SSE2" "%vmovq\t{%1, %0|%0, %q1}" [(set_attr "type" "ssemov") diff --git a/gcc/testsuite/gcc.target/i386/sse2-pr94680-2.c b/gcc/testsuite/gcc.target/i386/sse2-pr94680-2.c new file mode 100644 index 0000000..abd260a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-pr94680-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ +typedef double v2df __attribute__ ((vector_size (16))); +typedef long long v2di __attribute__((vector_size(16))); + +v2df foo_v2df (v2df x) +{ + return __builtin_shuffle (x, (v2df) { 0, 0 }, (v2di) { 0, 2 }); +} + +/* { dg-final { scan-assembler "movq" } } */ +/* { dg-final { scan-assembler-not "pxor" } } */ + |