RISC-V: Use default cost model for insn scheduling

Use default cost model scheduling on these test cases. All these tests
introduce scan dump failures with -mtune generic-ooo. Since the vector
cost models are the same across all three tunes, some of the tests
in PR113249 will be fixed with this patch series.

	PR target/113249

gcc/testsuite/ChangeLog:

	* g++.target/riscv/rvv/base/bug-1.C: Use default scheduling
	* gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-102.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-108.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-114.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-119.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-12.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-16.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-17.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-19.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-21.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-23.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-25.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-27.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-29.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-31.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-33.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-35.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-4.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-40.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-44.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-50.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-56.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-62.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-68.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-74.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-79.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-8.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-84.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-90.c: Ditto
	* gcc.target/riscv/rvv/base/binop_vx_constraint-96.c: Ditto
	* gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c: Ditto
	* gcc.target/riscv/rvv/base/pr108185-1.c: Ditto
	* gcc.target/riscv/rvv/base/pr108185-2.c: Ditto
	* gcc.target/riscv/rvv/base/pr108185-3.c: Ditto
	* gcc.target/riscv/rvv/base/pr108185-4.c: Ditto
	* gcc.target/riscv/rvv/base/pr108185-5.c: Ditto
	* gcc.target/riscv/rvv/base/pr108185-6.c: Ditto
	* gcc.target/riscv/rvv/base/pr108185-7.c: Ditto
	* gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: Ditto
	* gcc.target/riscv/rvv/vsetvl/pr111037-3.c: Ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: Ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: Ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c: Ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c: Ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: Ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: Ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: Ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: Ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: Ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: Ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: Ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: Ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: Ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: Ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: Ditto
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: Ditto
	* gfortran.dg/vect/vect-8.f90: Ditto

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>

58 files changed, 116 insertions, 0 deletions

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C
index c1070f9..6f62a64 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 template < class T > 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c
index 7be22d6..17a6b6f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "reduc_call-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c
index 4b24b97..8386b42 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, int32_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c
index 99acc51..e2ed4b7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, int32_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c
index d595c44..61340be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, int32_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c
index 0b51175..0f1485e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, uint64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c
index 634c12a..173ac62 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c
index 651d610..1edba89 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c
index d19a9fd..75340c3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c
index 16f4315..7e4aedc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c
index 347c846..755e92a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c
index bc41444..2c82dc0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c
index ce3f3af..e2ac6a3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c
index 4946f84..436a0e8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c
index 5f2eede..72b3216 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c
index 5f2eede..72b3216 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c
index 88fcba6..6908c78 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c
index 88fcba6..6908c78 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c
index 87a1645..ee1db1c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c
index c0321ce..fb969eb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c
index ab0f13b..542f43e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c
index 3893e17..31109a8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, int32_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c
index b0ea553..924f450 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, int64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c
index 350697d..659d8d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, int64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c
index 0f138c5..6387460 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, int64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c
index f4cbf09..a214d70 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, int64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c
index d606078..efa659b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, int64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c
index 9bf9ff5..6a26248 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c
index bca55b2..429fe12 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, uint64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c
index 586e264..0cd0af7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, int32_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c
index d1bbb78..bb1690e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 #include "riscv_vector.h"
 
 void f (void * in, void *out, int32_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c
index 7e73878..37ef0f0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
index c3d0b10..4c6e88e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
index bd13ba9..0844e3e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
index 99928f7..49a5744 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
index 321cd5c..cef0a11 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gc_zve64d -mabi=lp64 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
index 575a784..3f0d677 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
index 95a11d3..4ed6588 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c
index 8f6f0b1..95b7ff9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c
index 250e017..9e0b41c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
index 110e55b..5e1859c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
index 4583504..f4f0e52 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
index f16f4b9..7e01b81 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c
index 43b443b..5615cb1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c
index 6785558..c906b15 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
index 960c9bf..006df7e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
index 5f22e8d..cc6d822 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c
index e5f35c0..9704e444 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
index 0532c7d..476735d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
index b664c4b..c7b7db3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
index 04c4b88..80ff75f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
index 1404c9d..127dc7f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
index 1404c9d..127dc7f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
index 609c68d..e19e869 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
index 043f177..90eca5b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
index 0bedde8..17b217b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
index 0bedde8..17b217b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gfortran.dg/vect/vect-8.f90 b/gcc/testsuite/gfortran.dg/vect/vect-8.f90
index 938dfc2..f77ec9f 100644
--- a/gcc/testsuite/gfortran.dg/vect/vect-8.f90
+++ b/gcc/testsuite/gfortran.dg/vect/vect-8.f90
@@ -1,6 +1,8 @@
 ! { dg-do compile }
 ! { dg-require-effective-target vect_double }
 ! { dg-additional-options "-fno-tree-loop-distribute-patterns -finline-matmul-limit=0" }
+! PR113249
+! { dg-options "-fno-schedule-insns -fno-schedule-insns2" { target { riscv*-*-* } } }
 
 module lfk_prec
  integer, parameter :: dp=kind(1.d0)