diff options
| author | Richard Sandiford <richard.sandiford@arm.com> | 2020-04-15 11:38:24 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2020-04-16 13:06:10 +0100 |
| commit | 3c3f12e2a7625c9a2f5d74a47dbacb2fd1ae5643 (patch) | |
| tree | 867f3f5046c7a5cd28036be268a5711aa2203a8f | |
| parent | 1acde74cf611f560172c74324610c29ca81edf94 (diff) | |
| download | gcc-3c3f12e2a7625c9a2f5d74a47dbacb2fd1ae5643.zip gcc-3c3f12e2a7625c9a2f5d74a47dbacb2fd1ae5643.tar.gz gcc-3c3f12e2a7625c9a2f5d74a47dbacb2fd1ae5643.tar.bz2 | |
early-remat: Handle sets of multiple candidate regs [PR94605]
early-remat.c:process_block wasn't handling insns that set multiple
candidate registers, which led to an assertion failure at the end
of the main loop.
Instructions that set two pseudos aren't rematerialisation candidates in
themselves, but we still need to track them if another instruction that
sets the same register is a rematerialisation candidate.
2020-04-16 Richard Sandiford <richard.sandiford@arm.com>
gcc/
PR rtl-optimization/94605
* early-remat.c (early_remat::process_block): Handle insns that
set multiple candidate registers.
gcc/testsuite/
PR rtl-optimization/94605
* gcc.target/aarch64/sve/pr94605.c: New test.
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/early-remat.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/sve/pr94605.c | 12 |
4 files changed, 24 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9f2f5db..2901b2f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-04-16 Richard Sandiford <richard.sandiford@arm.com> + + PR rtl-optimization/94605 + * early-remat.c (early_remat::process_block): Handle insns that + set multiple candidate registers. + 2020-04-16 Richard Biener <rguenther@suse.de> PR middle-end/94614 diff --git a/gcc/early-remat.c b/gcc/early-remat.c index 80672cc..9f5f854 100644 --- a/gcc/early-remat.c +++ b/gcc/early-remat.c @@ -2020,7 +2020,7 @@ early_remat::process_block (basic_block bb) } /* Now process definitions. */ - if (next_def && insn == next_def->insn) + while (next_def && insn == next_def->insn) { unsigned int gen = canon_candidate (next_candidate); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index f35d4e1..ed44204 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-04-16 Richard Sandiford <richard.sandiford@arm.com> + + PR rtl-optimization/94605 + * gcc.target/aarch64/sve/pr94605.c: New test. + 2020-04-16 Richard Biener <rguenther@suse.de> * gcc.dg/graphite/interchange-1.c: Remove scan for tiled. diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr94605.c b/gcc/testsuite/gcc.target/aarch64/sve/pr94605.c new file mode 100644 index 0000000..593e959 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr94605.c @@ -0,0 +1,12 @@ +/* { dg-options "-O2 -msve-vector-bits=256" } */ + +typedef int v8si __attribute__((vector_size(32))); +int g (v8si, v8si); + +void +f (void) +{ + v8si x = {}, y = {}; + while (g (x, y)) + asm ("" : "+w" (x), "+w" (y)); +} |