sparc.c (input_operand): Recognize (const (constant_p_rtx)).

        * sparc.c (input_operand): Recognize (const (constant_p_rtx)).
        (arith_operand): Remove constant_p_rtx handling.
        (const64_operand, const64_high_operand): Likewise.
        (arith11_operand, arith10_operand, arith_double_operand): Likewise.
        (arith11_double_operand, arith10_double_operand, small_int): Likewise.
        (small_int_or_double, uns_small_int, zero_operand): Likewise.
        * sparc.h (PREDICATE_CODES): Likewise.

From-SVN: r24440

3 files changed, 71 insertions, 73 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cb230d9..c33075b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+Tue Dec 29 11:58:53 1998  Richard Henderson  <rth@cygnus.com>
+
+	* sparc.c (input_operand): Recognize (const (constant_p_rtx)).
+	(arith_operand): Remove constant_p_rtx handling.
+	(const64_operand, const64_high_operand): Likewise.
+	(arith11_operand, arith10_operand, arith_double_operand): Likewise.
+	(arith11_double_operand, arith10_double_operand, small_int): Likewise.
+	(small_int_or_double, uns_small_int, zero_operand): Likewise.
+	* sparc.h (PREDICATE_CODES): Likewise.
+
 Tue Dec 29 11:32:54 1998  Richard Kenner  <kenner@vlsi1.ultra.nyu.edu>:
 
 	* rtl.def (CONSTANT_P_RTX): Clarify commentary.
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index f3e48c8..2748a9a 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -792,8 +792,7 @@ arith_operand (op, mode)
      enum machine_mode mode;
 {
   int val;
-  if (register_operand (op, mode)
-      || GET_CODE (op) == CONSTANT_P_RTX)
+  if (register_operand (op, mode))
     return 1;
   if (GET_CODE (op) != CONST_INT)
     return 0;
@@ -842,7 +841,7 @@ const64_operand (op, mode)
 		  ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
 		   (HOST_WIDE_INT)0xffffffff : 0)))
 #endif
-	  || GET_CODE (op) == CONSTANT_P_RTX);
+	  );
 }
 
 /* The same, but only for sethi instructions.  */
@@ -864,8 +863,7 @@ const64_high_operand (op, mode)
 	  || (GET_CODE (op) == CONST_DOUBLE
 	      && CONST_DOUBLE_HIGH (op) == 0
 	      && (CONST_DOUBLE_LOW (op) & 0xfffffc00) != 0
-	      && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
-	  || GET_CODE (op) == CONSTANT_P_RTX);
+	      && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
 }
 
 /* Return true if OP is a register, or is a CONST_INT that can fit in a
@@ -878,7 +876,6 @@ arith11_operand (op, mode)
      enum machine_mode mode;
 {
   return (register_operand (op, mode)
-	  || GET_CODE (op) == CONSTANT_P_RTX
 	  || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
 }
 
@@ -892,7 +889,6 @@ arith10_operand (op, mode)
      enum machine_mode mode;
 {
   return (register_operand (op, mode)
-	  || GET_CODE (op) == CONSTANT_P_RTX
 	  || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
 }
 
@@ -909,7 +905,6 @@ arith_double_operand (op, mode)
      enum machine_mode mode;
 {
   return (register_operand (op, mode)
-	  || GET_CODE (op) == CONSTANT_P_RTX
 	  || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
 	  || (! TARGET_ARCH64
 	      && GET_CODE (op) == CONST_DOUBLE
@@ -959,7 +954,6 @@ arith11_double_operand (op, mode)
      enum machine_mode mode;
 {
   return (register_operand (op, mode)
-	  || GET_CODE (op) == CONSTANT_P_RTX
 	  || (GET_CODE (op) == CONST_DOUBLE
 	      && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
 	      && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
@@ -983,7 +977,6 @@ arith10_double_operand (op, mode)
      enum machine_mode mode;
 {
   return (register_operand (op, mode)
-	  || GET_CODE (op) == CONSTANT_P_RTX
 	  || (GET_CODE (op) == CONST_DOUBLE
 	      && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
 	      && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
@@ -1005,8 +998,7 @@ small_int (op, mode)
      rtx op;
      enum machine_mode mode ATTRIBUTE_UNUSED;
 {
-  return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
-	  || GET_CODE (op) == CONSTANT_P_RTX);
+  return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
 }
 
 int
@@ -1017,8 +1009,7 @@ small_int_or_double (op, mode)
   return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
 	  || (GET_CODE (op) == CONST_DOUBLE
 	      && CONST_DOUBLE_HIGH (op) == 0
-	      && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
-	  || GET_CODE (op) == CONSTANT_P_RTX);
+	      && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
 }
 
 /* Recognize operand values for the umul instruction.  That instruction sign
@@ -1032,17 +1023,15 @@ uns_small_int (op, mode)
 {
 #if HOST_BITS_PER_WIDE_INT > 32
   /* All allowed constants will fit a CONST_INT.  */
-  return ((GET_CODE (op) == CONST_INT
-	   && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
-	       || (INTVAL (op) >= 0xFFFFF000
-                   && INTVAL (op) < 0x100000000)))
-	  || GET_CODE (op) == CONSTANT_P_RTX);
+  return (GET_CODE (op) == CONST_INT
+	  && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
+	      || (INTVAL (op) >= 0xFFFFF000
+                  && INTVAL (op) < 0x100000000)));
 #else
-  return (((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
-	   || (GET_CODE (op) == CONST_DOUBLE
-	       && CONST_DOUBLE_HIGH (op) == 0
-	       && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000))
-	  || GET_CODE (op) == CONSTANT_P_RTX);
+  return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
+	  || (GET_CODE (op) == CONST_DOUBLE
+	      && CONST_DOUBLE_HIGH (op) == 0
+	      && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
 #endif
 }
 
@@ -1070,7 +1059,7 @@ zero_operand (op, mode)
      rtx op;
      enum machine_mode mode ATTRIBUTE_UNUSED;
 {
-  return (op == const0_rtx || GET_CODE (op) == CONSTANT_P_RTX);
+  return op == const0_rtx;
 }
 
 /* Return 1 if OP is a valid operand for the source of a move insn.  */
@@ -1084,6 +1073,10 @@ input_operand (op, mode)
   if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
     return 0;
 
+  /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary.  */
+  if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == CONSTANT_P_RTX)
+    return 1;
+
   /* Allow any one instruction integer constant, and all CONST_INT
      variants when we are working in DImode and !arch64.  */
   if (GET_MODE_CLASS (mode) == MODE_INT
@@ -1112,10 +1105,6 @@ input_operand (op, mode)
 		  ))))
     return 1;
 
-  /* Always match this.  */
-  if (GET_CODE (op) == CONSTANT_P_RTX)
-    return 1;
-
   /* If !arch64 and this is a DImode const, allow it so that
      the splits can be generated.  */
   if (! TARGET_ARCH64
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index 852a93f..a0ecb14 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -3276,50 +3276,49 @@ do {									\
 
 /* Define the codes that are matched by predicates in sparc.c.  */
 
-#define PREDICATE_CODES								    \
-{"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}},			    \
-{"fp_zero_operand", {CONST_DOUBLE}},						    \
-{"intreg_operand", {SUBREG, REG}},						    \
-{"fcc_reg_operand", {REG}},							    \
-{"icc_or_fcc_reg_operand", {REG}},						    \
-{"restore_operand", {REG}},							    \
-{"call_operand", {MEM}},							    \
-{"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE, ADDRESSOF,    \
-                          SUBREG, REG, PLUS, LO_SUM, CONST_INT}},		    \
-{"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE}},		    \
-{"symbolic_memory_operand", {SUBREG, MEM}},					    \
-{"label_ref_operand", {LABEL_REF}},						    \
-{"sp64_medium_pic_operand", {CONST}},						    \
-{"data_segment_operand", {SYMBOL_REF, PLUS, CONST}},				    \
-{"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}},			    \
-{"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}},				    \
-{"splittable_symbolic_memory_operand", {MEM}},					    \
-{"splittable_immediate_memory_operand", {MEM}},					    \
-{"eq_or_neq", {EQ, NE}},							    \
-{"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}},				    \
-{"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}},		    \
-{"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}},					    \
-{"extend_op", {SIGN_EXTEND, ZERO_EXTEND}},					    \
-{"cc_arithop", {AND, IOR, XOR}},						    \
-{"cc_arithopn", {AND, IOR}},							    \
-{"arith_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT}},			    \
-{"arith_add_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT}},		    \
-{"arith11_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT}},			    \
-{"arith10_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT}},			    \
-{"arith_double_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT, CONST_DOUBLE}},   \
-{"arith_double_add_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT, CONST_DOUBLE}},\
-{"arith11_double_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT, CONST_DOUBLE}}, \
-{"arith10_double_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT, CONST_DOUBLE}}, \
-{"small_int", {CONST_INT, CONSTANT_P_RTX}},					    \
-{"small_int_or_double", {CONST_INT, CONST_DOUBLE, CONSTANT_P_RTX}},		    \
-{"uns_small_int", {CONST_INT, CONSTANT_P_RTX}},					    \
-{"uns_arith_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}},		    \
-{"clobbered_register", {REG}},							    \
-{"input_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT, MEM}},		    \
-{"zero_operand", {CONST_INT, CONSTANT_P_RTX}},					    \
-{"const64_operand", {CONST_INT, CONST_DOUBLE, CONSTANT_P_RTX}},			    \
-{"const64_high_operand", {CONST_INT, CONST_DOUBLE, CONSTANT_P_RTX}},
-
+#define PREDICATE_CODES							\
+{"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}},		\
+{"fp_zero_operand", {CONST_DOUBLE}},					\
+{"intreg_operand", {SUBREG, REG}},					\
+{"fcc_reg_operand", {REG}},						\
+{"icc_or_fcc_reg_operand", {REG}},					\
+{"restore_operand", {REG}},						\
+{"call_operand", {MEM}},						\
+{"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE,	\
+	ADDRESSOF, SUBREG, REG, PLUS, LO_SUM, CONST_INT}},		\
+{"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE}},	\
+{"symbolic_memory_operand", {SUBREG, MEM}},				\
+{"label_ref_operand", {LABEL_REF}},					\
+{"sp64_medium_pic_operand", {CONST}},					\
+{"data_segment_operand", {SYMBOL_REF, PLUS, CONST}},			\
+{"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}},		\
+{"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}},			\
+{"splittable_symbolic_memory_operand", {MEM}},				\
+{"splittable_immediate_memory_operand", {MEM}},				\
+{"eq_or_neq", {EQ, NE}},						\
+{"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}},			\
+{"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}},	\
+{"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}},				\
+{"extend_op", {SIGN_EXTEND, ZERO_EXTEND}},				\
+{"cc_arithop", {AND, IOR, XOR}},					\
+{"cc_arithopn", {AND, IOR}},						\
+{"arith_operand", {SUBREG, REG, CONST_INT}},				\
+{"arith_add_operand", {SUBREG, REG, CONST_INT}},			\
+{"arith11_operand", {SUBREG, REG, CONST_INT}},				\
+{"arith10_operand", {SUBREG, REG, CONST_INT}},				\
+{"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}},	\
+{"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}},	\
+{"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}},	\
+{"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}},	\
+{"small_int", {CONST_INT}},						\
+{"small_int_or_double", {CONST_INT, CONST_DOUBLE}},			\
+{"uns_small_int", {CONST_INT}},						\
+{"uns_arith_operand", {SUBREG, REG, CONST_INT}},			\
+{"clobbered_register", {REG}},						\
+{"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}},		\
+{"zero_operand", {CONST_INT}},						\
+{"const64_operand", {CONST_INT, CONST_DOUBLE}},				\
+{"const64_high_operand", {CONST_INT, CONST_DOUBLE}},
 
 /* The number of Pmode words for the setjmp buffer.  */
 #define JMP_BUF_SIZE 12