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| author | mayshao <mayshao-oc@zhaoxin.com> | 2024-07-18 22:43:00 +0200 |
|---|---|---|
| committer | Uros Bizjak <ubizjak@gmail.com> | 2024-07-18 22:45:07 +0200 |
| commit | 9846b0916c1a9b9f3e9df4657670ef4419617134 (patch) | |
| tree | 0ad09e71c1cf28f14135a61308c3ce5da43aa749 | |
| parent | 9690fb3a43e5cf26a5fb853283d4200df312a640 (diff) | |
| download | gcc-9846b0916c1a9b9f3e9df4657670ef4419617134.zip gcc-9846b0916c1a9b9f3e9df4657670ef4419617134.tar.gz gcc-9846b0916c1a9b9f3e9df4657670ef4419617134.tar.bz2 | |
libatomic: Handle AVX+CX16 ZHAOXIN like Intel for 16b atomic [PR104688]
PR target/104688
libatomic/ChangeLog:
* config/x86/init.c (__libat_feat1_init): Don't clear
bit_AVX on ZHAOXIN CPUs.
| -rw-r--r-- | libatomic/config/x86/init.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/libatomic/config/x86/init.c b/libatomic/config/x86/init.c index 26168d4..c6ce997 100644 --- a/libatomic/config/x86/init.c +++ b/libatomic/config/x86/init.c @@ -41,11 +41,15 @@ __libat_feat1_init (void) { /* Intel SDM guarantees that 16-byte VMOVDQA on 16-byte aligned address is atomic, and AMD is going to do something similar soon. - We don't have a guarantee from vendors of other CPUs with AVX, - like Zhaoxin and VIA. */ + Zhaoxin also guarantees this. We don't have a guarantee + from vendors of other CPUs with AVX, like VIA. */ + unsigned int family = (eax >> 8) & 0x0f; unsigned int ecx2; __cpuid (0, eax, ebx, ecx2, edx); - if (ecx2 != signature_INTEL_ecx && ecx2 != signature_AMD_ecx) + if (ecx2 != signature_INTEL_ecx + && ecx2 != signature_AMD_ecx + && !(ecx2 == signature_CENTAUR_ecx && family > 6) + && ecx2 != signature_SHANGHAI_ecx) FEAT1_REGISTER &= ~bit_AVX; } #endif |