diff options
| author | Wolfgang Gellerich <gellerich@de.ibm.com> | 2008-08-15 07:36:40 +0000 |
|---|---|---|
| committer | Andreas Krebbel <krebbel@gcc.gnu.org> | 2008-08-15 07:36:40 +0000 |
| commit | 9381e3f1da8b6f5911ea85de43a3808dd7e49db9 (patch) | |
| tree | c3d715e00b1ee0379cbc13b408228ae9a00f3c52 | |
| parent | 501bbad73ffd655e9b22d58e2812275acd7858e3 (diff) | |
| download | gcc-9381e3f1da8b6f5911ea85de43a3808dd7e49db9.zip gcc-9381e3f1da8b6f5911ea85de43a3808dd7e49db9.tar.gz gcc-9381e3f1da8b6f5911ea85de43a3808dd7e49db9.tar.bz2 | |
2008-08-15 Wolfgang Gellerich <gellerich@de.ibm.com>
* config/s390/2097.md New file.
* config/s390/s390.md ("z10prop" attribute): Define none,
z10_super, z10_super_E1, z10_super_A1, z10_super_c,
z10_super_c_E1, z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
z10_rec, z10_fr, z10_fr_A3, z10_fr_E1, z10_c, and z10_cobra as
possible values and apply them to insns as appropriate.
("type" attribute): Removed itof and added ftrunctf,ftruncdf,
ftruncsd, ftruncdd, itoftf, itofdf, itofsf, itofdd, itoftd,
fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, fsimpdd,
fsimpsd, fsimptd, fstoredd, fstoresd, ftoidfp as possible
values.
("bfp" mode attribute): Removed. Every occurence replaced
with <mode>.
* config/s390/s390.c (struct "z10_cost"): Updated entries.
* config/s390/2084.md (insn_reservation "x_itof"): Updated
type attribute.
From-SVN: r139124
| -rw-r--r-- | gcc/ChangeLog | 19 | ||||
| -rw-r--r-- | gcc/config/s390/2084.md | 2 | ||||
| -rw-r--r-- | gcc/config/s390/2097.md | 764 | ||||
| -rw-r--r-- | gcc/config/s390/s390.c | 53 | ||||
| -rw-r--r-- | gcc/config/s390/s390.md | 879 |
5 files changed, 1444 insertions, 273 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 73b478e..d25df32 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,22 @@ +2008-08-15 Wolfgang Gellerich <gellerich@de.ibm.com> + + * config/s390/2097.md New file. + * config/s390/s390.md ("z10prop" attribute): Define none, + z10_super, z10_super_E1, z10_super_A1, z10_super_c, + z10_super_c_E1, z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, + z10_rec, z10_fr, z10_fr_A3, z10_fr_E1, z10_c, and z10_cobra as + possible values and apply them to insns as appropriate. + ("type" attribute): Removed itof and added ftrunctf,ftruncdf, + ftruncsd, ftruncdd, itoftf, itofdf, itofsf, itofdd, itoftd, + fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, fsimpdd, + fsimpsd, fsimptd, fstoredd, fstoresd, ftoidfp as possible + values. + ("bfp" mode attribute): Removed. Every occurence replaced + with <mode>. + * config/s390/s390.c (struct "z10_cost"): Updated entries. + * config/s390/2084.md (insn_reservation "x_itof"): Updated + type attribute. + 2008-08-14 Manuel Lopez-Ibanez <manu@gcc.gnu.org> PR c/28152 diff --git a/gcc/config/s390/2084.md b/gcc/config/s390/2084.md index 0c42f18..d3c9272 100644 --- a/gcc/config/s390/2084.md +++ b/gcc/config/s390/2084.md @@ -243,7 +243,7 @@ (define_insn_reservation "x_itof" 7 (and (eq_attr "cpu" "z990,z9_109") - (eq_attr "type" "itof")) + (eq_attr "type" "itoftf,itofdf,itofsf")) "x_e1_t*3,x-wr-fp") (define_bypass 1 "x_fsimpdf" "x_fstoredf") diff --git a/gcc/config/s390/2097.md b/gcc/config/s390/2097.md new file mode 100644 index 0000000..f27302e --- /dev/null +++ b/gcc/config/s390/2097.md @@ -0,0 +1,764 @@ +;; Scheduling description for z10 (cpu 2097). +;; Copyright (C) 2008 Free Software Foundation, Inc. +;; Contributed by Wolfgang Gellerich (gellerich@de.ibm.com). + + +; General naming conventions used in this file: +; - The two pipelines are called S and T, respectively. +; - A name ending "_S" or "_T" indicates that something happens in +; (or belongs to) this pipeline. +; - A name ending "_ANY" indicates that something happens in (or belongs +; to) either of the two pipelines. +; - A name ending "_BOTH" indicates that something happens in (or belongs +; to) both pipelines. + + +;; Automaton and components. + +(define_automaton "z10_cpu") + +(define_cpu_unit "z10_e1_S, z10_e1_T" "z10_cpu") +(define_reservation "z10_e1_ANY" "(z10_e1_S | z10_e1_T)") +(define_reservation "z10_e1_BOTH" "(z10_e1_S + z10_e1_T)") + + +; Both pipelines can execute a branch instruction, and branch +; instructions can be grouped with all other groupable instructions +; but not with a second branch instruction. + +(define_cpu_unit "z10_branch_ANY" "z10_cpu") + +(define_insn_reservation "z10_branch" 4 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "branch")) + "z10_branch_ANY + z10_e1_ANY, z10_Gate_ANY") + + +; Z10 operand and result forwarding. + +; Instructions marked with the attributes as z10_fwd or z10_fr can +; forward a value they load from one of their operants into a register +; if the instruction in the second pipeline reads the same register. +; The second operation must be superscalar. Instructions marked as +; z10_rec or z10_fr can receive a value they read from a register is +; this register gets updated by an instruction in the first pipeline. +; The first instruction must be superscalar. + + +; Forwarding from z10_fwd and z10_fr to z10_super. + +(define_bypass 0 "z10_la_fwd, z10_la_fwd_A1, z10_larl_fwd, z10_larl_fwd_A3, \ + z10_load_fwd, z10_load_fwd_A3, \ + z10_other_fwd, z10_other_fwd_A1, z10_other_fwd_A3, \ + z10_other_fr, z10_other_fr_A3, z10_other_fr_E1, \ + z10_other_fwd_E1, z10_lr_fr, z10_lr_fr_E1, \ + z10_int_fwd, z10_int_fwd_A1, z10_int_fwd_A3, \ + z10_int_fwd_E1, z10_int_fr, z10_int_fr_E1, \ + z10_int_fr_A3" + "z10_other_super, z10_other_super_c_E1, z10_other_super_E1, \ + z10_int_super, z10_int_super_E1, \ + z10_lr, z10_store_super") + + +; Forwarding from z10_super to frz10_ and z10_rec. + +(define_bypass 0 "z10_other_super, z10_other_super_E1, z10_other_super_c_E1, \ + z10_int_super, z10_int_super_E1, \ + z10_larl_super_E1, z10_larl_super, \ + z10_store_super" + "z10_int_fr, z10_int_fr_E1, z10_int_fr_A3, \ + z10_other_fr, z10_other_fr_A3, z10_lr_fr, z10_lr_fr_E1, \ + z10_other_fr_E1, z10_store_rec") + + +; Forwarding from z10_fwd and z10_fr to z10_rec and z10_fr. + +(define_bypass 0 "z10_la_fwd, z10_la_fwd_A1, z10_larl_fwd, z10_larl_fwd_A3, \ + z10_load_fwd, z10_load_fwd_A3, \ + z10_other_fwd, z10_other_fwd_A1, z10_other_fwd_A3, \ + z10_other_fr, z10_other_fr_A3, z10_other_fr_E1, \ + z10_other_fwd_E1, \ + z10_lr_fr, z10_lr_fr_E1, \ + z10_int_fwd, z10_int_fwd_A1, z10_int_fwd_A3, \ + z10_int_fwd_E1, z10_int_fr, z10_int_fr_E1, \ + z10_int_fr_A3" + "z10_int_fr, z10_int_fr_E1, z10_int_fr_A3, \ + z10_other_fr, z10_other_fr_A3, z10_lr_fr, z10_lr_fr_E1, \ + z10_other_fr_E1, z10_store_rec") + + +; +; Simple insns +; + +; Here is the cycle diagram for FXU-executed instructions: +; ... A1 A2 A3 E1 P1 P2 P3 R0 ... +; ^ ^ ^ +; | | updated GPR is available +; | write to GPR +; instruction reads GPR during this cycle + + +; Variants of z10_int follow. + +(define_insn_reservation "z10_int" 6 + (and (and (eq_attr "cpu" "z10") + (eq_attr "type" "integer")) + (and (eq_attr "atype" "reg") + (and (and (eq_attr "z10prop" "!z10_super") + (eq_attr "z10prop" "!z10_super_c")) + (and (and (and (and (eq_attr "z10prop" "!z10_super_E1") + (eq_attr "z10prop" "!z10_super_c_E1")) + (eq_attr "z10prop" "!z10_fwd")) + (and (eq_attr "z10prop" "!z10_fwd_A1") + (eq_attr "z10prop" "!z10_fwd_A3"))) + (and (and (eq_attr "z10prop" "!z10_fwd_E1") + (eq_attr "z10prop" "!z10_fr")) + (and (eq_attr "z10prop" "!z10_fr_E1") + (eq_attr "z10prop" "!z10_fr_A3"))))))) + "z10_e1_ANY, z10_Gate_ANY") + +(define_insn_reservation "z10_int_super" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "integer") + (and (eq_attr "atype" "reg") + (ior (eq_attr "z10prop" "z10_super") + (eq_attr "z10prop" "z10_super_c"))))) + "z10_e1_ANY, z10_Gate_ANY") + +(define_insn_reservation "z10_int_super_E1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "integer") + (and (eq_attr "atype" "reg") + (ior (eq_attr "z10prop" "z10_super_E1") + (eq_attr "z10prop" "z10_super_c_E1"))))) + "z10_e1_ANY, z10_Gate_ANY") + +(define_insn_reservation "z10_int_fwd" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "integer") + (and (eq_attr "atype" "reg") + (eq_attr "z10prop" "z10_fwd")))) + "z10_e1_ANY, z10_Gate_ANY") + +(define_insn_reservation "z10_int_fwd_A1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "integer") + (and (eq_attr "atype" "reg") + (eq_attr "z10prop" "z10_fwd_A1")))) + "z10_e1_ANY, z10_Gate_ANY") + +(define_insn_reservation "z10_int_fwd_A3" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "integer") + (and (eq_attr "atype" "reg") + (eq_attr "z10prop" "z10_fwd_A3")))) + "z10_e1_ANY, z10_Gate_ANY") + +(define_insn_reservation "z10_int_fwd_E1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "integer") + (and (eq_attr "atype" "reg") + (eq_attr "z10prop" "z10_fwd_E1")))) + "z10_e1_ANY, z10_Gate_ANY") + +(define_insn_reservation "z10_int_fr" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "integer") + (and (eq_attr "atype" "reg") + (eq_attr "z10prop" "z10_fr")))) + "z10_e1_ANY, z10_Gate_ANY") + +(define_insn_reservation "z10_int_fr_E1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "integer") + (and (eq_attr "atype" "reg") + (eq_attr "z10prop" "z10_fr_E1")))) + "z10_e1_ANY, z10_Gate_ANY") + +(define_insn_reservation "z10_int_fr_A3" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "integer") + (and (eq_attr "atype" "reg") + (eq_attr "z10prop" "z10_fr_A3")))) + "z10_e1_ANY, z10_Gate_ANY") + +; END of z10_int variants + + +(define_insn_reservation "z10_agen" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "integer") + (eq_attr "atype" "agen"))) + "z10_e1_ANY, z10_Gate_ANY") + + +(define_insn_reservation "z10_lr" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "lr") + (and (eq_attr "z10prop" "!z10_fr") + (eq_attr "z10prop" "!z10_fr_E1")))) + "z10_e1_ANY, z10_Gate_ANY") + +(define_insn_reservation "z10_lr_fr" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "lr") + (eq_attr "z10prop" "z10_fr"))) + "z10_e1_ANY, z10_Gate_ANY") +; "z10_e1_ANY") + +(define_insn_reservation "z10_lr_fr_E1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "lr") + (eq_attr "z10prop" "z10_fr_E1"))) + "z10_e1_ANY, z10_Gate_ANY") +; "z10_e1_ANY") + + +(define_insn_reservation "z10_la" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "la") + (and (eq_attr "z10prop" "!z10_fwd") + (eq_attr "z10prop" "!z10_fwd_A1")))) + "z10_e1_ANY, z10_Gate_ANY") + +(define_insn_reservation "z10_la_fwd" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "la") + (eq_attr "z10prop" "z10_fwd"))) + "z10_e1_ANY, z10_Gate_ANY") +; "z10_e1_ANY") + +(define_insn_reservation "z10_la_fwd_A1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "la") + (eq_attr "z10prop" "z10_fwd_A1"))) + "z10_e1_ANY, z10_Gate_ANY") +; "z10_e1_ANY") + + +; larl-type instructions + +(define_insn_reservation "z10_larl" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "larl") + (and (eq_attr "z10prop" "!z10_super_A1") + (and (eq_attr "z10prop" "!z10_fwd") + (and (eq_attr "z10prop" "!z10_fwd_A3") + (and (eq_attr "z10prop" "!z10_super") + (eq_attr "z10prop" "!z10_super_c")) + (and (eq_attr "z10prop" "!z10_super_E1") + (eq_attr "z10prop" "!z10_super_c_E1"))))))) + "z10_e1_ANY, z10_Gate_ANY") + +(define_insn_reservation "z10_larl_super" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "larl") + (and (eq_attr "z10prop" "z10_super") + (eq_attr "z10prop" "z10_super_c")))) + "z10_e1_ANY, z10_Gate_ANY") + +(define_insn_reservation "z10_larl_fwd" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "larl") + (eq_attr "z10prop" "z10_fwd"))) + "z10_e1_ANY, z10_Gate_ANY") + +(define_insn_reservation "z10_larl_fwd_A3" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "larl") + (eq_attr "z10prop" "z10_fwd_A3"))) + "z10_e1_ANY, z10_Gate_ANY") + + +(define_insn_reservation "z10_larl_A1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "larl") + (eq_attr "z10prop" "z10_super_A1"))) + "z10_e1_ANY, z10_Gate_ANY") +; "z10_e1_ANY") + +(define_insn_reservation "z10_larl_super_E1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "larl") + (ior (eq_attr "z10prop" "z10_super_E1") + (eq_attr "z10prop" "z10_super_c_E1")))) + "z10_e1_ANY, z10_Gate_ANY") +; "z10_e1_ANY") + + +(define_insn_reservation "z10_load" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "load") + (and (eq_attr "z10prop" "!z10_fwd") + (eq_attr "z10prop" "!z10_fwd_A3")))) + "z10_e1_ANY, z10_Gate_ANY") + +(define_insn_reservation "z10_load_fwd" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "load") + (eq_attr "z10prop" "z10_fwd"))) + "z10_e1_ANY, z10_Gate_ANY") +; "z10_e1_ANY") + +(define_insn_reservation "z10_load_fwd_A3" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "load") + (eq_attr "z10prop" "z10_fwd_A3"))) + "z10_e1_ANY, z10_Gate_ANY") +; "z10_e1_ANY") + +(define_insn_reservation "z10_store" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "store") + (and (eq_attr "z10prop" "!z10_rec") + (and (eq_attr "z10prop" "!z10_super") + (eq_attr "z10prop" "!z10_super_c"))))) + "z10_e1_ANY, z10_Gate_ANY") + +(define_insn_reservation "z10_store_super" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "store") + (ior (eq_attr "z10prop" "z10_super") + (eq_attr "z10prop" "z10_super_c")))) + "z10_e1_ANY, z10_Gate_ANY") + +(define_insn_reservation "z10_store_rec" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "store") + (eq_attr "z10prop" "z10_rec"))) + "z10_e1_ANY, z10_Gate_ANY") + +; The default_latency is chosen to drain off the pipeline. +(define_insn_reservation "z10_call" 14 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "jsr")) + "z10_e1_BOTH*4, z10_Gate_BOTH") + +; The default latency is for worst case. CS and CSG take one +; cycle only (i.e. latency would be 6). +(define_insn_reservation "z10_sem" 9 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "sem")) + "z10_e1_BOTH*5, z10_Gate_ANY") + +(define_insn_reservation "z10_cs" 6 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "cs")) + "z10_e1_BOTH, z10_Gate_BOTH") + +(define_insn_reservation "z10_vs" 6 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "vs")) + "z10_e1_BOTH*4, z10_Gate_BOTH") + +; Load and store multiple. Actual number of cycles +; in unknown at compile.time. +(define_insn_reservation "z10_stm" 10 + (and (eq_attr "cpu" "z10") + (ior (eq_attr "type" "stm") + (eq_attr "type" "lm"))) + "z10_e1_BOTH*4, z10_Gate_BOTH") + + +; Subsets of z10_other follow. + +(define_insn_reservation "z10_other" 6 + (and (and (eq_attr "cpu" "z10") + (eq_attr "type" "other")) + (and (and (eq_attr "z10prop" "!z10_fwd") + (eq_attr "z10prop" "!z10_fwd_A1")) + (and (and (and (eq_attr "z10prop" "!z10_fr_A3") + (eq_attr "z10prop" "!z10_fwd_A3")) + (and (eq_attr "z10prop" "!z10_fr") + (eq_attr "z10prop" "!z10_fr_E1"))) + (and (and (and (eq_attr "z10prop" "!z10_super") + (eq_attr "z10prop" "!z10_super_c")) + (eq_attr "z10prop" "!z10_super_c_E1")) + (and (eq_attr "z10prop" "!z10_super_E1") + (eq_attr "z10prop" "!z10_fwd_E1")))))) + "z10_e1_BOTH, z10_Gate_BOTH") + +(define_insn_reservation "z10_other_fr_E1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "other") + (eq_attr "z10prop" "z10_fr_E1"))) + "z10_e1_BOTH, z10_Gate_BOTH") + +(define_insn_reservation "z10_other_super_c_E1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "other") + (eq_attr "z10prop" "z10_super_c_E1"))) + "z10_e1_BOTH, z10_Gate_BOTH") + +(define_insn_reservation "z10_other_super_E1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "other") + (eq_attr "z10prop" "z10_super_E1"))) + "z10_e1_BOTH, z10_Gate_BOTH") + +(define_insn_reservation "z10_other_fwd_E1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "other") + (eq_attr "z10prop" "z10_fwd_E1"))) + "z10_e1_BOTH, z10_Gate_BOTH") + +(define_insn_reservation "z10_other_fwd" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "other") + (eq_attr "z10prop" "z10_fwd"))) + "z10_e1_BOTH, z10_Gate_BOTH") + +(define_insn_reservation "z10_other_fwd_A3" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "other") + (eq_attr "z10prop" "z10_fwd_A3"))) + "z10_e1_BOTH, z10_Gate_BOTH") + +(define_insn_reservation "z10_other_fwd_A1" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "other") + (eq_attr "z10prop" "z10_fwd_A1"))) + "z10_e1_BOTH, z10_Gate_BOTH") + +(define_insn_reservation "z10_other_fr" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "other") + (eq_attr "z10prop" "z10_fr"))) + "z10_e1_BOTH, z10_Gate_BOTH") + +(define_insn_reservation "z10_other_fr_A3" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "other") + (eq_attr "z10prop" "z10_fr_A3"))) + "z10_e1_BOTH, z10_Gate_BOTH") + +(define_insn_reservation "z10_other_super" 6 + (and (eq_attr "cpu" "z10") + (and (eq_attr "type" "other") + (ior (eq_attr "z10prop" "z10_super") + (eq_attr "z10prop" "z10_super_c")))) + "z10_e1_BOTH, z10_Gate_BOTH") + +; END of z10_other subsets. + + +; +; Floating point insns +; + +; Z10 executes the following integer operations in the BFU pipeline. + +(define_insn_reservation "z10_mul_sidi" 12 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "imulsi,imuldi,imulhi")) + "z10_e1_BOTH, z10_Gate_FP") + +; Some variants take fewer cycles, but that is not relevant here. +(define_insn_reservation "z10_div" 162 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "idiv")) + "z10_e1_BOTH*4, z10_Gate_FP") + + +; BFP multiplication and general instructions + +(define_insn_reservation "z10_fsimpdf" 12 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fsimpdf,fmuldf")) + "z10_e1_BOTH, z10_Gate_FP") +; Wg "z10_e1_T, z10_Gate_FP") + +(define_insn_reservation "z10_fsimpsf" 12 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fsimpsf,fmulsf")) + "z10_e1_BOTH, z10_Gate_FP") +; Wg "z10_e1_T, z10_Gate_FP") + +(define_insn_reservation "z10_fmultf" 52 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fmultf")) + "z10_e1_BOTH*4, z10_Gate_FP") +; Wg "z10_e1_T*4, z10_Gate_FP") + +(define_insn_reservation "z10_fsimptf" 14 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fsimptf")) + "z10_e1_BOTH*2, z10_Gate_FP") +; Wg "z10_e1_T*2, z10_Gate_FP") + + +; BFP division + +(define_insn_reservation "z10_fdivtf" 113 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fdivtf")) + "z10_e1_T*4, z10_Gate_FP") + +(define_insn_reservation "z10_fdivdf" 41 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fdivdf")) + "z10_e1_T*4, z10_Gate_FP") + +(define_insn_reservation "z10_fdivsf" 34 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fdivsf")) + "z10_e1_T*4, z10_Gate_FP") + + +; BFP sqrt + +(define_insn_reservation "z10_fsqrtsf" 41 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fsqrtsf")) + "z10_e1_T*4, z10_Gate_FP") + +(define_insn_reservation "z10_fsqrtdf" 54 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fsqrtdf")) + "z10_e1_T*4, z10_Gate_FP") + +(define_insn_reservation "z10_fsqrtf" 122 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fsqrttf")) + "z10_e1_T*4, z10_Gate_FP") + + +; BFP load and store + +(define_insn_reservation "z10_floadtf" 12 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "floadtf")) + "z10_e1_T, z10_Gate_FP") + +(define_insn_reservation "z10_floaddf" 12 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "floaddf")) + "z10_e1_T, z10_Gate_FP") + +(define_insn_reservation "z10_floadsf" 12 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "floadsf")) + "z10_e1_T, z10_Gate_FP") + +(define_insn_reservation "z10_fstoredf" 12 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fstoredf,fstoredd")) + "z10_e1_T, z10_Gate_FP") + +(define_insn_reservation "z10_fstoresf" 12 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fstoresf,fstoresd")) + "z10_e1_T, z10_Gate_FP") + + +; BFP truncate +(define_insn_reservation "z10_ftrunctf" 12 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "ftrunctf")) + "z10_e1_T, z10_Gate_FP") + +(define_insn_reservation "z10_ftruncdf" 16 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "ftruncdf")) + "z10_e1_T, z10_Gate_FP") + + +; Conversion between BFP and int. +(define_insn_reservation "z10_ftoi" 13 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "ftoi")) + "z10_e1_T, z10_Gate_FP") + +(define_insn_reservation "z10_itoftf" 14 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "itoftf")) + "z10_e1_T*2, z10_Gate_FP") + +(define_insn_reservation "z10_itofsfdf" 12 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "itofdf,itofsf")) + "z10_e1_T, z10_Gate_FP") + + + +; BFP-related bypasses. There is no bypass for extended mode. +(define_bypass 1 "z10_fsimpdf" "z10_fstoredf") +(define_bypass 1 "z10_fsimpsf" "z10_fstoresf") +(define_bypass 1 "z10_floaddf" "z10_fsimpdf, z10_fstoredf, z10_floaddf") +(define_bypass 1 "z10_floadsf" "z10_fsimpsf, z10_fstoresf, z10_floadsf") + + +; +; insn_reservations for DFP instructions. +; + +; Exact number of cycles is not known at compile-time. +(define_insn_reservation "z10_fdivddtd" 40 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fdivdd,fdivtd")) + "z10_e1_BOTH,z10_Gate_DFU") + +(define_insn_reservation "z10_ftruncsd" 38 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "ftruncsd")) + "z10_e1_BOTH*4,z10_Gate_DFU") + +(define_insn_reservation "z10_ftruncdd" 340 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "ftruncsd")) + "z10_e1_BOTH*4,z10_Gate_DFU") + +(define_insn_reservation "z10_floaddd" 12 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "floaddd")) + "z10_e1_BOTH,z10_Gate_DFU") + +(define_insn_reservation "z10_floadsd" 12 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "floadsd")) + "z10_e1_BOTH,z10_Gate_DFU") + +; Exact number of cycles is not known at compile-time. +(define_insn_reservation "z10_fmulddtd" 35 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fmuldd,fmultd")) + "z10_e1_BOTH,z10_Gate_DFU") + +(define_insn_reservation "z10_fsimpdd" 17 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fsimpdd")) + "z10_e1_BOTH,z10_Gate_DFU") + +(define_insn_reservation "z10_fsimpsd" 17 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fsimpsd")) + "z10_e1_BOTH,z10_Gate_DFU") + +(define_insn_reservation "z10_fsimptd" 18 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "fsimptd")) + "z10_e1_BOTH,z10_Gate_DFU") + +(define_insn_reservation "z10_itofdd" 36 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "itofdd")) + "z10_e1_BOTH*3,z10_Gate_DFU") + +(define_insn_reservation "z10_itoftd" 49 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "itoftd")) + "z10_e1_BOTH*3,z10_Gate_DFU") + +; Exact number of cycles is not known at compile-time. +(define_insn_reservation "z10_ftoidfp" 30 + (and (eq_attr "cpu" "z10") + (eq_attr "type" "ftoidfp")) + "z10_e1_BOTH*3,z10_Gate_DFU") + + +; +; Address-related bypasses +; + +; Here is the cycle diagram for Address-related bypasses: +; ... G1 G2 G3 A0 A1 A2 A3 E1 P1 P2 P3 R0 ... +; ^ ^ ^ ^ ^ +; | | | | E1-type bypasses provide the new addr AFTER this cycle +; | | | A3-type bypasses provide the new addr AFTER this cycle +; | | A1-type bypasses provide the new addr AFTER this cycle +; | AGI resolution, actual USE of address is DURING this cycle +; AGI detection + +(define_bypass 3 "z10_larl_A1, z10_la_fwd_A1, z10_other_fwd_A1, \ + z10_int_fwd_A1" + "z10_agen, z10_la, z10_branch, z10_call, z10_load, \ + z10_store, \ + z10_cs, z10_stm, z10_other" + "s390_agen_dep_p") + + +(define_bypass 5 "z10_larl_fwd_A3, z10_load_fwd_A3, z10_other_fwd_A3, \ + z10_other_fr_A3, z10_int_fwd_A3, z10_int_fr_A3" + "z10_agen, z10_la, z10_branch, z10_call, z10_load, \ + z10_store, \ + z10_cs, z10_stm, z10_other" + "s390_agen_dep_p") + +(define_bypass 6 "z10_other_fr_E1, z10_other_super_c_E1, z10_other_super_E1, \ + z10_other_fwd_E1, \ + z10_lr_fr_E1, z10_larl_super_E1, \ + z10_int_super_E1, z10_int_fwd_E1, z10_int_fr_E1" + "z10_agen, z10_la, z10_branch, z10_call, z10_load, \ + z10_store, \ + z10_cs, z10_stm, z10_other" + "s390_agen_dep_p") + + + +; +; Try to avoid transitions between DFU-, BFU- and FXU-executed instructions as there is a +; dispatch delay required. +; + + +; Declaration for some pseudo-pipeline stages that reflect the +; dispatch gap when issueing an INT/FXU/BFU-executed instruction after +; an instruction executed by a different unit has been executed. The +; approach is that we pretend a pipelined execution of BFU operations +; with as many stages as the gap is long and request that none of +; these stages is busy when issueing a FXU- or DFU-executed +; instruction. Similar for FXU- and DFU-executed instructions. + +; Declaration for FPU stages. +(define_cpu_unit "z10_f0, z10_f1, z10_f2, z10_f3, z10_f4, z10_f5, z10_f6, \ + z10_f7, z10_f8, z10_f9, z10_f10, z10_f11, z10_f12" "z10_cpu") +(define_reservation "z10_FP_PP" "z10_f0, z10_f1, z10_f2, z10_f3, z10_f4, \ + z10_f5, z10_f6, z10_f7, z10_f8, z10_f9, z10_f10, z10_f11, \ + z10_f12") + +; Declaration for FXU stages. +(define_cpu_unit "z10_S1, z10_S2, z10_S3, z10_S4, z10_S5, z10_S6" "z10_cpu") +(define_cpu_unit "z10_T1, z10_T2, z10_T3, z10_T4, z10_T5, z10_T6" "z10_cpu") +(define_reservation "z10_INT_PP" "z10_S1 | z10_T1, z10_S2 | z10_T2, z10_S3 \ + | z10_T3, z10_S4 | z10_T4, z10_S5 | \ + z10_T5, z10_S6 | z10_T6") + +; Declaration for DFU stages. +(define_cpu_unit "z10_d0, z10_d1, z10_d2, z10_d3, z10_d4, z10_d5, z10_d6" + "z10_cpu") +(define_reservation "z10_DFU_PP" "z10_d0, z10_d1, z10_d2, z10_d3, z10_d4, \ + z10_d5, z10_d6") + + +; Pseudo-units representing whether the respective unit is available +; in the sense that using it does not cause a dispatch delay. + +(define_cpu_unit "z10_S_avail, z10_T_avail, z10_FP_avail, z10_DFU_avail" + "z10_cpu") + +(absence_set "z10_FP_avail" + "z10_S1, z10_S2, z10_S3, z10_S4, z10_S5, z10_S6, z10_T1, z10_T2, z10_T3, z10_T4, \ + z10_T5, z10_T6, \ + z10_d0, z10_d1, z10_d2, z10_d3, z10_d4, z10_d5, z10_d6") + +(absence_set "z10_S_avail,z10_T_avail" + "z10_f0, z10_f1, z10_f2, z10_f3, z10_f4, z10_f5, z10_f6, z10_f7, \ + z10_f8, z10_f9, z10_f10, z10_f11, z10_f12, \ + z10_d0, z10_d1, z10_d2, z10_d3, z10_d4, z10_d5, z10_d6") + +(absence_set "z10_DFU_avail" + "z10_S1, z10_S2, z10_S3, z10_S4, z10_S5, z10_S6, z10_T1, z10_T2, z10_T3, z10_T4, \ + z10_T5, z10_T6, \ + z10_f0, z10_f1, z10_f2, z10_f3, z10_f4, z10_f5, z10_f6, z10_f7, \ + z10_f8, z10_f9, z10_f10, z10_f11, z10_f12") + + +; Pseudo-units to be used in insn_reservations. + +(define_reservation "z10_Gate_ANY" "((z10_S_avail | z10_T_avail), z10_INT_PP)") +(define_reservation "z10_Gate_BOTH" "((z10_S_avail + z10_T_avail), z10_INT_PP)") + +(define_reservation "z10_Gate_FP" "z10_FP_avail, z10_FP_PP") + +(define_reservation "z10_Gate_DFU" "z10_DFU_avail, z10_DFU_PP") diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index 9d60c44..957707b 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -192,33 +192,33 @@ struct processor_costs z9_109_cost = static const struct processor_costs z10_cost = { - COSTS_N_INSNS (4), /* M */ - COSTS_N_INSNS (2), /* MGHI */ - COSTS_N_INSNS (2), /* MH */ - COSTS_N_INSNS (2), /* MHI */ - COSTS_N_INSNS (4), /* ML */ - COSTS_N_INSNS (4), /* MR */ - COSTS_N_INSNS (5), /* MS */ - COSTS_N_INSNS (6), /* MSG */ - COSTS_N_INSNS (4), /* MSGF */ - COSTS_N_INSNS (4), /* MSGFR */ - COSTS_N_INSNS (4), /* MSGR */ - COSTS_N_INSNS (4), /* MSR */ - COSTS_N_INSNS (1), /* multiplication in DFmode */ - COSTS_N_INSNS (28), /* MXBR */ - COSTS_N_INSNS (130), /* SQXBR */ - COSTS_N_INSNS (66), /* SQDBR */ + COSTS_N_INSNS (10), /* M */ + COSTS_N_INSNS (10), /* MGHI */ + COSTS_N_INSNS (10), /* MH */ + COSTS_N_INSNS (10), /* MHI */ + COSTS_N_INSNS (10), /* ML */ + COSTS_N_INSNS (10), /* MR */ + COSTS_N_INSNS (10), /* MS */ + COSTS_N_INSNS (10), /* MSG */ + COSTS_N_INSNS (10), /* MSGF */ + COSTS_N_INSNS (10), /* MSGFR */ + COSTS_N_INSNS (10), /* MSGR */ + COSTS_N_INSNS (10), /* MSR */ + COSTS_N_INSNS (10), /* multiplication in DFmode */ + COSTS_N_INSNS (50), /* MXBR */ + COSTS_N_INSNS (120), /* SQXBR */ + COSTS_N_INSNS (52), /* SQDBR */ COSTS_N_INSNS (38), /* SQEBR */ - COSTS_N_INSNS (1), /* MADBR */ - COSTS_N_INSNS (1), /* MAEBR */ - COSTS_N_INSNS (60), /* DXBR */ - COSTS_N_INSNS (40), /* DDBR */ - COSTS_N_INSNS (26), /* DEBR */ - COSTS_N_INSNS (30), /* DLGR */ - COSTS_N_INSNS (23), /* DLR */ - COSTS_N_INSNS (23), /* DR */ - COSTS_N_INSNS (24), /* DSGFR */ - COSTS_N_INSNS (24), /* DSGR */ + COSTS_N_INSNS (10), /* MADBR */ + COSTS_N_INSNS (10), /* MAEBR */ + COSTS_N_INSNS (111), /* DXBR */ + COSTS_N_INSNS (39), /* DDBR */ + COSTS_N_INSNS (32), /* DEBR */ + COSTS_N_INSNS (160), /* DLGR */ + COSTS_N_INSNS (71), /* DLR */ + COSTS_N_INSNS (71), /* DR */ + COSTS_N_INSNS (71), /* DSGFR */ + COSTS_N_INSNS (71), /* DSGR */ }; extern int reload_completed; @@ -5266,6 +5266,7 @@ s390_agen_dep_p (rtx dep_insn, rtx insn) return 0; } + /* A C statement (sans semicolon) to update the integer scheduling priority INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier, reduce the priority to execute INSN later. Do not define this macro if diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index f9e89c9..21cde2b 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -202,8 +202,12 @@ branch,jsr,fsimptf,fsimpdf,fsimpsf, floadtf,floaddf,floadsf,fstoredf,fstoresf, fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, - ftoi,itof,fsqrttf,fsqrtdf,fsqrtsf, - ftrunctf,ftruncdf,other" + ftoi,fsqrttf,fsqrtdf,fsqrtsf, + ftrunctf,ftruncdf, ftruncsd, ftruncdd, + itoftf, itofdf, itofsf, itofdd, itoftd, + fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, + fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, + ftoidfp, other" (cond [(eq_attr "op_type" "NN") (const_string "other") (eq_attr "op_type" "SS") (const_string "cs")] (const_string "integer"))) @@ -217,6 +221,31 @@ (const_string "reg") (const_string "agen"))) +;; Properties concerning Z10 execution grouping and value forwarding. +;; z10_super: instruction is superscalar. +;; z10_super_c: instruction is superscalar and meets the condition of z10_c. +;; z10_fwd: The instruction reads the value of an operand and stores it into a +;; target register. It can forward this value to a second instruction that reads +;; the same register if that second instruction is issued in the same group. +;; z10_rec: The instruction is in the T pipeline and reads a register. If the +;; instruction in the S pipe writes to the register, then the T instruction +;; can immediately read the new value. +;; z10_fr: union of Z10_fwd and z10_rec. +;; z10_c: second operand of instruction is a register and read with complemented bits. +;; z10_cobra: its a compare and branch instruction +;; +;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. + + +(define_attr "z10prop" "none, + z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, + z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, + z10_rec, + z10_fr, z10_fr_A3, z10_fr_E1, + z10_c, z10_cobra" + (const_string "none")) + + ;; Length in bytes. (define_attr "length" "" @@ -272,6 +301,9 @@ ;; Pipeline description for z990, z9-109 and z9-ec. (include "2084.md") +;; Pipeline description for z10 +(include "2097.md") + ;; Predicates (include "predicates.md") @@ -388,12 +420,6 @@ ;; modes and to an empty string for bfp modes. (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) -;; Although it is imprecise for z9-ec we handle all dfp instructions like -;; bfp regarding the pipeline description. -(define_mode_attr bfp [(TF "tf") (DF "df") (SF "sf") - (TD "tf") (DD "df") (SD "sf")]) - - ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode ;; and "0" in SImode. This allows to combine instructions of which the 31bit ;; version only operates on one register. @@ -403,13 +429,13 @@ ;; version only operates on one register. The DImode version needs an additional ;; register for the assembler output. (define_mode_attr 1 [(DI "%1,") (SI "")]) - -;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in + +;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in ;; 'ashift' and "srdl" in 'lshiftrt'. (define_code_attr lr [(ashift "l") (lshiftrt "r")]) ;; In SHIFT templates, this attribute holds the correct standard name for the -;; pattern itself and the corresponding function calls. +;; pattern itself and the corresponding function calls. (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) ;; This attribute handles differences in the instruction 'type' and will result @@ -499,7 +525,8 @@ "@ tm\t%S0,%b1 tmy\t%S0,%b1" - [(set_attr "op_type" "SI,SIY")]) + [(set_attr "op_type" "SI,SIY") + (set_attr "z10prop" "z10_super,z10_super")]) (define_insn "*tmdi_reg" [(set (reg CC_REGNUM) @@ -515,7 +542,8 @@ tmhl\t%0,%i1 tmlh\t%0,%i1 tmll\t%0,%i1" - [(set_attr "op_type" "RI")]) + [(set_attr "op_type" "RI") + (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) (define_insn "*tmsi_reg" [(set (reg CC_REGNUM) @@ -558,7 +586,8 @@ "ltgfr\t%2,%0 ltgf\t%2,%0" [(set_attr "op_type" "RRE,RXY") - (set_attr "cpu_facility" "*,z10")]) + (set_attr "cpu_facility" "*,z10") + (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) ; ltr, lt, ltgr, ltg (define_insn "*tst<mode>_extimm" @@ -571,7 +600,8 @@ "@ lt<g>r\t%2,%0 lt<g>\t%2,%0" - [(set_attr "op_type" "RR<E>,RXY")]) + [(set_attr "op_type" "RR<E>,RXY") + (set_attr "z10prop" "z10_fr_E1,z10_fr_A3") ]) ; ltr, lt, ltgr, ltg (define_insn "*tst<mode>_cconly_extimm" @@ -583,7 +613,8 @@ "@ lt<g>r\t%0,%0 lt<g>\t%2,%0" - [(set_attr "op_type" "RR<E>,RXY")]) + [(set_attr "op_type" "RR<E>,RXY") + (set_attr "z10prop" "z10_fr_E1,z10_fr_A3")]) (define_insn "*tstdi" [(set (reg CC_REGNUM) @@ -593,7 +624,8 @@ (match_dup 0))] "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM" "ltgr\t%2,%0" - [(set_attr "op_type" "RRE")]) + [(set_attr "op_type" "RRE") + (set_attr "z10prop" "z10_fr_E1")]) (define_insn "*tstsi" [(set (reg CC_REGNUM) @@ -606,7 +638,8 @@ ltr\t%2,%0 icm\t%2,15,%S0 icmy\t%2,15,%S0" - [(set_attr "op_type" "RR,RS,RSY")]) + [(set_attr "op_type" "RR,RS,RSY") + (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) (define_insn "*tstsi_cconly" [(set (reg CC_REGNUM) @@ -618,7 +651,8 @@ ltr\t%0,%0 icm\t%2,15,%S0 icmy\t%2,15,%S0" - [(set_attr "op_type" "RR,RS,RSY")]) + [(set_attr "op_type" "RR,RS,RSY") + (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) (define_insn "*tstdi_cconly_31" [(set (reg CC_REGNUM) @@ -636,7 +670,8 @@ (match_operand:GPR 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode)" "lt<g>r\t%0,%0" - [(set_attr "op_type" "RR<E>")]) + [(set_attr "op_type" "RR<E>") + (set_attr "z10prop" "z10_fr_E1")]) ; tst(hi|qi) instruction pattern(s). @@ -651,7 +686,8 @@ icm\t%2,<icm_lo>,%S0 icmy\t%2,<icm_lo>,%S0 tml\t%0,<max_uint>" - [(set_attr "op_type" "RS,RSY,RI")]) + [(set_attr "op_type" "RS,RSY,RI") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) (define_insn "*tsthiCCT_cconly" [(set (reg CC_REGNUM) @@ -663,7 +699,8 @@ icm\t%2,3,%S0 icmy\t%2,3,%S0 tml\t%0,65535" - [(set_attr "op_type" "RS,RSY,RI")]) + [(set_attr "op_type" "RS,RSY,RI") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) (define_insn "*tstqiCCT_cconly" [(set (reg CC_REGNUM) @@ -674,7 +711,8 @@ cli\t%S0,0 cliy\t%S0,0 tml\t%0,255" - [(set_attr "op_type" "SI,SIY,RI")]) + [(set_attr "op_type" "SI,SIY,RI") + (set_attr "z10prop" "z10_super,z10_super,*")]) (define_insn "*tst<mode>" [(set (reg CC_REGNUM) @@ -686,7 +724,8 @@ "@ icm\t%2,<icm_lo>,%S0 icmy\t%2,<icm_lo>,%S0" - [(set_attr "op_type" "RS,RSY")]) + [(set_attr "op_type" "RS,RSY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_insn "*tst<mode>_cconly" [(set (reg CC_REGNUM) @@ -697,7 +736,8 @@ "@ icm\t%2,<icm_lo>,%S0 icmy\t%2,<icm_lo>,%S0" - [(set_attr "op_type" "RS,RSY")]) + [(set_attr "op_type" "RS,RSY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) ; Compare (equality) instructions @@ -713,7 +753,8 @@ cgfi\t%0,%1 cg\t%0,%1 #" - [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")]) + [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") + (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) (define_insn "*cmpsi_cct" [(set (reg CC_REGNUM) @@ -727,8 +768,8 @@ c\t%0,%1 cy\t%0,%1 #" - [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")]) - + [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") + (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super,z10_super,*")]) ; Compare (signed) instructions @@ -743,9 +784,11 @@ cgf\t%0,%1 cgfrl\t%0,%1" [(set_attr "op_type" "RRE,RXY,RIL") - (set_attr "cpu_facility" "*,*,z10") + (set_attr "z10prop" "z10_c,*,*") (set_attr "type" "*,*,larl")]) + + (define_insn "*cmpsi_ccs_sign" [(set (reg CC_REGNUM) (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) @@ -796,7 +839,8 @@ c<g>rl\t%0,%1" [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10") - (set_attr "type" "*,*,*,*,*,*,larl")]) + (set_attr "type" "*,*,*,*,*,*,larl") + (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")]) ; Compare (unsigned) instructions @@ -820,7 +864,8 @@ "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" "cl<g>hrl\t%0,%1" [(set_attr "op_type" "RIL") - (set_attr "type" "larl")]) + (set_attr "type" "larl") + (set_attr "z10prop" "z10_super")]) (define_insn "*cmpdi_ccu_zero" [(set (reg CC_REGNUM) @@ -834,7 +879,8 @@ clgfrl\t%0,%1" [(set_attr "op_type" "RRE,RXY,RIL") (set_attr "cpu_facility" "*,*,z10") - (set_attr "type" "*,*,larl")]) + (set_attr "type" "*,*,larl") + (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")]) (define_insn "*cmpdi_ccu" [(set (reg CC_REGNUM) @@ -853,7 +899,8 @@ #" [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") - (set_attr "type" "*,*,larl,*,*,*,*")]) + (set_attr "type" "*,*,larl,*,*,*,*") + (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")]) (define_insn "*cmpsi_ccu" [(set (reg CC_REGNUM) @@ -871,7 +918,8 @@ #" [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*") - (set_attr "type" "*,*,larl,*,*,*,*,*")]) + (set_attr "type" "*,*,larl,*,*,*,*,*") + (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")]) (define_insn "*cmphi_ccu" [(set (reg CC_REGNUM) @@ -886,7 +934,8 @@ # #" [(set_attr "op_type" "RS,RSY,SIL,SS,SS") - (set_attr "cpu_facility" "*,*,z10,*,*")]) + (set_attr "cpu_facility" "*,*,z10,*,*") + (set_attr "z10prop" "*,*,z10_super,*,*")]) (define_insn "*cmpqi_ccu" [(set (reg CC_REGNUM) @@ -901,7 +950,8 @@ cliy\t%S0,%b1 # #" - [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")]) + [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") + (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) ; Block compare (CLC) instruction patterns. @@ -948,7 +998,7 @@ "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" "lt<xde><bt>r\t%0,%0" [(set_attr "op_type" "RRE") - (set_attr "type" "fsimp<bfp>")]) + (set_attr "type" "fsimp<mode>")]) ; cxtr, cxbr, cdbr, cebr, cxb, cdb, ceb, cxbtr, cdbtr (define_insn "*cmp<mode>_ccs" @@ -960,12 +1010,14 @@ c<xde><bt>r\t%0,%1 c<xde>b\t%0,%1" [(set_attr "op_type" "RRE,RXE") - (set_attr "type" "fsimp<bfp>")]) + (set_attr "type" "fsimp<mode>")]) ; Compare and Branch instructions ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr +; The following instructions do a complementary access of their second +; operand (z01 only): crj_c, cgrjc, cr, cgr (define_insn "*cmp_and_br_signed_<mode>" [(set (pc) (if_then_else (match_operator 0 "s390_signed_integer_comparison" @@ -985,12 +1037,15 @@ } [(set_attr "op_type" "RIE") (set_attr "type" "branch") + (set_attr "z10prop" "z10_cobra,z10_super") (set (attr "length") (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg ; 10 byte for cgr/jg ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr +; The following instructions do a complementary access of their second +; operand (z10 only): clrj, clgrj, clr, clgr (define_insn "*cmp_and_br_unsigned_<mode>" [(set (pc) (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" @@ -1010,6 +1065,7 @@ } [(set_attr "op_type" "RIE") (set_attr "type" "branch") + (set_attr "z10prop" "z10_cobra,z10_super") (set (attr "length") (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg @@ -1210,7 +1266,8 @@ && !FP_REG_P (operands[0])" "larl\t%0,%1" [(set_attr "op_type" "RIL") - (set_attr "type" "larl")]) + (set_attr "type" "larl") + (set_attr "z10prop" "z10_super_A1")]) (define_insn "*movdi_64" [(set (match_operand:DI 0 "nonimmediate_operand" @@ -1255,7 +1312,35 @@ *,*,*") (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, z10,*,*,*,*,*,longdisp,*,longdisp, - z10,z10,*,*,*,*,*")]) + z10,z10,*,*,*,*,*") + (set_attr "z10prop" "z10_fwd_A1, + z10_fwd_E1, + z10_fwd_E1, + z10_fwd_E1, + z10_fwd_E1, + z10_fwd_A1, + z10_fwd_E1, + z10_fwd_E1, + *, + *, + z10_fwd_A1, + z10_fwd_A3, + z10_fr_E1, + z10_fwd_A3, + z10_rec, + *, + *, + *, + *, + *, + z10_rec, + z10_super, + *, + *, + *, + *, + *") +]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -1390,7 +1475,8 @@ la\t%0,%a1 lay\t%0,%a1" [(set_attr "op_type" "RX,RXY") - (set_attr "type" "la")]) + (set_attr "type" "la") + (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) (define_peephole2 [(parallel @@ -1441,7 +1527,8 @@ && !FP_REG_P (operands[0])" "larl\t%0,%1" [(set_attr "op_type" "RIL") - (set_attr "type" "larl")]) + (set_attr "type" "larl") + (set_attr "z10prop" "z10_super_A1")]) (define_insn "*movsi_zarch" [(set (match_operand:SI 0 "nonimmediate_operand" @@ -1475,10 +1562,54 @@ #" [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,SS") - (set_attr "type" "*,*,*,*,la,larl,lr,load,load,store,store, - floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,larl,*,*,*") + (set_attr "type" "*, + *, + *, + *, + la, + larl, + lr, + load, + load, + store, + store, + floadsf, + floadsf, + floadsf, + fstoresf, + fstoresf, + *, + *, + *, + larl, + *, + *, + *") (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, - *,*,longdisp,*,longdisp,*,*,*,z10,z10,*,*")]) + *,*,longdisp,*,longdisp,*,*,*,z10,z10,*,*") + (set_attr "z10prop" "z10_fwd_A1, + z10_fwd_E1, + z10_fwd_E1, + z10_fwd_A1, + z10_fwd_A1, + z10_fwd_A3, + z10_fr_E1, + z10_fwd_A3, + z10_fwd_A3, + z10_super, + z10_rec, + *, + *, + *, + *, + *, + z10_super_E1, + z10_super, + *, + z10_rec, + z10_super, + *, + *")]) (define_insn "*movsi_esa" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q") @@ -1498,7 +1629,20 @@ lam\t%0,%0,%S1 #" [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS") - (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")]) + (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*") + (set_attr "z10prop" "z10_fwd_A1, + z10_fr_E1, + z10_fwd_A3, + z10_super, + *, + *, + *, + z10_super_E1, + z10_super, + *, + *, + *") +]) (define_peephole2 [(set (match_operand:SI 0 "register_operand" "") @@ -1519,7 +1663,8 @@ la\t%0,%a1 lay\t%0,%a1" [(set_attr "op_type" "RX,RXY") - (set_attr "type" "la")]) + (set_attr "type" "la") + (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) (define_peephole2 [(parallel @@ -1554,7 +1699,8 @@ la\t%0,%a1 lay\t%0,%a1" [(set_attr "op_type" "RX,RXY") - (set_attr "type" "la")]) + (set_attr "type" "la") + (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) (define_insn_and_split "*la_31_and_cc" [(set (match_operand:SI 0 "register_operand" "=d") @@ -1579,7 +1725,8 @@ la\t%0,%a1 lay\t%0,%a1" [(set_attr "op_type" "RX") - (set_attr "type" "la")]) + (set_attr "type" "la") + (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) ; ; movhi instruction pattern(s). @@ -1620,7 +1767,17 @@ #" [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,SS") (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*") - (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10,*")]) + (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10,*") + (set_attr "z10prop" "z10_fr_E1, + z10_fwd_A1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super, + z10_rec, + z10_rec, + z10_super, + *")]) (define_peephole2 [(set (match_operand:HI 0 "register_operand" "") @@ -1669,7 +1826,16 @@ mviy\t%S0,%b1 #" [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS") - (set_attr "type" "lr,*,*,*,store,store,store,store,*")]) + (set_attr "type" "lr,*,*,*,store,store,store,store,*") + (set_attr "z10prop" "z10_fr_E1, + z10_fwd_A1, + z10_super_E1, + z10_super_E1, + z10_super, + z10_rec, + z10_super, + z10_super, + *")]) (define_peephole2 [(set (match_operand:QI 0 "nonimmediate_operand" "") @@ -1692,7 +1858,8 @@ "@ ic\t%0,%1 icy\t%0,%1" - [(set_attr "op_type" "RX,RXY")]) + [(set_attr "op_type" "RX,RXY") + (set_attr "z10prop" "z10_super_E1,z10_super")]) ; ; movstricthi instruction pattern(s). @@ -1706,7 +1873,8 @@ "@ icm\t%0,3,%S1 icmy\t%0,3,%S1" - [(set_attr "op_type" "RS,RSY")]) + [(set_attr "op_type" "RS,RSY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) ; ; movstrictsi instruction pattern(s). @@ -1722,7 +1890,8 @@ ly\t%0,%1 ear\t%0,%1" [(set_attr "op_type" "RR,RX,RXY,RRE") - (set_attr "type" "lr,load,load,*")]) + (set_attr "type" "lr,load,load,*") + (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) ; ; mov(tf|td) instruction pattern(s). @@ -1812,7 +1981,7 @@ (define_split [(set (match_operand:TD_TF 0 "register_operand" "") (match_operand:TD_TF 1 "memory_operand" ""))] - "reload_completed && offsettable_memref_p (operands[1]) + "reload_completed && offsettable_memref_p (operands[1]) && FP_REG_P (operands[0])" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] @@ -1872,7 +2041,20 @@ #" [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, - fstoredf,fstoredf,lr,load,store,*")]) + fstoredf,fstoredf,lr,load,store,*") + (set_attr "z10prop" "*, + *, + *, + *, + *, + *, + *, + *, + z10_fr_E1, + z10_fwd_A3, + z10_rec, + *") +]) (define_insn "*mov<mode>_64" [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT,?Q") @@ -1890,8 +2072,18 @@ stg\t%1,%0 #" [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") - (set_attr "type" "fsimp<bfp>,fload<bfp>,fload<bfp>,fload<bfp>, - fstore<bfp>,fstore<bfp>,lr,load,store,*")]) + (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>, + fstore<mode>,fstore<mode>,lr,load,store,*") + (set_attr "z10prop" "*, + *, + *, + *, + *, + *, + z10_fr_E1, + z10_fwd_A3, + z10_rec, + *")]) (define_insn "*mov<mode>_31" [(set (match_operand:DD_DF 0 "nonimmediate_operand" @@ -1914,8 +2106,8 @@ # #" [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS") - (set_attr "type" "fsimp<bfp>,fload<bfp>,fload<bfp>,fload<bfp>, - fstore<bfp>,fstore<bfp>,lm,lm,stm,stm,*,*,*")]) + (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>, + fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*,*")]) (define_split [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") @@ -1982,8 +2174,20 @@ sty\t%1,%0 #" [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") - (set_attr "type" "fsimp<bfp>,fload<bfp>,fload<bfp>,fload<bfp>, - fstore<bfp>,fstore<bfp>,lr,load,load,store,store,*")]) + (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>, + fstore<mode>,fstore<mode>,lr,load,load,store,store,*") + (set_attr "z10prop" "*, + *, + *, + *, + *, + *, + z10_fr_E1, + z10_fwd_A3, + z10_fwd_A3, + z10_super, + z10_rec, + *")]) ; ; movcc instruction pattern @@ -2002,7 +2206,8 @@ l\t%1,%0 ly\t%1,%0" [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") - (set_attr "type" "lr,*,*,store,store,load,load")]) + (set_attr "type" "lr,*,*,store,store,load,load") + (set_attr "z10prop" "z10_fr_E1,*,*,z10_super,z10_rec,z10_fwd_A3,z10_fwd_A3")]) ; ; Block move (MVC) patterns. @@ -2042,7 +2247,7 @@ (use (match_operand 5 "const_int_operand" ""))])] "s390_offset_p (operands[0], operands[3], operands[2]) && s390_offset_p (operands[1], operands[4], operands[2]) - && !s390_overlap_p (operands[0], operands[1], + && !s390_overlap_p (operands[0], operands[1], INTVAL (operands[2]) + INTVAL (operands[5])) && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" [(parallel @@ -2348,19 +2553,19 @@ "clst\t%0,%1\;jo\t.-4" [(set_attr "length" "8") (set_attr "type" "vs")]) - + ; ; movstr instruction pattern. ; (define_expand "movstr" [(set (reg:SI 0) (const_int 0)) - (parallel + (parallel [(clobber (match_dup 3)) (set (match_operand:BLK 1 "memory_operand" "") (match_operand:BLK 2 "memory_operand" "")) (set (match_operand 0 "register_operand" "") - (unspec [(match_dup 1) + (unspec [(match_dup 1) (match_dup 2) (reg:SI 0)] UNSPEC_MVST)) (clobber (reg:CC CC_REGNUM))])] @@ -2381,7 +2586,7 @@ (set (mem:BLK (match_operand:P 1 "register_operand" "0")) (mem:BLK (match_operand:P 3 "register_operand" "2"))) (set (match_operand:P 0 "register_operand" "=d") - (unspec [(mem:BLK (match_dup 1)) + (unspec [(mem:BLK (match_dup 1)) (mem:BLK (match_dup 3)) (reg:SI 0)] UNSPEC_MVST)) (clobber (reg:CC CC_REGNUM))] @@ -2389,7 +2594,7 @@ "mvst\t%1,%2\;jo\t.-4" [(set_attr "length" "8") (set_attr "type" "vs")]) - + ; ; movmemM instruction pattern(s). @@ -2477,7 +2682,7 @@ "reload_completed && TARGET_CPU_ZARCH" [(set (match_dup 3) (label_ref (match_dup 4))) (parallel - [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) + [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) (label_ref (match_dup 4))] UNSPEC_EXECUTE) (set (match_dup 0) (match_dup 1)) (use (const_int 1))])] @@ -2538,8 +2743,8 @@ (define_expand "signbit<mode>2" [(set (reg:CCZ CC_REGNUM) - (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") - (match_dup 2)] + (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") + (match_dup 2)] UNSPEC_TDC_INSN)) (set (match_operand:SI 0 "register_operand" "=d") (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))] @@ -2550,8 +2755,8 @@ (define_expand "isinf<mode>2" [(set (reg:CCZ CC_REGNUM) - (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") - (match_dup 2)] + (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") + (match_dup 2)] UNSPEC_TDC_INSN)) (set (match_operand:SI 0 "register_operand" "=d") (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))] @@ -2563,16 +2768,16 @@ ; This insn is used to generate all variants of the Test Data Class ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand ; is the register to be tested and the second one is the bit mask -; specifying the required test(s). +; specifying the required test(s). ; (define_insn "*TDC_insn_<mode>" [(set (reg:CCZ CC_REGNUM) - (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") + (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] "TARGET_HARD_FLOAT" "t<_d>c<xde><bt>\t%0,%1" [(set_attr "op_type" "RXE") - (set_attr "type" "fsimp<bfp>")]) + (set_attr "type" "fsimp<mode>")]) (define_insn_and_split "*ccz_to_int" [(set (match_operand:SI 0 "register_operand" "=d") @@ -2679,14 +2884,14 @@ "reload_completed && TARGET_CPU_ZARCH" [(set (match_dup 2) (label_ref (match_dup 3))) (parallel - [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) + [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) (label_ref (match_dup 3))] UNSPEC_EXECUTE) (set (match_dup 0) (const_int 0)) (use (const_int 1)) (clobber (reg:CC CC_REGNUM))])] "operands[3] = gen_label_rtx ();") -; Initialize a block of arbitrary length with (operands[2] % 256). +; Initialize a block of arbitrary length with (operands[2] % 256). (define_expand "setmem_long" [(parallel @@ -2833,7 +3038,7 @@ "reload_completed && TARGET_CPU_ZARCH" [(set (match_dup 3) (label_ref (match_dup 4))) (parallel - [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) + [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) (label_ref (match_dup 4))] UNSPEC_EXECUTE) (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) (use (const_int 1))])] @@ -2938,7 +3143,7 @@ (define_insn_and_split "*cmpint_sign_cc" [(set (reg CC_REGNUM) - (compare (ashiftrt:DI (ashift:DI (subreg:DI + (compare (ashiftrt:DI (ashift:DI (subreg:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] UNSPEC_CCU_TO_INT) 0) (const_int 32)) (const_int 32)) @@ -2972,7 +3177,8 @@ "@ icm\t%0,%2,%S1 icmy\t%0,%2,%S1" - [(set_attr "op_type" "RS,RSY")]) + [(set_attr "op_type" "RS,RSY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_insn "*sethighpartdi_64" [(set (match_operand:DI 0 "register_operand" "=d") @@ -2992,7 +3198,9 @@ "@ icm\t%0,%2,%S1 icmy\t%0,%2,%S1" - [(set_attr "op_type" "RS,RSY")]) + [(set_attr "op_type" "RS,RSY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) + (define_insn_and_split "*extzv<mode>" [(set (match_operand:GPR 0 "register_operand" "=d") @@ -3083,7 +3291,8 @@ return "risbg\t%0,%3,%b2,%b1,%b4"; } - [(set_attr "op_type" "RIE")]) + [(set_attr "op_type" "RIE") + (set_attr "z10prop" "z10_super_E1")]) ; and op1 with a mask being 1 for the selected bits and 0 for the rest ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest @@ -3112,7 +3321,8 @@ return "risbg\t%0,%1,%b5,%b6,%b7"; } - [(set_attr "op_type" "RIE")]) + [(set_attr "op_type" "RIE") + (set_attr "z10prop" "z10_super_E1")]) ; and op1 with a mask being 1 for the selected bits and 0 for the rest (define_insn "*insv<mode>_or_z10_noshift" @@ -3151,10 +3361,11 @@ int size = INTVAL (operands[1]) / BITS_PER_UNIT; operands[1] = GEN_INT ((1ul << size) - 1); - return (which_alternative == 0) ? "stcm\t%2,%1,%S0" + return (which_alternative == 0) ? "stcm\t%2,%1,%S0" : "stcmy\t%2,%1,%S0"; } - [(set_attr "op_type" "RS,RSY")]) + [(set_attr "op_type" "RS,RSY") + (set_attr "z10prop" "z10_super,z10_super")]) (define_insn "*insvdi_mem_reghigh" [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS") @@ -3172,7 +3383,8 @@ operands[1] = GEN_INT ((1ul << size) - 1); return "stcmh\t%2,%1,%S0"; } -[(set_attr "op_type" "RSY")]) +[(set_attr "op_type" "RSY") + (set_attr "z10prop" "z10_super")]) (define_insn "*insv<mode>_reg_imm" [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") @@ -3193,7 +3405,9 @@ default: gcc_unreachable(); } } - [(set_attr "op_type" "RI")]) + [(set_attr "op_type" "RI") + (set_attr "z10prop" "z10_super_E1")]) + (define_insn "*insv<mode>_reg_extimm" [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") @@ -3212,7 +3426,9 @@ default: gcc_unreachable(); } } - [(set_attr "op_type" "RIL")]) + [(set_attr "op_type" "RIL") + (set_attr "z10prop" "z10_fwd_E1")]) + ; ; extendsidi2 instruction pattern(s). @@ -3243,7 +3459,8 @@ lgfrl\t%0,%1" [(set_attr "op_type" "RRE,RXY,RIL") (set_attr "type" "*,*,larl") - (set_attr "cpu_facility" "*,*,z10")]) + (set_attr "cpu_facility" "*,*,z10") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) ; ; extend(hi|qi)(si|di)2 instruction pattern(s). @@ -3287,14 +3504,16 @@ lghrl\t%0,%1" [(set_attr "op_type" "RRE,RXY,RIL") (set_attr "type" "*,*,larl") - (set_attr "cpu_facility" "extimm,extimm,z10")]) + (set_attr "cpu_facility" "extimm,extimm,z10") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) (define_insn "*extendhidi2" [(set (match_operand:DI 0 "register_operand" "=d") (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))] "TARGET_64BIT" "lgh\t%0,%1" - [(set_attr "op_type" "RXY")]) + [(set_attr "op_type" "RXY") + (set_attr "z10prop" "z10_super_E1")]) ; ; extendhisi2 instruction pattern(s). @@ -3311,7 +3530,8 @@ lhrl\t%0,%1" [(set_attr "op_type" "RRE,RX,RXY,RIL") (set_attr "type" "*,*,*,larl") - (set_attr "cpu_facility" "extimm,extimm,extimm,z10")]) + (set_attr "cpu_facility" "extimm,extimm,extimm,z10") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) (define_insn "*extendhisi2" [(set (match_operand:SI 0 "register_operand" "=d,d") @@ -3320,7 +3540,8 @@ "@ lh\t%0,%1 lhy\t%0,%1" - [(set_attr "op_type" "RX,RXY")]) + [(set_attr "op_type" "RX,RXY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) ; ; extendqi(si|di)2 instruction pattern(s). @@ -3334,7 +3555,8 @@ "@ l<g>br\t%0,%1 l<g>b\t%0,%1" - [(set_attr "op_type" "RRE,RXY")]) + [(set_attr "op_type" "RRE,RXY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) ; lb, lgb (define_insn "*extendqi<mode>2" @@ -3342,7 +3564,8 @@ (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))] "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" "l<g>b\t%0,%1" - [(set_attr "op_type" "RXY")]) + [(set_attr "op_type" "RXY") + (set_attr "z10prop" "z10_super_E1")]) (define_insn_and_split "*extendqi<mode>2_short_displ" [(set (match_operand:GPR 0 "register_operand" "=d") @@ -3392,7 +3615,8 @@ llgfrl\t%0,%1" [(set_attr "op_type" "RRE,RXY,RIL") (set_attr "type" "*,*,larl") - (set_attr "cpu_facility" "*,*,z10")]) + (set_attr "cpu_facility" "*,*,z10") + (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")]) ; ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). @@ -3404,7 +3628,8 @@ (const_int 2147483647)))] "TARGET_64BIT" "llgt\t%0,%1" - [(set_attr "op_type" "RXE")]) + [(set_attr "op_type" "RXE") + (set_attr "z10prop" "z10_super_E1")]) (define_insn_and_split "*llgt_sidi_split" [(set (match_operand:DI 0 "register_operand" "=d") @@ -3427,7 +3652,8 @@ "@ llgtr\t%0,%1 llgt\t%0,%1" - [(set_attr "op_type" "RRE,RXE")]) + [(set_attr "op_type" "RRE,RXE") + (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_insn "*llgt_didi" [(set (match_operand:DI 0 "register_operand" "=d,d") @@ -3437,7 +3663,8 @@ "@ llgtr\t%0,%1 llgt\t%0,%N1" - [(set_attr "op_type" "RRE,RXE")]) + [(set_attr "op_type" "RRE,RXE") + (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_split [(set (match_operand:GPR 0 "register_operand" "") @@ -3468,7 +3695,7 @@ } else if (!TARGET_EXTIMM) { - rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) - + rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) - GET_MODE_BITSIZE(<MODE>mode)); operands[1] = gen_lowpart (DImode, operands[1]); emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); @@ -3485,7 +3712,7 @@ if (!TARGET_EXTIMM) { operands[1] = gen_lowpart (SImode, operands[1]); - emit_insn (gen_andsi3 (operands[0], operands[1], + emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1))); DONE; } @@ -3502,7 +3729,8 @@ ll<g>hrl\t%0,%1" [(set_attr "op_type" "RXY,RRE,RIL") (set_attr "type" "*,*,larl") - (set_attr "cpu_facility" "*,*,z10")]) + (set_attr "cpu_facility" "*,*,z10") + (set_attr "z10prop" "z10_fwd_A3")]) ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" @@ -3512,7 +3740,8 @@ "@ ll<g><hc>r\t%0,%1 ll<g><hc>\t%0,%1" - [(set_attr "op_type" "RRE,RXY")]) + [(set_attr "op_type" "RRE,RXY") + (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) ; llgh, llgc (define_insn "*zero_extend<HQI:mode><GPR:mode>2" @@ -3520,7 +3749,8 @@ (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))] "TARGET_ZARCH && !TARGET_EXTIMM" "llg<hc>\t%0,%1" - [(set_attr "op_type" "RXY")]) + [(set_attr "op_type" "RXY") + (set_attr "z10prop" "z10_fwd_A3")]) (define_insn_and_split "*zero_extendhisi2_31" [(set (match_operand:SI 0 "register_operand" "=&d") @@ -3564,7 +3794,8 @@ (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] "TARGET_ZARCH && !TARGET_EXTIMM" "llgc\t%0,%1" - [(set_attr "op_type" "RXY")]) + [(set_attr "op_type" "RXY") + (set_attr "z10prop" "z10_fwd_A3")]) (define_insn_and_split "*zero_extendqihi2_31" [(set (match_operand:HI 0 "register_operand" "=&d") @@ -3585,7 +3816,7 @@ [(set (match_operand:DI 0 "register_operand" "") (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) (clobber (match_scratch:TD 2 "=f"))])] - + "TARGET_HARD_FLOAT && TARGET_HARD_DFP" { rtx label1 = gen_label_rtx (); @@ -3597,7 +3828,7 @@ decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ /* 2^63 can't be represented as 64bit DFP number with full precision. The - solution is doing the check and the subtraction in TD mode and using a + solution is doing the check and the subtraction in TD mode and using a TD -> DI convert afterwards. */ emit_insn (gen_extendddtd2 (temp, operands[1])); temp = force_reg (TDmode, temp); @@ -3624,11 +3855,11 @@ rtx label2 = gen_label_rtx (); rtx temp = gen_reg_rtx (TDmode); REAL_VALUE_TYPE cmp, sub; - + operands[1] = force_reg (TDmode, operands[1]); decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ - + emit_insn (gen_cmptd (operands[1], CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode))); emit_jump_insn (gen_blt (label1)); @@ -3644,7 +3875,7 @@ }) ; -; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 +; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 ; instruction pattern(s). ; @@ -3657,11 +3888,11 @@ rtx label2 = gen_label_rtx (); rtx temp = gen_reg_rtx (<BFP:MODE>mode); REAL_VALUE_TYPE cmp, sub; - + operands[1] = force_reg (<BFP:MODE>mode, operands[1]); real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode); real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode); - + emit_insn (gen_cmp<BFP:mode> (operands[1], CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode))); emit_jump_insn (gen_blt (label1)); @@ -3724,7 +3955,7 @@ "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_HARD_DFP" "cg<DFP:xde>tr\t%0,%h2,%1" [(set_attr "op_type" "RRF") - (set_attr "type" "ftoi")]) + (set_attr "type" "ftoidfp")]) ; @@ -3751,7 +3982,7 @@ "TARGET_64BIT && TARGET_HARD_FLOAT" "c<xde>g<bt>r\t%0,%1" [(set_attr "op_type" "RRE") - (set_attr "type" "itof" )]) + (set_attr "type" "itof<mode>" )]) ; cxfbr, cdfbr, cefbr (define_insn "floatsi<mode>2" @@ -3760,7 +3991,7 @@ "TARGET_HARD_FLOAT" "c<xde>fbr\t%0,%1" [(set_attr "op_type" "RRE") - (set_attr "type" "itof" )]) + (set_attr "type" "itof<mode>" )]) ; @@ -3787,7 +4018,7 @@ "TARGET_HARD_FLOAT" "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" [(set_attr "length" "6") - (set_attr "type" "ftrunctf")]) + (set_attr "type" "ftrunctf")]) ; ; trunctddd2 and truncddsd2 instruction pattern(s). @@ -3800,7 +4031,7 @@ "TARGET_HARD_FLOAT && TARGET_HARD_DFP" "ldxtr\t%2,0,%1,0\;ldr\t%0,%2" [(set_attr "length" "6") - (set_attr "type" "ftrunctf")]) + (set_attr "type" "ftruncdd")]) (define_insn "truncddsd2" [(set (match_operand:SD 0 "register_operand" "=f") @@ -3808,7 +4039,7 @@ "TARGET_HARD_FLOAT && TARGET_HARD_DFP" "ledtr\t%0,0,%1,0" [(set_attr "op_type" "RRF") - (set_attr "type" "fsimptf")]) + (set_attr "type" "ftruncsd")]) ; ; extend(sf|df)(df|tf)2 instruction pattern(s). @@ -4045,7 +4276,8 @@ "@ algfr\t%0,%2 algf\t%0,%2" - [(set_attr "op_type" "RRE,RXY")]) + [(set_attr "op_type" "RRE,RXY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_insn "*adddi3_zero_cconly" [(set (reg CC_REGNUM) @@ -4057,7 +4289,8 @@ "@ algfr\t%0,%2 algf\t%0,%2" - [(set_attr "op_type" "RRE,RXY")]) + [(set_attr "op_type" "RRE,RXY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_insn "*adddi3_zero" [(set (match_operand:DI 0 "register_operand" "=d,d") @@ -4068,7 +4301,8 @@ "@ algfr\t%0,%2 algf\t%0,%2" - [(set_attr "op_type" "RRE,RXY")]) + [(set_attr "op_type" "RRE,RXY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_insn_and_split "*adddi3_31z" [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") @@ -4171,7 +4405,14 @@ a<y>\t%0,%2 a<g>si\t%0,%c2" [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY,SIY") - (set_attr "cpu_facility" "*,*,extimm,extimm,*,*,z10")]) + (set_attr "cpu_facility" "*,*,extimm,extimm,*,*,z10") + (set_attr "z10prop" "z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1")]) ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi (define_insn "*add<mode>3_carry1_cc" @@ -4190,7 +4431,13 @@ al<y>\t%0,%2 al<g>si\t%0,%c2" [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") - (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")]) + (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10") + (set_attr "z10prop" "z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1")]) ; alr, al, aly, algr, alg (define_insn "*add<mode>3_carry1_cconly" @@ -4204,7 +4451,8 @@ al<g>r\t%0,%2 al<g>\t%0,%2 al<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) + [(set_attr "op_type" "RR<E>,RX<Y>,RXY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi (define_insn "*add<mode>3_carry2_cc" @@ -4223,7 +4471,13 @@ al<y>\t%0,%2 al<g>si\t%0,%c2" [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") - (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")]) + (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10") + (set_attr "z10prop" "z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1")]) ; alr, al, aly, algr, alg (define_insn "*add<mode>3_carry2_cconly" @@ -4237,7 +4491,8 @@ al<g>r\t%0,%2 al<g>\t%0,%2 al<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) + [(set_attr "op_type" "RR<E>,RX<Y>,RXY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi (define_insn "*add<mode>3_cc" @@ -4256,7 +4511,13 @@ al<y>\t%0,%2 al<g>si\t%0,%c2" [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") - (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")]) + (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10") + (set_attr "z10prop" "z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1")]) ; alr, al, aly, algr, alg (define_insn "*add<mode>3_cconly" @@ -4270,7 +4531,8 @@ al<g>r\t%0,%2 al<g>\t%0,%2 al<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) + [(set_attr "op_type" "RR<E>,RX<Y>,RXY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) ; alr, al, aly, algr, alg (define_insn "*add<mode>3_cconly2" @@ -4283,7 +4545,8 @@ al<g>r\t%0,%2 al<g>\t%0,%2 al<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) + [(set_attr "op_type" "RR<E>,RX<Y>,RXY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) ; ahi, afi, aghi, agfi, asi, agsi (define_insn "*add<mode>3_imm_cc" @@ -4303,7 +4566,8 @@ a<g>fi\t%0,%2 a<g>si\t%0,%c2" [(set_attr "op_type" "RI,RIL,SIY") - (set_attr "cpu_facility" "*,extimm,z10")]) + (set_attr "cpu_facility" "*,extimm,z10") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) ; ; add(tf|df|sf|td|dd)3 instruction pattern(s). @@ -4320,7 +4584,7 @@ a<xde><bt>r\t%0,<op1>%2 a<xde>b\t%0,%2" [(set_attr "op_type" "<RRer>,RXE") - (set_attr "type" "fsimp<bfp>")]) + (set_attr "type" "fsimp<mode>")]) ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr (define_insn "*add<mode>3_cc" @@ -4335,7 +4599,7 @@ a<xde><bt>r\t%0,<op1>%2 a<xde>b\t%0,%2" [(set_attr "op_type" "<RRer>,RXE") - (set_attr "type" "fsimp<bfp>")]) + (set_attr "type" "fsimp<mode>")]) ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr (define_insn "*add<mode>3_cconly" @@ -4349,7 +4613,7 @@ a<xde><bt>r\t%0,<op1>%2 a<xde>b\t%0,%2" [(set_attr "op_type" "<RRer>,RXE") - (set_attr "type" "fsimp<bfp>")]) + (set_attr "type" "fsimp<mode>")]) ;; @@ -4406,7 +4670,8 @@ "@ sgfr\t%0,%2 sgf\t%0,%2" - [(set_attr "op_type" "RRE,RXY")]) + [(set_attr "op_type" "RRE,RXY") + (set_attr "z10prop" "z10_c,*")]) (define_insn "*subdi3_zero_cc" [(set (reg CC_REGNUM) @@ -4419,7 +4684,8 @@ "@ slgfr\t%0,%2 slgf\t%0,%2" - [(set_attr "op_type" "RRE,RXY")]) + [(set_attr "op_type" "RRE,RXY") + (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) (define_insn "*subdi3_zero_cconly" [(set (reg CC_REGNUM) @@ -4431,7 +4697,8 @@ "@ slgfr\t%0,%2 slgf\t%0,%2" - [(set_attr "op_type" "RRE,RXY")]) + [(set_attr "op_type" "RRE,RXY") + (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) (define_insn "*subdi3_zero" [(set (match_operand:DI 0 "register_operand" "=d,d") @@ -4442,7 +4709,8 @@ "@ slgfr\t%0,%2 slgf\t%0,%2" - [(set_attr "op_type" "RRE,RXY")]) + [(set_attr "op_type" "RRE,RXY") + (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) (define_insn_and_split "*subdi3_31z" [(set (match_operand:DI 0 "register_operand" "=&d") @@ -4539,7 +4807,8 @@ s<g>r\t%0,%2 s<g>\t%0,%2 s<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) + [(set_attr "op_type" "RR<E>,RX<Y>,RXY") + (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) ; slr, sl, sly, slgr, slg (define_insn "*sub<mode>3_borrow_cc" @@ -4554,7 +4823,8 @@ sl<g>r\t%0,%2 sl<g>\t%0,%2 sl<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) + [(set_attr "op_type" "RR<E>,RX<Y>,RXY") + (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) ; slr, sl, sly, slgr, slg (define_insn "*sub<mode>3_borrow_cconly" @@ -4568,7 +4838,8 @@ sl<g>r\t%0,%2 sl<g>\t%0,%2 sl<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) + [(set_attr "op_type" "RR<E>,RX<Y>,RXY") + (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) ; slr, sl, sly, slgr, slg (define_insn "*sub<mode>3_cc" @@ -4583,7 +4854,8 @@ sl<g>r\t%0,%2 sl<g>\t%0,%2 sl<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) + [(set_attr "op_type" "RR<E>,RX<Y>,RXY") + (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) ; slr, sl, sly, slgr, slg (define_insn "*sub<mode>3_cc2" @@ -4597,7 +4869,8 @@ sl<g>r\t%0,%2 sl<g>\t%0,%2 sl<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) + [(set_attr "op_type" "RR<E>,RX<Y>,RXY") + (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) ; slr, sl, sly, slgr, slg (define_insn "*sub<mode>3_cconly" @@ -4611,7 +4884,9 @@ sl<g>r\t%0,%2 sl<g>\t%0,%2 sl<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) + [(set_attr "op_type" "RR<E>,RX<Y>,RXY") + (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) + ; slr, sl, sly, slgr, slg (define_insn "*sub<mode>3_cconly2" @@ -4624,7 +4899,9 @@ sl<g>r\t%0,%2 sl<g>\t%0,%2 sl<y>\t%0,%2" - [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) + [(set_attr "op_type" "RR<E>,RX<Y>,RXY") + (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) + ; ; sub(tf|df|sf|td|dd)3 instruction pattern(s). @@ -4641,7 +4918,7 @@ s<xde><bt>r\t%0,<op1>%2 s<xde>b\t%0,%2" [(set_attr "op_type" "<RRer>,RXE") - (set_attr "type" "fsimp<bfp>")]) + (set_attr "type" "fsimp<mode>")]) ; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr (define_insn "*sub<mode>3_cc" @@ -4656,7 +4933,7 @@ s<xde><bt>r\t%0,<op1>%2 s<xde>b\t%0,%2" [(set_attr "op_type" "<RRer>,RXE") - (set_attr "type" "fsimp<bfp>")]) + (set_attr "type" "fsimp<mode>")]) ; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr (define_insn "*sub<mode>3_cconly" @@ -4670,7 +4947,7 @@ s<xde><bt>r\t%0,<op1>%2 s<xde>b\t%0,%2" [(set_attr "op_type" "<RRer>,RXE") - (set_attr "type" "fsimp<bfp>")]) + (set_attr "type" "fsimp<mode>")]) ;; @@ -4793,7 +5070,8 @@ "@ slb<g>r\t%0,%2 slb<g>\t%0,%2" - [(set_attr "op_type" "RRE,RXY")]) + [(set_attr "op_type" "RRE,RXY") + (set_attr "z10prop" "z10_c,*")]) ; slbr, slb, slbgr, slbg (define_insn "*sub<mode>3_slb" @@ -4806,7 +5084,8 @@ "@ slb<g>r\t%0,%2 slb<g>\t%0,%2" - [(set_attr "op_type" "RRE,RXY")]) + [(set_attr "op_type" "RRE,RXY") + (set_attr "z10prop" "z10_c,*")]) (define_expand "add<mode>cc" [(match_operand:GPR 0 "register_operand" "") @@ -4814,9 +5093,9 @@ (match_operand:GPR 2 "register_operand" "") (match_operand:GPR 3 "const_int_operand" "")] "TARGET_CPU_ZARCH" - "if (!s390_expand_addcc (GET_CODE (operands[1]), - s390_compare_op0, s390_compare_op1, - operands[0], operands[2], + "if (!s390_expand_addcc (GET_CODE (operands[1]), + s390_compare_op0, s390_compare_op1, + operands[0], operands[2], operands[3])) FAIL; DONE;") ; @@ -4872,7 +5151,7 @@ [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1))) (clobber (reg:CC CC_REGNUM))])] "" -{ +{ if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode) FAIL; operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1); @@ -4881,7 +5160,7 @@ (define_insn_and_split "*sne" [(set (match_operand:SI 0 "register_operand" "=d") - (ne:SI (match_operand:CCZ1 1 "register_operand" "0") + (ne:SI (match_operand:CCZ1 1 "register_operand" "0") (const_int 0))) (clobber (reg:CC CC_REGNUM))] "" @@ -4996,7 +5275,7 @@ ; mul(tf|df|sf|td|dd)3 instruction pattern(s). ; -; mxbr mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr +; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr (define_insn "mul<mode>3" [(set (match_operand:FP 0 "register_operand" "=f,f") (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") @@ -5006,9 +5285,9 @@ m<xdee><bt>r\t%0,<op1>%2 m<xdee>b\t%0,%2" [(set_attr "op_type" "<RRer>,RXE") - (set_attr "type" "fmul<bfp>")]) + (set_attr "type" "fmul<mode>")]) -; maxbr, madbr, maebr, maxb, madb, maeb +; madbr, maebr, maxb, madb, maeb (define_insn "*fmadd<mode>" [(set (match_operand:DSF 0 "register_operand" "=f,f") (plus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "%f,f") @@ -5466,7 +5745,7 @@ d<xde><bt>r\t%0,<op1>%2 d<xde>b\t%0,%2" [(set_attr "op_type" "<RRer>,RXE") - (set_attr "type" "fdiv<bfp>")]) + (set_attr "type" "fdiv<mode>")]) ;; @@ -5496,7 +5775,8 @@ "@ ngr\t%0,%2 ng\t%0,%2" - [(set_attr "op_type" "RRE,RXY")]) + [(set_attr "op_type" "RRE,RXY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_insn "*anddi3_cconly" [(set (reg CC_REGNUM) @@ -5510,7 +5790,8 @@ "@ ngr\t%0,%2 ng\t%0,%2" - [(set_attr "op_type" "RRE,RXY")]) + [(set_attr "op_type" "RRE,RXY") + (set_attr "z10prop" "z10_super_E1, z10_super_E1")]) (define_insn "*anddi3" [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q") @@ -5534,7 +5815,19 @@ # #" [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS") - (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,*,*,*")]) + (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,*,*,*") + (set_attr "z10prop" "*, + *, + z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + *, + *")]) (define_split [(set (match_operand:DI 0 "s_operand" "") @@ -5564,7 +5857,8 @@ nr\t%0,%2 n\t%0,%2 ny\t%0,%2" - [(set_attr "op_type" "RIL,RR,RX,RXY")]) + [(set_attr "op_type" "RIL,RR,RX,RXY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) (define_insn "*andsi3_cconly" [(set (reg CC_REGNUM) @@ -5580,7 +5874,8 @@ nr\t%0,%2 n\t%0,%2 ny\t%0,%2" - [(set_attr "op_type" "RIL,RR,RX,RXY")]) + [(set_attr "op_type" "RIL,RR,RX,RXY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) (define_insn "*andsi3_zarch" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") @@ -5601,7 +5896,17 @@ ny\t%0,%2 # #" - [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")]) + [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS") + (set_attr "z10prop" "*, + *, + z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + *, + *")]) (define_insn "*andsi3_esa" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") @@ -5614,7 +5919,9 @@ n\t%0,%2 # #" - [(set_attr "op_type" "RR,RX,SI,SS")]) + [(set_attr "op_type" "RR,RX,SI,SS") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) + (define_split [(set (match_operand:SI 0 "s_operand" "") @@ -5641,7 +5948,9 @@ nill\t%0,%x2 # #" - [(set_attr "op_type" "RR,RI,SI,SS")]) + [(set_attr "op_type" "RR,RI,SI,SS") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*") +]) (define_insn "*andhi3_esa" [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") @@ -5653,7 +5962,9 @@ nr\t%0,%2 # #" - [(set_attr "op_type" "RR,SI,SS")]) + [(set_attr "op_type" "RR,SI,SS") + (set_attr "z10prop" "z10_super_E1,*,*") +]) (define_split [(set (match_operand:HI 0 "s_operand" "") @@ -5681,7 +5992,8 @@ ni\t%S0,%b2 niy\t%S0,%b2 #" - [(set_attr "op_type" "RR,RI,SI,SIY,SS")]) + [(set_attr "op_type" "RR,RI,SI,SIY,SS") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")]) (define_insn "*andqi3_esa" [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") @@ -5693,7 +6005,8 @@ nr\t%0,%2 ni\t%S0,%b2 #" - [(set_attr "op_type" "RR,SI,SS")]) + [(set_attr "op_type" "RR,SI,SS") + (set_attr "z10prop" "z10_super_E1,z10_super,*")]) ; ; Block and (NC) patterns. @@ -5742,7 +6055,7 @@ (clobber (reg:CC CC_REGNUM))])] "s390_offset_p (operands[0], operands[3], operands[2]) && s390_offset_p (operands[1], operands[4], operands[2]) - && !s390_overlap_p (operands[0], operands[1], + && !s390_overlap_p (operands[0], operands[1], INTVAL (operands[2]) + INTVAL (operands[5])) && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" [(parallel @@ -5781,7 +6094,8 @@ "@ ogr\t%0,%2 og\t%0,%2" - [(set_attr "op_type" "RRE,RXY")]) + [(set_attr "op_type" "RRE,RXY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_insn "*iordi3_cconly" [(set (reg CC_REGNUM) @@ -5793,7 +6107,8 @@ "@ ogr\t%0,%2 og\t%0,%2" - [(set_attr "op_type" "RRE,RXY")]) + [(set_attr "op_type" "RRE,RXY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_insn "*iordi3" [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") @@ -5814,7 +6129,17 @@ # #" [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS") - (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,*,*,*")]) + (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,*,*,*") + (set_attr "z10prop" "z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + *, + *")]) (define_split [(set (match_operand:DI 0 "s_operand" "") @@ -5843,7 +6168,8 @@ or\t%0,%2 o\t%0,%2 oy\t%0,%2" - [(set_attr "op_type" "RIL,RR,RX,RXY")]) + [(set_attr "op_type" "RIL,RR,RX,RXY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) (define_insn "*iorsi3_cconly" [(set (reg CC_REGNUM) @@ -5857,7 +6183,8 @@ or\t%0,%2 o\t%0,%2 oy\t%0,%2" - [(set_attr "op_type" "RIL,RR,RX,RXY")]) + [(set_attr "op_type" "RIL,RR,RX,RXY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) (define_insn "*iorsi3_zarch" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q") @@ -5874,7 +6201,15 @@ oy\t%0,%2 # #" - [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")]) + [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS") + (set_attr "z10prop" "z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + z10_super_E1, + *, + *")]) (define_insn "*iorsi3_esa" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") @@ -5887,7 +6222,8 @@ o\t%0,%2 # #" - [(set_attr "op_type" "RR,RX,SI,SS")]) + [(set_attr "op_type" "RR,RX,SI,SS") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) (define_split [(set (match_operand:SI 0 "s_operand" "") @@ -5914,7 +6250,8 @@ oill\t%0,%x2 # #" - [(set_attr "op_type" "RR,RI,SI,SS")]) + [(set_attr "op_type" "RR,RI,SI,SS") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) (define_insn "*iorhi3_esa" [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") @@ -5926,7 +6263,8 @@ or\t%0,%2 # #" - [(set_attr "op_type" "RR,SI,SS")]) + [(set_attr "op_type" "RR,SI,SS") + (set_attr "z10prop" "z10_super_E1,*,*")]) (define_split [(set (match_operand:HI 0 "s_operand" "") @@ -5954,7 +6292,8 @@ oi\t%S0,%b2 oiy\t%S0,%b2 #" - [(set_attr "op_type" "RR,RI,SI,SIY,SS")]) + [(set_attr "op_type" "RR,RI,SI,SIY,SS") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")]) (define_insn "*iorqi3_esa" [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") @@ -5966,7 +6305,8 @@ or\t%0,%2 oi\t%S0,%b2 #" - [(set_attr "op_type" "RR,SI,SS")]) + [(set_attr "op_type" "RR,SI,SS") + (set_attr "z10prop" "z10_super_E1,z10_super,*")]) ; ; Block inclusive or (OC) patterns. @@ -6015,7 +6355,7 @@ (clobber (reg:CC CC_REGNUM))])] "s390_offset_p (operands[0], operands[3], operands[2]) && s390_offset_p (operands[1], operands[4], operands[2]) - && !s390_overlap_p (operands[0], operands[1], + && !s390_overlap_p (operands[0], operands[1], INTVAL (operands[2]) + INTVAL (operands[5])) && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" [(parallel @@ -6054,7 +6394,8 @@ "@ xgr\t%0,%2 xg\t%0,%2" - [(set_attr "op_type" "RRE,RXY")]) + [(set_attr "op_type" "RRE,RXY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_insn "*xordi3_cconly" [(set (reg CC_REGNUM) @@ -6066,7 +6407,8 @@ "@ xgr\t%0,%2 xg\t%0,%2" - [(set_attr "op_type" "RRE,RXY")]) + [(set_attr "op_type" "RRE,RXY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) (define_insn "*xordi3" [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q") @@ -6082,7 +6424,8 @@ # #" [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS") - (set_attr "cpu_facility" "extimm,extimm,*,*,*,*")]) + (set_attr "cpu_facility" "extimm,extimm,*,*,*,*") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")]) (define_split [(set (match_operand:DI 0 "s_operand" "") @@ -6111,7 +6454,8 @@ xr\t%0,%2 x\t%0,%2 xy\t%0,%2" - [(set_attr "op_type" "RIL,RR,RX,RXY")]) + [(set_attr "op_type" "RIL,RR,RX,RXY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) (define_insn "*xorsi3_cconly" [(set (reg CC_REGNUM) @@ -6125,7 +6469,8 @@ xr\t%0,%2 x\t%0,%2 xy\t%0,%2" - [(set_attr "op_type" "RIL,RR,RX,RXY")]) + [(set_attr "op_type" "RIL,RR,RX,RXY") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) (define_insn "*xorsi3" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q") @@ -6140,7 +6485,8 @@ xy\t%0,%2 # #" - [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")]) + [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")]) (define_split [(set (match_operand:SI 0 "s_operand" "") @@ -6167,7 +6513,8 @@ xr\t%0,%2 # #" - [(set_attr "op_type" "RIL,RR,SI,SS")]) + [(set_attr "op_type" "RIL,RR,SI,SS") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) (define_split [(set (match_operand:HI 0 "s_operand" "") @@ -6195,7 +6542,9 @@ xi\t%S0,%b2 xiy\t%S0,%b2 #" - [(set_attr "op_type" "RIL,RR,SI,SIY,SS")]) + [(set_attr "op_type" "RIL,RR,SI,SIY,SS") + (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")]) + ; ; Block exclusive or (XC) patterns. @@ -6244,7 +6593,7 @@ (clobber (reg:CC CC_REGNUM))])] "s390_offset_p (operands[0], operands[3], operands[2]) && s390_offset_p (operands[1], operands[4], operands[2]) - && !s390_overlap_p (operands[0], operands[1], + && !s390_overlap_p (operands[0], operands[1], INTVAL (operands[2]) + INTVAL (operands[5])) && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" [(parallel @@ -6316,7 +6665,7 @@ "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" "lcgfr\t%0,%1" [(set_attr "op_type" "RRE")]) - + (define_insn "*negdi2_sign" [(set (match_operand:DI 0 "register_operand" "=d") (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) @@ -6334,7 +6683,8 @@ (neg:GPR (match_dup 1)))] "s390_match_ccmode (insn, CCAmode)" "lc<g>r\t%0,%1" - [(set_attr "op_type" "RR<E>")]) + [(set_attr "op_type" "RR<E>") + (set_attr "z10prop" "z10_super_c_E1")]) ; lcr, lcgr (define_insn "*neg<mode>2_cconly" @@ -6344,7 +6694,8 @@ (clobber (match_scratch:GPR 0 "=d"))] "s390_match_ccmode (insn, CCAmode)" "lc<g>r\t%0,%1" - [(set_attr "op_type" "RR<E>")]) + [(set_attr "op_type" "RR<E>") + (set_attr "z10prop" "z10_super_c_E1")]) ; lcr, lcgr (define_insn "*neg<mode>2" @@ -6353,7 +6704,8 @@ (clobber (reg:CC CC_REGNUM))] "" "lc<g>r\t%0,%1" - [(set_attr "op_type" "RR<E>")]) + [(set_attr "op_type" "RR<E>") + (set_attr "z10prop" "z10_super_c_E1")]) (define_insn_and_split "*negdi2_31" [(set (match_operand:DI 0 "register_operand" "=d") @@ -6425,7 +6777,7 @@ "TARGET_HARD_FLOAT && TARGET_DFP" "lcdfr\t%0,%1" [(set_attr "op_type" "RRE") - (set_attr "type" "fsimp<bfp>")]) + (set_attr "type" "fsimp<mode>")]) ; lcxbr, lcdbr, lcebr (define_insn "*neg<mode>2" @@ -6475,9 +6827,10 @@ (abs:GPR (match_dup 1)))] "s390_match_ccmode (insn, CCAmode)" "lp<g>r\t%0,%1" - [(set_attr "op_type" "RR<E>")]) + [(set_attr "op_type" "RR<E>") + (set_attr "z10prop" "z10_c")]) -; lpr, lpgr +; lpr, lpgr (define_insn "*abs<mode>2_cconly" [(set (reg CC_REGNUM) (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) @@ -6485,7 +6838,8 @@ (clobber (match_scratch:GPR 0 "=d"))] "s390_match_ccmode (insn, CCAmode)" "lp<g>r\t%0,%1" - [(set_attr "op_type" "RR<E>")]) + [(set_attr "op_type" "RR<E>") + (set_attr "z10prop" "z10_c")]) ; lpr, lpgr (define_insn "abs<mode>2" @@ -6494,7 +6848,8 @@ (clobber (reg:CC CC_REGNUM))] "" "lp<g>r\t%0,%1" - [(set_attr "op_type" "RR<E>")]) + [(set_attr "op_type" "RR<E>") + (set_attr "z10prop" "z10_c")]) ; ; abs(df|sf)2 instruction pattern(s). @@ -6538,7 +6893,7 @@ "TARGET_HARD_FLOAT && TARGET_DFP" "lpdfr\t%0,%1" [(set_attr "op_type" "RRE") - (set_attr "type" "fsimp<bfp>")]) + (set_attr "type" "fsimp<mode>")]) ; lpxbr, lpdbr, lpebr (define_insn "*abs<mode>2" @@ -6570,7 +6925,7 @@ "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" "lngfr\t%0,%1" [(set_attr "op_type" "RRE")]) - + (define_insn "*negabsdi2_sign" [(set (match_operand:DI 0 "register_operand" "=d") (neg:DI (abs:DI (sign_extend:DI @@ -6589,7 +6944,8 @@ (neg:GPR (abs:GPR (match_dup 1))))] "s390_match_ccmode (insn, CCAmode)" "ln<g>r\t%0,%1" - [(set_attr "op_type" "RR<E>")]) + [(set_attr "op_type" "RR<E>") + (set_attr "z10prop" "z10_c")]) ; lnr, lngr (define_insn "*negabs<mode>2_cconly" @@ -6599,7 +6955,8 @@ (clobber (match_scratch:GPR 0 "=d"))] "s390_match_ccmode (insn, CCAmode)" "ln<g>r\t%0,%1" - [(set_attr "op_type" "RR<E>")]) + [(set_attr "op_type" "RR<E>") + (set_attr "z10prop" "z10_c")]) ; lnr, lngr (define_insn "*negabs<mode>2" @@ -6608,7 +6965,8 @@ (clobber (reg:CC CC_REGNUM))] "" "ln<g>r\t%0,%1" - [(set_attr "op_type" "RR<E>")]) + [(set_attr "op_type" "RR<E>") + (set_attr "z10prop" "z10_c")]) ; ; Floating point @@ -6644,7 +7002,7 @@ "TARGET_HARD_FLOAT && TARGET_DFP" "lndfr\t%0,%1" [(set_attr "op_type" "RRE") - (set_attr "type" "fsimp<bfp>")]) + (set_attr "type" "fsimp<mode>")]) ; lnxbr, lndbr, lnebr (define_insn "*negabs<mode>2" @@ -6664,12 +7022,12 @@ (define_insn "copysign<mode>3" [(set (match_operand:FP 0 "register_operand" "=f") (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") - (match_operand:FP 2 "register_operand" "f")] + (match_operand:FP 2 "register_operand" "f")] UNSPEC_COPYSIGN))] "TARGET_HARD_FLOAT && TARGET_DFP" "cpsdr\t%0,%2,%1" [(set_attr "op_type" "RRF") - (set_attr "type" "fsimp<bfp>")]) + (set_attr "type" "fsimp<mode>")]) ;; ;;- Square root instructions. @@ -6679,7 +7037,7 @@ ; sqrt(df|sf)2 instruction pattern(s). ; -; sqxbr, sqdbr, sqebr, sqxb, sqdb, sqeb +; sqxbr, sqdbr, sqebr, sqdb, sqeb (define_insn "sqrt<mode>2" [(set (match_operand:BFP 0 "register_operand" "=f,f") (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))] @@ -6726,7 +7084,7 @@ emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); - insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); + insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); set_unique_reg_note (insn, REG_EQUAL, clz_equal); DONE; @@ -6735,16 +7093,16 @@ (define_insn "clztidi2" [(set (match_operand:TI 0 "register_operand" "=d") (ior:TI - (ashift:TI - (zero_extend:TI + (ashift:TI + (zero_extend:TI (xor:DI (match_operand:DI 1 "register_operand" "d") (lshiftrt (match_operand:DI 2 "const_int_operand" "") (subreg:SI (clz:DI (match_dup 1)) 4)))) - + (const_int 64)) (zero_extend:TI (clz:DI (match_dup 1))))) (clobber (reg:CC CC_REGNUM))] - "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) + "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) == (unsigned HOST_WIDE_INT) 1 << 63 && TARGET_EXTIMM && TARGET_64BIT" "flogr\t%0,%1" @@ -6767,7 +7125,8 @@ "TARGET_CPU_ZARCH" "rll<g>\t%0,%1,%Y2" [(set_attr "op_type" "RSE") - (set_attr "atype" "reg")]) + (set_attr "atype" "reg") + (set_attr "z10prop" "z10_super_E1")]) ; rll, rllg (define_insn "*rotl<mode>3_and" @@ -6778,7 +7137,8 @@ "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63" "rll<g>\t%0,%1,%Y2" [(set_attr "op_type" "RSE") - (set_attr "atype" "reg")]) + (set_attr "atype" "reg") + (set_attr "z10prop" "z10_super_E1")]) ;; @@ -6814,7 +7174,8 @@ "" "s<lr>l<g>\t%0,<1>%Y2" [(set_attr "op_type" "RS<E>") - (set_attr "atype" "reg")]) + (set_attr "atype" "reg") + (set_attr "z10prop" "z10_super_E1")]) ; sldl, srdl (define_insn "*<shift>di3_31_and" @@ -6836,7 +7197,8 @@ "(INTVAL (operands[3]) & 63) == 63" "s<lr>l<g>\t%0,<1>%Y2" [(set_attr "op_type" "RS<E>") - (set_attr "atype" "reg")]) + (set_attr "atype" "reg") + (set_attr "z10prop" "z10_super_E1")]) ; ; ashr(di|si)3 instruction pattern(s). @@ -6895,7 +7257,8 @@ "s390_match_ccmode(insn, CCSmode)" "sra<g>\t%0,<1>%Y2" [(set_attr "op_type" "RS<E>") - (set_attr "atype" "reg")]) + (set_attr "atype" "reg") + (set_attr "z10prop" "z10_super_E1")]) ; sra, srag (define_insn "*ashr<mode>3_cconly" @@ -6907,7 +7270,8 @@ "s390_match_ccmode(insn, CCSmode)" "sra<g>\t%0,<1>%Y2" [(set_attr "op_type" "RS<E>") - (set_attr "atype" "reg")]) + (set_attr "atype" "reg") + (set_attr "z10prop" "z10_super_E1")]) ; sra, srag (define_insn "*ashr<mode>3" @@ -6918,7 +7282,8 @@ "" "sra<g>\t%0,<1>%Y2" [(set_attr "op_type" "RS<E>") - (set_attr "atype" "reg")]) + (set_attr "atype" "reg") + (set_attr "z10prop" "z10_super_E1")]) ; shift pattern with implicit ANDs @@ -6973,7 +7338,8 @@ "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" "sra<g>\t%0,<1>%Y2" [(set_attr "op_type" "RS<E>") - (set_attr "atype" "reg")]) + (set_attr "atype" "reg") + (set_attr "z10prop" "z10_super_E1")]) ; sra, srag (define_insn "*ashr<mode>3_cconly_and" @@ -6986,7 +7352,8 @@ "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" "sra<g>\t%0,<1>%Y2" [(set_attr "op_type" "RS<E>") - (set_attr "atype" "reg")]) + (set_attr "atype" "reg") + (set_attr "z10prop" "z10_super_E1")]) ; sra, srag (define_insn "*ashr<mode>3_and" @@ -6998,7 +7365,8 @@ "(INTVAL (operands[3]) & 63) == 63" "sra<g>\t%0,<1>%Y2" [(set_attr "op_type" "RS<E>") - (set_attr "atype" "reg")]) + (set_attr "atype" "reg") + (set_attr "z10prop" "z10_super_E1")]) ;; @@ -7158,7 +7526,7 @@ "" { if (operands[1] != const0_rtx) FAIL; - operands[0] = s390_emit_compare (GET_CODE (operands[0]), + operands[0] = s390_emit_compare (GET_CODE (operands[0]), s390_compare_op0, s390_compare_op1); }) @@ -7181,7 +7549,8 @@ c<g>rt%C0\t%1,%2 c<g>it%C0\t%1,%h2" [(set_attr "op_type" "RRF,RIE") - (set_attr "type" "branch")]) + (set_attr "type" "branch") + (set_attr "z10prop" "z10_c,*")]) ; clrt, clgrt, clfit, clgit (define_insn "*cmp_and_trap_unsigned_int<mode>" @@ -7194,7 +7563,8 @@ cl<g>rt%C0\t%1,%2 cl<gf>it%C0\t%1,%x2" [(set_attr "op_type" "RRF,RIE") - (set_attr "type" "branch")]) + (set_attr "type" "branch") + (set_attr "z10prop" "z10_c,*")]) ;; ;;- Loop instructions. @@ -7256,6 +7626,9 @@ (pc)))] "" [(set_attr "op_type" "RI") + ; Strictly speaking, the z10 properties are valid for brct only, however, it does not + ; hurt us in the (rare) case of ahi. + (set_attr "z10prop" "z10_super") (set_attr "type" "branch") (set (attr "length") (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) @@ -7295,6 +7668,9 @@ (pc)))] "" [(set_attr "op_type" "RI") + ; Strictly speaking, the z10 properties are valid for brct only, however, it does not + ; hurt us in the (rare) case of ahi. + (set_attr "z10prop" "z10_super") (set_attr "type" "branch") (set (attr "length") (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) @@ -7361,6 +7737,9 @@ (pc)))] "" [(set_attr "op_type" "RI") + ; Strictly speaking, the z10 properties are valid for brct only, however, it does not + ; hurt us in the (rare) case of ahi. + (set_attr "z10prop" "z10_super") (set_attr "type" "branch") (set (attr "length") (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) @@ -7427,7 +7806,8 @@ (if_then_else (match_operand 0 "register_operand" "") (const_string "RR") (const_string "RX"))) (set_attr "type" "branch") - (set_attr "atype" "agen")]) + (set_attr "atype" "agen") + (set_attr "z10prop" "z10_super")]) ; ; casesi instruction pattern(s). @@ -7770,7 +8150,8 @@ UNSPEC_TLS_LOAD))] "TARGET_64BIT" "lg\t%0,%1%J2" - [(set_attr "op_type" "RXE")]) + [(set_attr "op_type" "RXE") + (set_attr "z10prop" "z10_fwd_A3")]) (define_insn "*tls_load_31" [(set (match_operand:SI 0 "register_operand" "=d,d") @@ -7781,7 +8162,8 @@ "@ l\t%0,%1%J2 ly\t%0,%1%J2" - [(set_attr "op_type" "RX,RXY")]) + [(set_attr "op_type" "RX,RXY") + (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) (define_insn "*bras_tls" [(set (match_operand 0 "" "") @@ -7851,6 +8233,8 @@ "" "bcr\t15,0" [(set_attr "op_type" "RR")]) +; Although bcr is superscalar on Z10, this variant will never become part of +; an execution group. ; ; compare and swap patterns. @@ -7883,7 +8267,7 @@ (set (reg:CCZ1 CC_REGNUM) (compare:CCZ1 (match_dup 1) (match_dup 2)))])] "" - "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], + "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2], operands[3]); DONE;") (define_expand "sync_compare_and_swap_cc<mode>" @@ -7936,7 +8320,7 @@ UNSPECV_CAS)) (set (reg:CCZ1 CC_REGNUM) (compare:CCZ1 (match_dup 1) (match_dup 2)))] - "" + "" "cs<g>\t%0,%3,%S1" [(set_attr "op_type" "RS<E>") (set_attr "type" "sem")]) @@ -7951,7 +8335,7 @@ (match_operand:HQI 1 "memory_operand") (match_operand:HQI 2 "general_operand")] "" - "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], + "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], operands[2], false); DONE;") (define_expand "sync_<atomic><mode>" @@ -7959,7 +8343,7 @@ (ATOMIC:HQI (match_dup 0) (match_operand:HQI 1 "general_operand")))] "" - "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], + "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], operands[1], false); DONE;") (define_expand "sync_old_<atomic><mode>" @@ -7969,16 +8353,16 @@ (ATOMIC:HQI (match_dup 1) (match_operand:HQI 2 "general_operand")))] "" - "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], + "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], operands[2], false); DONE;") (define_expand "sync_new_<atomic><mode>" [(set (match_operand:HQI 0 "register_operand") (ATOMIC:HQI (match_operand:HQI 1 "memory_operand") - (match_operand:HQI 2 "general_operand"))) + (match_operand:HQI 2 "general_operand"))) (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))] "" - "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], + "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], operands[2], true); DONE;") ;; @@ -8090,7 +8474,7 @@ if (TARGET_BACKCHAIN) temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode)); - + emit_move_insn (base, operand_subword (operands[1], 2, 0, mode)); emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode)); @@ -8178,7 +8562,8 @@ "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" "larl\t%0,%1" [(set_attr "op_type" "RIL") - (set_attr "type" "larl")]) + (set_attr "type" "larl") + (set_attr "z10prop" "z10_super_A1")]) (define_insn "main_pool" [(set (match_operand 0 "register_operand" "=a") @@ -8187,7 +8572,7 @@ { gcc_unreachable (); } - [(set (attr "type") + [(set (attr "type") (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) (const_string "larl") (const_string "la")))]) @@ -8205,7 +8590,8 @@ "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" "larl\t%0,%1" [(set_attr "op_type" "RIL") - (set_attr "type" "larl")]) + (set_attr "type" "larl") + (set_attr "z10prop" "z10_super_A1")]) (define_insn "pool" [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] @@ -8366,6 +8752,7 @@ instruction. */ return ""; - -} [(set_attr "type" "load,larl") - (set_attr "op_type" "RXY,RIL")]) +} + [(set_attr "type" "load,larl") + (set_attr "op_type" "RXY,RIL") + (set_attr "z10prop" "z10_super")]) |