re PR middle-end/91603 (Unaligned access in expand_assignment)

2019-09-03  Bernd Edlinger  <bernd.edlinger@hotmail.de>

        PR middle-end/91603
        PR middle-end/91612
        PR middle-end/91613
        * expr.c (expand_expr_real_1): Handle unaligned decl_rtl
        and SSA_NAME referring to CONSTANT_P correctly.

testsuite:
2019-09-03  Bernd Edlinger  <bernd.edlinger@hotmail.de>

        PR middle-end/91603
        * testsuite/gcc.target/arm/pr91603.c: New test.

From-SVN: r275342

4 files changed, 77 insertions, 4 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cf628e1..9c88006 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2019-09-03  Bernd Edlinger  <bernd.edlinger@hotmail.de>
+
+	PR middle-end/91603
+	PR middle-end/91612
+	PR middle-end/91613
+	* expr.c (expand_expr_real_1): Handle unaligned decl_rtl
+	and SSA_NAME referring to CONSTANT_P correctly.
+
 2019-09-03  Richard Biener  <rguenther@suse.de>
 
 	* tree-ssa-sccvn.h (vn_nary_op_lookup): Remove.
@@ -76,7 +84,7 @@
 	PR middle-end/91605
 	* expr.c (addr_expr_of_non_mem_decl_p_1): Refactor into...
 	(non_mem_decl_p): ...this.
-	(mem_ref_refers_to_non_mem_p): Handle DECL_P as well ase MEM_REF.
+	(mem_ref_refers_to_non_mem_p): Handle DECL_P as well as MEM_REF.
 	(expand_assignment): Call mem_ref_referes_to_non_mem_p
 	unconditionally as before.
 
diff --git a/gcc/expr.c b/gcc/expr.c
index 3c3f15a..0c96551 100644
--- a/gcc/expr.c
+++ b/gcc/expr.c
@@ -10062,6 +10062,42 @@ expand_expr_real_1 (tree exp, rtx target, machine_mode tmode,
 	{
 	  if (exp && MEM_P (temp) && REG_P (XEXP (temp, 0)))
 	    mark_reg_pointer (XEXP (temp, 0), DECL_ALIGN (exp));
+	}
+      else if (MEM_P (decl_rtl))
+	temp = decl_rtl;
+
+      if (temp != 0)
+	{
+	  if (MEM_P (temp)
+	      && modifier != EXPAND_WRITE
+	      && modifier != EXPAND_MEMORY
+	      && modifier != EXPAND_INITIALIZER
+	      && modifier != EXPAND_CONST_ADDRESS
+	      && modifier != EXPAND_SUM
+	      && !inner_reference_p
+	      && mode != BLKmode
+	      && MEM_ALIGN (temp) < GET_MODE_ALIGNMENT (mode))
+	    {
+	      enum insn_code icode;
+
+	      if ((icode = optab_handler (movmisalign_optab, mode))
+		  != CODE_FOR_nothing)
+		{
+		  class expand_operand ops[2];
+
+		  /* We've already validated the memory, and we're creating a
+		     new pseudo destination.  The predicates really can't fail,
+		     nor can the generator.  */
+		  create_output_operand (&ops[0], NULL_RTX, mode);
+		  create_fixed_operand (&ops[1], temp);
+		  expand_insn (icode, 2, ops);
+		  temp = ops[0].value;
+		}
+	      else if (targetm.slow_unaligned_access (mode, MEM_ALIGN (temp)))
+		temp = extract_bit_field (temp, GET_MODE_BITSIZE (mode),
+					  0, unsignedp, NULL_RTX,
+					  mode, mode, false, NULL);
+	    }
 
 	  return temp;
 	}
@@ -10974,9 +11010,10 @@ expand_expr_real_1 (tree exp, rtx target, machine_mode tmode,
 	  op0 = copy_rtx (op0);
 
 	/* Don't set memory attributes if the base expression is
-	   SSA_NAME that got expanded as a MEM.  In that case, we should
-	   just honor its original memory attributes.  */
-	if (TREE_CODE (tem) != SSA_NAME || !MEM_P (orig_op0))
+	   SSA_NAME that got expanded as a MEM or a CONSTANT.  In that case,
+	   we should just honor its original memory attributes.  */
+	if (!(TREE_CODE (tem) == SSA_NAME
+	      && (MEM_P (orig_op0) || CONSTANT_P (orig_op0))))
 	  set_mem_attributes (op0, exp, 0);
 
 	if (REG_P (XEXP (op0, 0)))
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 2771cd9..24e0d2b 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2019-09-03  Bernd Edlinger  <bernd.edlinger@hotmail.de>
+
+	PR middle-end/91603
+	* gcc.target/arm/pr91603.c: New test.
+
 2019-09-03  Ilya Leoshkevich  <iii@linux.ibm.com>
 
 	* gcc.target/s390/sigfpe-eh.c: New test.
diff --git a/gcc/testsuite/gcc.target/arm/pr91603.c b/gcc/testsuite/gcc.target/arm/pr91603.c
new file mode 100644
index 0000000..ab09c3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr91603.c
@@ -0,0 +1,23 @@
+/* { dg-do compile }  */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O3" } */
+/* { dg-add-options arm_neon } */
+
+typedef __simd64_int32_t int32x2_t;
+typedef __attribute__((aligned (1))) int32x2_t unalignedvec;
+
+unalignedvec a = {11, 13};
+
+void foo(unalignedvec *);
+
+void test()
+{
+  unalignedvec x = a;
+  foo (&x);
+  a = x;
+}
+
+/* { dg-final { scan-assembler-times "vld1.32" 1 } } */
+/* { dg-final { scan-assembler-times "vst1.32" 1 } } */
+/* { dg-final { scan-assembler-times "vldr" 1 } } */
+/* { dg-final { scan-assembler-times "vstr" 1 } } */