s390: Fix zero extend patterns using vlgv

In commit r16-2316-gc6676092318 mistakenly patterns were introduced
which actually should have been merged as alternatives to existing zero
extend patterns.

While on it, generalize the vec_extract patterns and also allow
registers for the index.  A subsequent patch will add
register+immediate support.

gcc/ChangeLog:

	* config/s390/s390.md: Merge movdi<mode>_zero_extend_A and
	movsi<mode>_zero_extend_A into zero_extendsidi2 and
	zero_extendhi<mode>2_z10 and
	zero_extend<HQI:mode><GPR:mode>2_extimm.
	* config/s390/vector.md (*movdi<mode>_zero_extend_A): Remove.
	(*movsi<mode>_zero_extend_A): Remove.
	(*movdi<mode>_zero_extend_B): Move to vec_extract patterns and
	rename to *vec_extract<mode>_zero_extend.
	(*movsi<mode>_zero_extend_B): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/s390/vector/vlgv-zero-extend-1.c: Require target
	s390_mvx.
	* gcc.target/s390/vector/vlgv-zero-extend-2.c: New test.

4 files changed, 98 insertions, 70 deletions

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 8cc48b0..858387c 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -5248,18 +5248,19 @@
 })
 
 (define_insn "*zero_extendsidi2"
-  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
-        (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))]
+  [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
+        (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b,v")))]
   "TARGET_ZARCH"
   "@
    llgfr\t%0,%1
    llgf\t%0,%1
-   llgfrl\t%0,%1"
-  [(set_attr "op_type"      "RRE,RXY,RIL")
-   (set_attr "type"         "*,*,larl")
-   (set_attr "cpu_facility" "*,*,z10")
-   (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")
-   (set_attr "relative_long" "*,*,yes")])
+   llgfrl\t%0,%1
+   vlgvf\t%0,%v1,0"
+  [(set_attr "op_type"      "RRE,RXY,RIL,VRS")
+   (set_attr "type"         "*,*,larl,*")
+   (set_attr "cpu_facility" "*,*,z10,vx")
+   (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3,*")
+   (set_attr "relative_long" "*,*,yes,*")])
 
 ;
 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
@@ -5362,29 +5363,32 @@
 
 ; llhrl, llghrl
 (define_insn "*zero_extendhi<mode>2_z10"
-  [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
-        (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b")))]
+  [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
+        (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b,v")))]
   "TARGET_Z10"
   "@
    ll<g>hr\t%0,%1
    ll<g>h\t%0,%1
-   ll<g>hrl\t%0,%1"
-  [(set_attr "op_type"      "RXY,RRE,RIL")
-   (set_attr "type"         "*,*,larl")
-   (set_attr "cpu_facility" "*,*,z10")
-   (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")
-   (set_attr "relative_long" "*,*,yes")])
+   ll<g>hrl\t%0,%1
+   vlgvh\t%0,%v1,0"
+  [(set_attr "op_type"      "RXY,RRE,RIL,VRS")
+   (set_attr "type"         "*,*,larl,*")
+   (set_attr "cpu_facility" "*,*,z10,vx")
+   (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3,*")
+   (set_attr "relative_long" "*,*,yes,*")])
 
 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
-  [(set (match_operand:GPR 0 "register_operand" "=d,d")
-        (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T")))]
+  [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
+        (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T,v")))]
   "TARGET_EXTIMM"
   "@
    ll<g><hc>r\t%0,%1
-   ll<g><hc>\t%0,%1"
-  [(set_attr "op_type" "RRE,RXY")
-   (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
+   ll<g><hc>\t%0,%1
+   vlgv<HQI:bhfgq>\t%0,%v1,0"
+  [(set_attr "op_type" "RRE,RXY,VRS")
+   (set_attr "cpu_facility" "*,*,vx")
+   (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,*")])
 
 ; llgh, llgc
 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 12bbeb6..745634e 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -501,54 +501,6 @@
                         SIL,SIL,RI,RI,RRE,RRE,RIL,RR,RXY,RXY,RIL")])
 
 
-; Instructions vlgvb, vlgvh, vlgvf zero all remaining bits of a GPR, i.e.,
-; an implicit zero extend is done.
-
-(define_insn "*movdi<mode>_zero_extend_A"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(zero_extend:DI (match_operand:SINT 1 "register_operand" "v")))]
-  "TARGET_VX"
-  "vlgv<bhfgq>\t%0,%v1,0"
-  [(set_attr "op_type" "VRS")])
-
-(define_insn "*movsi<mode>_zero_extend_A"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(zero_extend:SI (match_operand:HQI 1 "register_operand" "v")))]
-  "TARGET_VX"
-  "vlgv<bhfgq>\t%0,%v1,0"
-  [(set_attr "op_type" "VRS")])
-
-(define_mode_iterator VLGV_DI [V1QI V2QI V4QI V8QI V16QI
-			       V1HI V2HI V4HI V8HI
-			       V1SI V2SI V4SI])
-(define_insn "*movdi<mode>_zero_extend_B"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(zero_extend:DI (vec_select:<non_vec>
-			  (match_operand:VLGV_DI 1 "register_operand" "v")
-			  (parallel [(match_operand:SI 2 "const_int_operand" "n")]))))]
-  "TARGET_VX"
-{
-  operands[2] = GEN_INT (UINTVAL (operands[2]) & (GET_MODE_NUNITS (<MODE>mode) - 1));
-  return "vlgv<bhfgq>\t%0,%v1,%Y2";
-}
-  [(set_attr "op_type" "VRS")
-   (set_attr "mnemonic" "vlgv<bhfgq>")])
-
-(define_mode_iterator VLGV_SI [V1QI V2QI V4QI V8QI V16QI
-			       V1HI V2HI V4HI V8HI])
-(define_insn "*movsi<mode>_zero_extend_B"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(zero_extend:SI (vec_select:<non_vec>
-			  (match_operand:VLGV_SI 1 "register_operand" "v")
-			  (parallel [(match_operand:SI 2 "const_int_operand" "n")]))))]
-  "TARGET_VX"
-{
-  operands[2] = GEN_INT (UINTVAL (operands[2]) & (GET_MODE_NUNITS (<MODE>mode) - 1));
-  return "vlgv<bhfgq>\t%0,%v1,%Y2";
-}
-  [(set_attr "op_type" "VRS")
-   (set_attr "mnemonic" "vlgv<bhfgq>")])
-
 ; vec_load_lanes?
 
 ; vec_store_lanes?
@@ -763,6 +715,42 @@
   DONE;
 })
 
+; Instructions vlgvb, vlgvh, vlgvf zero all remaining bits of a GPR, i.e.,
+; an implicit zero extend is done.
+
+(define_mode_iterator VLGV_DI [V1QI V2QI V4QI V8QI V16QI
+			       V1HI V2HI V4HI V8HI
+			       V1SI V2SI V4SI])
+(define_insn "*vec_extract<mode>_zero_extend"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(zero_extend:DI (vec_select:<non_vec>
+			  (match_operand:VLGV_DI 1 "register_operand" "v")
+			  (parallel [(match_operand:SI 2 "nonmemory_operand" "an")]))))]
+  "TARGET_VX"
+{
+  if (CONST_INT_P (operands[2]))
+    operands[2] = GEN_INT (UINTVAL (operands[2]) & (GET_MODE_NUNITS (<MODE>mode) - 1));
+  return "vlgv<bhfgq>\t%0,%v1,%Y2";
+}
+  [(set_attr "op_type" "VRS")
+   (set_attr "mnemonic" "vlgv<bhfgq>")])
+
+(define_mode_iterator VLGV_SI [V1QI V2QI V4QI V8QI V16QI
+			       V1HI V2HI V4HI V8HI])
+(define_insn "*vec_extract<mode>_zero_extend"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(zero_extend:SI (vec_select:<non_vec>
+			  (match_operand:VLGV_SI 1 "register_operand" "v")
+			  (parallel [(match_operand:SI 2 "nonmemory_operand" "an")]))))]
+  "TARGET_VX"
+{
+  if (CONST_INT_P (operands[2]))
+    operands[2] = GEN_INT (UINTVAL (operands[2]) & (GET_MODE_NUNITS (<MODE>mode) - 1));
+  return "vlgv<bhfgq>\t%0,%v1,%Y2";
+}
+  [(set_attr "op_type" "VRS")
+   (set_attr "mnemonic" "vlgv<bhfgq>")])
+
 (define_insn "*vec_vllezlf<mode>"
   [(set (match_operand:V_HW_4              0 "register_operand" "=v")
 	(vec_concat:V_HW_4
diff --git a/gcc/testsuite/gcc.target/s390/vector/vlgv-zero-extend-1.c b/gcc/testsuite/gcc.target/s390/vector/vlgv-zero-extend-1.c
index 11df6c1..b2cb35f 100644
--- a/gcc/testsuite/gcc.target/s390/vector/vlgv-zero-extend-1.c
+++ b/gcc/testsuite/gcc.target/s390/vector/vlgv-zero-extend-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target s390_vx } */
+/* { dg-require-effective-target s390_mvx } */
 /* { dg-additional-options "-O2" } */
 /* { dg-final { scan-assembler-not {\tllg?[fhc]r\t} } } */
 
diff --git a/gcc/testsuite/gcc.target/s390/vector/vlgv-zero-extend-2.c b/gcc/testsuite/gcc.target/s390/vector/vlgv-zero-extend-2.c
new file mode 100644
index 0000000..9bace28
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/vlgv-zero-extend-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target s390_mvx } */
+/* { dg-additional-options "-O2" } */
+/* { dg-final { scan-assembler-not {\tllg?[fhc]r\t} } } */
+
+typedef unsigned char __attribute__ ((vector_size (1))) V1QI;
+typedef unsigned char __attribute__ ((vector_size (2))) V2QI;
+typedef unsigned char __attribute__ ((vector_size (4))) V4QI;
+typedef unsigned char __attribute__ ((vector_size (8))) V8QI;
+typedef unsigned char __attribute__ ((vector_size (16))) V16QI;
+
+typedef unsigned short __attribute__ ((vector_size (2))) V1HI;
+typedef unsigned short __attribute__ ((vector_size (4))) V2HI;
+typedef unsigned short __attribute__ ((vector_size (8))) V4HI;
+typedef unsigned short __attribute__ ((vector_size (16))) V8HI;
+
+typedef unsigned int __attribute__ ((vector_size (4))) V1SI;
+typedef unsigned int __attribute__ ((vector_size (8))) V2SI;
+typedef unsigned int __attribute__ ((vector_size (16))) V4SI;
+
+#define TEST(T, U) unsigned T test_ ## _ ## U (U x, int i) { return x[i]; }
+
+TEST (char, V1QI)
+TEST (char, V2QI)
+TEST (char, V4QI)
+TEST (char, V8QI)
+TEST (char, V16QI)
+
+TEST (short, V1HI)
+TEST (short, V2HI)
+TEST (short, V4HI)
+TEST (short, V8HI)
+
+TEST (int, V1SI)
+TEST (int, V2SI)
+TEST (int, V4SI)