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authorThomas Preud'homme <thomas.preudhomme@linaro.org>2018-10-31 10:05:54 +0000
committerThomas Preud'homme <thopre01@gcc.gnu.org>2018-10-31 10:05:54 +0000
commit6dc8ee419ea91a2641e35b7b00b81639f5bb4a8e (patch)
tree6c961f24d64d8d5e92316459ffdcfc5ac195e8d5
parent563cc649beaf11d707c422e5f4e9e5cdacb818c3 (diff)
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Fix PR87374: ICE with -mslow-flash-data and -mword-relocations
GCC ICEs under -mslow-flash-data and -mword-relocations because there is no way to load an address, both literal pools and MOVW/MOVT being forbidden. This patch gives an error message when both options are specified by the user and adds the according dg-skip-if directives for tests that use either of these options. It also explicitely set the option when in PIC mode as per documentation rather than always check for target_word_relocation together with flag_pic. 2018-10-31 Thomas Preud'homme <thomas.preudhomme@linaro.org> gcc/ PR target/87374 * config/arm/arm.c (arm_option_check_internal): Disable the combined use of -mslow-flash-data and -mword-relocations. (arm_option_override): Enable -mword-relocations if -fpic or -fPIC. * config/arm/arm.md (SYMBOL_REF MOVT splitter): Stop checking for flag_pic. * doc/invoke.texi (-mword-relocations): Mention conflict with -mslow-flash-data. (-mslow-flash-data): Reciprocally. gcc/testsuite/ PR target/87374 * gcc.target/arm/movdi_movt.c: Skip if both -mslow-flash-data and -mword-relocations would be passed when compiling the test. * gcc.target/arm/movsi_movt.c: Likewise. * gcc.target/arm/pr81863.c: Likewise. * gcc.target/arm/thumb2-slow-flash-data-1.c: Likewise. * gcc.target/arm/thumb2-slow-flash-data-2.c: Likewise. * gcc.target/arm/thumb2-slow-flash-data-3.c: Likewise. * gcc.target/arm/thumb2-slow-flash-data-4.c: Likewise. * gcc.target/arm/thumb2-slow-flash-data-5.c: Likewise. * gcc.target/arm/tls-disable-literal-pool.c: Likewise. From-SVN: r265662
-rw-r--r--gcc/ChangeLog12
-rw-r--r--gcc/config/arm/arm.c22
-rw-r--r--gcc/config/arm/arm.md2
-rw-r--r--gcc/doc/invoke.texi4
-rw-r--r--gcc/testsuite/ChangeLog14
-rw-r--r--gcc/testsuite/gcc.target/arm/movdi_movt.c1
-rw-r--r--gcc/testsuite/gcc.target/arm/movsi_movt.c1
-rw-r--r--gcc/testsuite/gcc.target/arm/pr81863.c1
-rw-r--r--gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-1.c1
-rw-r--r--gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-2.c1
-rw-r--r--gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-3.c1
-rw-r--r--gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-4.c1
-rw-r--r--gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-5.c1
-rw-r--r--gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c1
14 files changed, 53 insertions, 10 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1587a51..de50a8f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2018-10-31 Thomas Preud'homme <thomas.preudhomme@linaro.org>
+
+ PR target/87374
+ * config/arm/arm.c (arm_option_check_internal): Disable the combined
+ use of -mslow-flash-data and -mword-relocations.
+ (arm_option_override): Enable -mword-relocations if -fpic or -fPIC.
+ * config/arm/arm.md (SYMBOL_REF MOVT splitter): Stop checking for
+ flag_pic.
+ * doc/invoke.texi (-mword-relocations): Mention conflict with
+ -mslow-flash-data.
+ (-mslow-flash-data): Reciprocally.
+
2018-10-31 Richard Henderson <richard.henderson@linaro.org>
* config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Force
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 8810df5..8393f0b 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2893,17 +2893,22 @@ arm_option_check_internal (struct gcc_options *opts)
flag_pic = 0;
}
- /* We only support -mpure-code and -mslow-flash-data on M-profile targets
- with MOVT. */
- if ((target_pure_code || target_slow_flash_data)
- && (!TARGET_HAVE_MOVT || arm_arch_notm || flag_pic || TARGET_NEON))
+ if (target_pure_code || target_slow_flash_data)
{
const char *flag = (target_pure_code ? "-mpure-code" :
"-mslow-flash-data");
- error ("%s only supports non-pic code on M-profile targets with the "
- "MOVT instruction", flag);
- }
+ /* We only support -mpure-code and -mslow-flash-data on M-profile targets
+ with MOVT. */
+ if (!TARGET_HAVE_MOVT || arm_arch_notm || flag_pic || TARGET_NEON)
+ error ("%s only supports non-pic code on M-profile targets with the "
+ "MOVT instruction", flag);
+
+ /* Cannot load addresses: -mslow-flash-data forbids literal pool and
+ -mword-relocations forbids relocation of MOVT/MOVW. */
+ if (target_word_relocations)
+ error ("%s incompatible with -mword-relocations", flag);
+ }
}
/* Recompute the global settings depending on target attribute options. */
@@ -3489,6 +3494,9 @@ arm_option_override (void)
arm_pic_register = pic_register;
}
+ if (flag_pic)
+ target_word_relocations = 1;
+
/* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores. */
if (fix_cm3_ldrd == 2)
{
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 270b8e4..a773518 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -6128,7 +6128,7 @@
[(set (match_operand:SI 0 "arm_general_register_operand" "")
(match_operand:SI 1 "general_operand" ""))]
"TARGET_USE_MOVT && GET_CODE (operands[1]) == SYMBOL_REF
- && !flag_pic && !target_word_relocations
+ && !target_word_relocations
&& !arm_tls_referenced_p (operands[1])"
[(clobber (const_int 0))]
{
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 055e8c4..3d83bf5 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -17034,7 +17034,7 @@ this option and always use the original scheme.
Only generate absolute relocations on word-sized values (i.e. R_ARM_ABS32).
This is enabled by default on targets (uClinux, SymbianOS) where the runtime
loader imposes this restriction, and when @option{-fpic} or @option{-fPIC}
-is specified.
+is specified. This option conflicts with @option{-mslow-flash-data}.
@item -mfix-cortex-m3-ldrd
@opindex mfix-cortex-m3-ldrd
@@ -17071,7 +17071,7 @@ to Neon is high.
Assume loading data from flash is slower than fetching instruction.
Therefore literal load is minimized for better performance.
This option is only supported when compiling for ARMv7 M-profile and
-off by default.
+off by default. It conflicts with @option{-mword-relocations}.
@item -masm-syntax-unified
@opindex masm-syntax-unified
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 4ca1d26..74e1ece 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,17 @@
+2018-10-31 Thomas Preud'homme <thomas.preudhomme@linaro.org>
+
+ PR target/87374
+ * gcc.target/arm/movdi_movt.c: Skip if both -mslow-flash-data and
+ -mword-relocations would be passed when compiling the test.
+ * gcc.target/arm/movsi_movt.c: Likewise.
+ * gcc.target/arm/pr81863.c: Likewise.
+ * gcc.target/arm/thumb2-slow-flash-data-1.c: Likewise.
+ * gcc.target/arm/thumb2-slow-flash-data-2.c: Likewise.
+ * gcc.target/arm/thumb2-slow-flash-data-3.c: Likewise.
+ * gcc.target/arm/thumb2-slow-flash-data-4.c: Likewise.
+ * gcc.target/arm/thumb2-slow-flash-data-5.c: Likewise.
+ * gcc.target/arm/tls-disable-literal-pool.c: Likewise.
+
2018-10-31 Richard Biener <rguenther@suse.de>
PR testsuite/87802
diff --git a/gcc/testsuite/gcc.target/arm/movdi_movt.c b/gcc/testsuite/gcc.target/arm/movdi_movt.c
index e2a28cc..a01ffa0 100644
--- a/gcc/testsuite/gcc.target/arm/movdi_movt.c
+++ b/gcc/testsuite/gcc.target/arm/movdi_movt.c
@@ -1,4 +1,5 @@
/* { dg-do compile { target { arm_cortex_m && { arm_thumb2_ok || arm_thumb1_movt_ok } } } } */
+/* { dg-skip-if "-mslow-flash-data and -mword-relocations incompatible" { *-*-* } { "-mword-relocations" } } */
/* { dg-options "-O2 -mslow-flash-data" } */
unsigned long long
diff --git a/gcc/testsuite/gcc.target/arm/movsi_movt.c b/gcc/testsuite/gcc.target/arm/movsi_movt.c
index 3cf46e2..19d202e 100644
--- a/gcc/testsuite/gcc.target/arm/movsi_movt.c
+++ b/gcc/testsuite/gcc.target/arm/movsi_movt.c
@@ -1,4 +1,5 @@
/* { dg-do compile { target { arm_cortex_m && { arm_thumb2_ok || arm_thumb1_movt_ok } } } } */
+/* { dg-skip-if "-mslow-flash-data and -mword-relocations incompatible" { *-*-* } { "-mword-relocations" } } */
/* { dg-options "-O2 -mslow-flash-data" } */
unsigned
diff --git a/gcc/testsuite/gcc.target/arm/pr81863.c b/gcc/testsuite/gcc.target/arm/pr81863.c
index 63b1ed6..225a0c5cc 100644
--- a/gcc/testsuite/gcc.target/arm/pr81863.c
+++ b/gcc/testsuite/gcc.target/arm/pr81863.c
@@ -1,5 +1,6 @@
/* testsuite/gcc.target/arm/pr48183.c */
/* { dg-do compile } */
+/* { dg-skip-if "-mslow-flash-data and -mword-relocations incompatible" { *-*-* } { "-mslow-flash-data" } } */
/* { dg-options "-O2 -mword-relocations -march=armv7-a -marm" } */
/* { dg-final { scan-assembler-not "\[\\t \]+movw" } } */
diff --git a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-1.c b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-1.c
index 089a72b..d10391a 100644
--- a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-1.c
+++ b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-1.c
@@ -6,6 +6,7 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_cortex_m } */
/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-skip-if "-mslow-flash-data and -mword-relocations incompatible" { *-*-* } { "-mword-relocations" } } */
/* { dg-options "-O2 -mthumb -mslow-flash-data" } */
float sf;
diff --git a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-2.c b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-2.c
index c87e050..90bd44e 100644
--- a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-2.c
+++ b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-2.c
@@ -3,6 +3,7 @@
/* { dg-require-effective-target arm_thumb2_ok } */
/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-m4" "-mcpu=cortex-m7" } } */
/* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
+/* { dg-skip-if "-mslow-flash-data and -mword-relocations incompatible" { *-*-* } { "-mword-relocations" } } */
/* { dg-options "-march=armv7e-m+fp -mfloat-abi=hard -O2 -mthumb -mslow-flash-data" } */
float f (float);
diff --git a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-3.c b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-3.c
index 8c6210e..5d9cd9c 100644
--- a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-3.c
+++ b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-3.c
@@ -3,6 +3,7 @@
/* { dg-require-effective-target arm_thumb2_ok } */
/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-m4" "-mcpu=cortex-m7" } } */
/* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
+/* { dg-skip-if "-mslow-flash-data and -mword-relocations incompatible" { *-*-* } { "-mword-relocations" } } */
/* { dg-options "-march=armv7e-m+fp -mfloat-abi=hard -mthumb -mslow-flash-data" } */
/* From PR71607 */
diff --git a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-4.c b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-4.c
index 1bcb692..0eeddd5 100644
--- a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-4.c
+++ b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-4.c
@@ -3,6 +3,7 @@
/* { dg-require-effective-target arm_thumb2_ok } */
/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-m4" "-mcpu=cortex-m7" } } */
/* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
+/* { dg-skip-if "-mslow-flash-data and -mword-relocations incompatible" { *-*-* } { "-mword-relocations" } } */
/* { dg-options "-march=armv7e-m+fp -mfloat-abi=hard -O2 -mthumb -mslow-flash-data" } */
double __attribute__ ((target ("fpu=fpv5-d16")))
diff --git a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-5.c b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-5.c
index 808fff0..7d52f38 100644
--- a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-5.c
+++ b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-5.c
@@ -3,6 +3,7 @@
/* { dg-require-effective-target arm_thumb2_ok } */
/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-m4" "-mcpu=cortex-m7" } } */
/* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
+/* { dg-skip-if "-mslow-flash-data and -mword-relocations incompatible" { *-*-* } { "-mword-relocations" } } */
/* { dg-options "-march=armv7e-m+fp -mfloat-abi=hard -O2 -mthumb -mslow-flash-data" } */
double __attribute__ ((target ("fpu=fpv5-sp-d16")))
diff --git a/gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c b/gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c
index 283201f..834eaf6 100644
--- a/gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c
+++ b/gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c
@@ -2,6 +2,7 @@
/* { dg-require-effective-target tls_native } */
/* { dg-require-effective-target arm_cortex_m } */
/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-skip-if "-mslow-flash-data and -mword-relocations incompatible" { *-*-* } { "-mword-relocations" } } */
/* { dg-options "-mslow-flash-data" } */
__thread int x = 0;