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| author | Andre Simoes Dias Vieira <andre.simoesdiasvieira@arm.com> | 2020-06-23 15:20:17 +0100 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2020-06-23 15:23:45 +0100 |
| commit | 5f426554fd804d65509875d706d8b8bc3a48393b (patch) | |
| tree | e2330b45686cc4b2100d1ad9df6cd9e4ae34f813 | |
| parent | b81d4f1e3d6a519afa20d84304f12ee639fde944 (diff) | |
| download | gcc-5f426554fd804d65509875d706d8b8bc3a48393b.zip gcc-5f426554fd804d65509875d706d8b8bc3a48393b.tar.gz gcc-5f426554fd804d65509875d706d8b8bc3a48393b.tar.bz2 | |
arm: PR target/95646: Do not clobber callee saved registers with CMSE
As reported in bugzilla when the -mcmse option is used while compiling for size
(-Os) with a thumb-1 target the generated code will clear the registers r7-r10.
These however are callee saved and should be preserved accross ABI boundaries.
The reason this happens is because these registers are made "fixed" when
optimising for size with Thumb-1 in a way to make sure they are not used, as
pushing and popping hi-registers requires extra moves to and from LO_REGS.
To fix this, this patch uses 'callee_saved_reg_p', which accounts for this
optimisation, instead of 'call_used_or_fixed_reg_p'. Be aware of
'callee_saved_reg_p''s definition, as it does still take call used registers
into account, which aren't callee_saved in my opinion, so it is a rather
misnoemer, works in our advantage here though as it does exactly what we need.
Regression tested on arm-none-eabi.
Is this OK for trunk? (Will eventually backport to previous versions if stable.)
gcc/ChangeLog:
2020-06-19 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR target/95646
* config/arm/arm.c: (cmse_nonsecure_entry_clear_before_return): Use
'callee_saved_reg_p' instead of 'calL_used_or_fixed_reg_p'.
gcc/testsuite/ChangeLog:
2020-06-19 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR target/95646
* gcc.target/arm/pr95646.c: New test.
| -rw-r--r-- | gcc/config/arm/arm.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/pr95646.c | 32 |
2 files changed, 33 insertions, 1 deletions
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 6b7ca82..dac9a6f 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -26960,7 +26960,7 @@ cmse_nonsecure_entry_clear_before_return (void) continue; if (IN_RANGE (regno, IP_REGNUM, PC_REGNUM)) continue; - if (call_used_or_fixed_reg_p (regno) + if (!callee_saved_reg_p (regno) && (!IN_RANGE (regno, FIRST_VFP_REGNUM, LAST_VFP_REGNUM) || TARGET_HARD_FLOAT)) bitmap_set_bit (to_clear_bitmap, regno); diff --git a/gcc/testsuite/gcc.target/arm/pr95646.c b/gcc/testsuite/gcc.target/arm/pr95646.c new file mode 100644 index 0000000..12d06a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr95646.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv8-m.base" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-m23" } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mfpu=*" } { } } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=soft" } } */ +/* { dg-options "-mcpu=cortex-m23 -mcmse" } */ +/* { dg-additional-options "-Os" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +int __attribute__ ((cmse_nonsecure_entry)) +foo (void) +{ + return 1; +} +/* { { dg-final { scan-assembler-not "mov\tr9, r0" } } */ + +/* +** __acle_se_bar: +** mov (r[0-3]), r9 +** push {\1} +** ... +** pop {(r[0-3])} +** mov r9, \2 +** ... +** bxns lr +*/ +int __attribute__ ((cmse_nonsecure_entry)) +bar (void) +{ + asm ("": : : "r9"); + return 1; +} |