diff options
| author | Aaron Sawdey <acsawdey@linux.ibm.com> | 2018-04-16 14:50:06 +0000 |
|---|---|---|
| committer | Aaron Sawdey <acsawdey@gcc.gnu.org> | 2018-04-16 09:50:06 -0500 |
| commit | 2d4e0a12089d6bfe5079df70f0618c925bee79e8 (patch) | |
| tree | d183ea52381e8389b365b6b1a32314ff290486b1 | |
| parent | af7a5758bf250decdba7b366068af186f32a52b5 (diff) | |
| download | gcc-2d4e0a12089d6bfe5079df70f0618c925bee79e8.zip gcc-2d4e0a12089d6bfe5079df70f0618c925bee79e8.tar.gz gcc-2d4e0a12089d6bfe5079df70f0618c925bee79e8.tar.bz2 | |
re PR target/83660 (ICE with vec_extract inside expression statement)
2018-04-16 Aaron Sawdey <acsawdey@linux.ibm.com>
PR target/83660
* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Mark
vec_extract expression as having side effects to make sure it gets
a cleanup point.
2018-04-16 Aaron Sawdey <acsawdey@linux.ibm.com>
PR target/83660
* gcc.target/powerpc/pr83660.C: New test.
From-SVN: r259403
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000-c.c | 9 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/pr83660.C | 14 |
4 files changed, 36 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b53fda6..c3ea8d62 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2018-04-16 Aaron Sawdey <acsawdey@linux.ibm.com> + + PR target/83660 + * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Mark + vec_extract expression as having side effects to make sure it gets + a cleanup point. + 2018-04-16 H.J. Lu <hongjiu.lu@intel.com> PR target/85403 @@ -20,7 +27,7 @@ PROCESSOR_SKYLAKE-AVX512. * gcc/config/i386/i386.h (processor_costs): Define TARGET_SKYLAKE. (processor_type): Add PROCESSOR_SKYLAKE. - + 2018-04-16 Paolo Carlini <paolo.carlini@oracle.com> Jason Merrill <jason@redhat.com> diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index b9b4671..bdf6405 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -6705,6 +6705,15 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1); stmt = build_indirect_ref (loc, stmt, RO_NULL); + /* PR83660: We mark this as having side effects so that + downstream in fold_build_cleanup_point_expr () it will get a + CLEANUP_POINT_EXPR. If it does not we can run into an ICE + later in gimplify_cleanup_point_expr (). Potentially this + causes missed optimization because the actually is no side + effect. */ + if (c_dialect_cxx ()) + TREE_SIDE_EFFECTS (stmt) = 1; + return stmt; } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 415994e..77e6737 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-04-16 Aaron Sawdey <acsawdey@linux.ibm.com> + + PR target/83660 + * gcc.target/powerpc/pr83660.C: New test. + 2018-04-16 H.J. Lu <hongjiu.lu@intel.com> PR target/85403 diff --git a/gcc/testsuite/gcc.target/powerpc/pr83660.C b/gcc/testsuite/gcc.target/powerpc/pr83660.C new file mode 100644 index 0000000..f3e5373 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr83660.C @@ -0,0 +1,14 @@ +/* PR target/83660 */ +/* { dg-do compile } */ +/* { dg-options "-mcpu=power7" } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ + +#include <altivec.h> + +typedef __vector unsigned int uvec32_t __attribute__((__aligned__(16))); + +unsigned get_word(uvec32_t v) +{ + return ({const unsigned _B1 = 32; + vec_extract((uvec32_t)v, 2);}); +} |