diff options
| author | Andre Vieira <avieira@gcc.gnu.org> | 2018-05-30 15:59:14 +0000 |
|---|---|---|
| committer | Andre Vieira <avieira@gcc.gnu.org> | 2018-05-30 15:59:14 +0000 |
| commit | 0c8e76210a1b7272b468691312f4e47028fd610d (patch) | |
| tree | da096dd888253589b22c7a2a1be2d2108b76c2f0 | |
| parent | 7ce4ce10cd0a6f332dd473bd4726f1a1adefda0e (diff) | |
| download | gcc-0c8e76210a1b7272b468691312f4e47028fd610d.zip gcc-0c8e76210a1b7272b468691312f4e47028fd610d.tar.gz gcc-0c8e76210a1b7272b468691312f4e47028fd610d.tar.bz2 | |
Reverting r260635
gcc
2018-05-30 Andre Vieira <andre.simoesdiasvieira@arm.com>
2018-05-24 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR target/83009
Revert:
* config/aarch64/predicates.md (aarch64_mem_pair_lanes_operand): Make
address check not strict.
gcc/testsuite
2018-05-30 Andre Vieira <andre.simoesdiasvieira@arm.com>
2018-05-24 Andre Vieira <andre.simoesdiasvieira@arm.com>
Revert
PR target/83009
* gcc/target/aarch64/store_v2vec_lanes.c: Add extra tests.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@260635 138bc75d-0d04-0410-961f-82ee72b054a4
From-SVN: r260957
| -rw-r--r-- | gcc/config/aarch64/predicates.md | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/store_v2vec_lanes.c | 28 |
2 files changed, 4 insertions, 26 deletions
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 4814b93..7aec76d 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -226,7 +226,7 @@ ;; as a 128-bit vec_concat. (define_predicate "aarch64_mem_pair_lanes_operand" (and (match_code "mem") - (match_test "aarch64_legitimate_address_p (DFmode, XEXP (op, 0), false, + (match_test "aarch64_legitimate_address_p (DFmode, XEXP (op, 0), 1, ADDR_QUERY_LDP_STP)"))) (define_predicate "aarch64_prefetch_operand" diff --git a/gcc/testsuite/gcc.target/aarch64/store_v2vec_lanes.c b/gcc/testsuite/gcc.target/aarch64/store_v2vec_lanes.c index 3296d04..990aea3 100644 --- a/gcc/testsuite/gcc.target/aarch64/store_v2vec_lanes.c +++ b/gcc/testsuite/gcc.target/aarch64/store_v2vec_lanes.c @@ -22,32 +22,10 @@ construct_lane_2 (long long *y, v2di *z) z[2] = x; } -void -construct_lane_3 (double **py, v2df **pz) -{ - double *y = *py; - v2df *z = *pz; - double y0 = y[0] + 1; - double y1 = y[1] + 2; - v2df x = {y0, y1}; - z[2] = x; -} - -void -construct_lane_4 (long long **py, v2di **pz) -{ - long long *y = *py; - v2di *z = *pz; - long long y0 = y[0] + 1; - long long y1 = y[1] + 2; - v2di x = {y0, y1}; - z[2] = x; -} - /* We can use the load_pair_lanes<mode> pattern to vec_concat two DI/DF values from consecutive memory into a 2-element vector by using a Q-reg LDR. */ -/* { dg-final { scan-assembler-times "stp\td\[0-9\]+, d\[0-9\]+" 2 } } */ -/* { dg-final { scan-assembler-times "stp\tx\[0-9\]+, x\[0-9\]+" 2 } } */ -/* { dg-final { scan-assembler-not "ins\t" } } */ +/* { dg-final { scan-assembler-times "stp\td\[0-9\]+, d\[0-9\]+" 1 { xfail ilp32 } } } */ +/* { dg-final { scan-assembler-times "stp\tx\[0-9\]+, x\[0-9\]+" 1 { xfail ilp32 } } } */ +/* { dg-final { scan-assembler-not "ins\t" { xfail ilp32 } } } */ |