diff options
| author | Paul A. Clarke <pc@us.ibm.com> | 2019-07-23 02:54:28 +0000 |
|---|---|---|
| committer | Paul Clarke <pc@gcc.gnu.org> | 2019-07-23 02:54:28 +0000 |
| commit | 0ac608a2cb5ddbc636b8bc1983f136db1f7a7ace (patch) | |
| tree | cb2a07ef89c97c7518641721fc780b7e811f317a | |
| parent | ffbb9818b0efd04bff65c372e3e9444fae634363 (diff) | |
| download | gcc-0ac608a2cb5ddbc636b8bc1983f136db1f7a7ace.zip gcc-0ac608a2cb5ddbc636b8bc1983f136db1f7a7ace.tar.gz gcc-0ac608a2cb5ddbc636b8bc1983f136db1f7a7ace.tar.bz2 | |
[rs6000] Add documentation for __builtin_mtfsf
2019-07-22 Paul A. Clarke <pc@us.ibm.com>
[gcc]
* doc/extend.texi (Basic PowerPC Built-in Functions Available on all
Configurations): Add documentation for __builtin_mtfsf.
From-SVN: r273715
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/doc/extend.texi | 6 |
2 files changed, 10 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fd00041..f4bb577 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2019-07-22 Paul A. Clarke <pc@us.ibm.com> + + * doc/extend.texi (Basic PowerPC Built-in Functions Available on all + Configurations): Add documentation for __builtin_mtfsf. + 2019-07-22 Ilia Diachkov <ilia.diachkov@optimitech.com> * config/riscv/riscv-opts.h (struct riscv_align_data): New. diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 0616074..14b232b 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -16848,6 +16848,7 @@ unsigned long __builtin_ppc_mftb (); double __builtin_unpack_ibm128 (__ibm128, int); __ibm128 __builtin_pack_ibm128 (double, double); double __builtin_mffs (void); +double __builtin_mtfsf (const int, double); void __builtin_mtfsb0 (const int); void __builtin_mtfsb1 (const int); void __builtin_set_fpscr_rn (int); @@ -16863,7 +16864,10 @@ the most significant word on 32-bit environments. The @code{__builtin_mffs} return the value of the FPSCR register. Note, ISA 3.0 supports the @code{__builtin_mffsl()} which permits software to read the control and non-sticky status bits in the FSPCR without the higher latency associated with -accessing the sticky status bits. The +accessing the sticky status bits. The @code{__builtin_mtfsf} takes a constant +8-bit integer field mask and a double precision floating point argument +and generates the @code{mtfsf} (extended mnemonic) instruction to write new +values to selected fields of the FPSCR. The @code{__builtin_mtfsb0} and @code{__builtin_mtfsb1} take the bit to change as an argument. The valid bit range is between 0 and 31. The builtins map to the @code{mtfsb0} and @code{mtfsb1} instructions which take the argument and |