Daily bump.

7 files changed, 642 insertions, 1 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 415d7ea..2d9e425 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,156 @@
+2023-06-20  Tamar Christina  <tamar.christina@arm.com>
+
+	PR bootstrap/110324
+	* gensupport.cc (convert_syntax): Explicitly check for RTX code.
+
+2023-06-20  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64.md (stack_tie): Hard-code the first
+	register operand to the stack pointer.  Require the second register
+	operand to have the number specified in a separate const_int operand.
+	* config/aarch64/aarch64.cc (aarch64_emit_stack_tie): New function.
+	(aarch64_allocate_and_probe_stack_space): Use it.
+	(aarch64_expand_prologue, aarch64_expand_epilogue): Likewise.
+	(aarch64_expand_epilogue): Likewise.
+
+2023-06-20  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/79173
+	* tree-ssa-math-opts.cc (match_uaddc_usubc): Remember lhs of
+	IMAGPART_EXPR of arg2/arg3 and use that as arg3 if it has the right
+	type.
+
+2023-06-20  Uros Bizjak  <ubizjak@gmail.com>
+
+	* calls.h (setjmp_call_p): Change return type from int to bool.
+	* calls.cc (struct arg_data): Change "pass_on_stack" to bool.
+	(store_one_arg): Change return type from int to bool
+	and adjust function body accordingly.  Change "sibcall_failure"
+	variable to bool.
+	(finalize_must_preallocate): Ditto.  Change *must_preallocate pointer
+	argument  to bool.  Change "partial_seen" variable to bool.
+	(load_register_parameters):  Change *sibcall_failure
+	pointer argument to bool.
+	(check_sibcall_argument_overlap_1): Change return type from int to bool
+	and adjust function body accordingly.
+	(check_sibcall_argument_overlap):  Ditto.  Change
+	"mark_stored_args_map" argument to bool.
+	(emit_call_1): Change "already_popped" variable to bool.
+	(setjmp_call_p): Change return type from int to bool
+	and adjust function body accordingly.
+	(initialize_argument_information): Change *must_preallocate
+	pointer argument to bool.
+	(expand_call): Change "pcc_struct_value", "must_preallocate"
+	and "sibcall_failure" variables to bool.
+	(emit_library_call_value_1): Change "pcc_struct_value"
+	variable to bool.
+
+2023-06-20  Martin Jambor  <mjambor@suse.cz>
+
+	PR ipa/110276
+	* ipa-sra.cc (struct caller_issues): New field there_is_one.
+	(check_for_caller_issues): Set it.
+	(check_all_callers_for_issues): Check it.
+
+2023-06-20  Martin Jambor  <mjambor@suse.cz>
+
+	* ipa-prop.h (ipa_uid_to_idx_map_elt): New type.
+	(struct ipcp_transformation): Rearrange members	according to
+	C++ class coding convention, add m_uid_to_idx,
+	get_param_index and maybe_create_parm_idx_map.
+	* ipa-cp.cc (ipcp_transformation::get_param_index): New function.
+	(compare_uids): Likewise.
+	(ipcp_transformation::maype_create_parm_idx_map): Likewise.
+	* ipa-prop.cc (ipcp_get_parm_bits): Use get_param_index.
+	(ipcp_update_bits): Accept TS as a parameter, assume it is not NULL.
+	(ipcp_update_vr): Likewise.
+	(ipcp_transform_function): Call, maybe_create_parm_idx_map of TS, bail
+	out quickly if empty, pass it to ipcp_update_bits and ipcp_update_vr.
+
+2023-06-20  Carl Love  <cel@us.ibm.com>
+
+	* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin):
+	Rename CODE_FOR_xsxsigqp_tf to CODE_FOR_xsxsigqp_tf_ti.
+	Rename CODE_FOR_xsxsigqp_kf to CODE_FOR_xsxsigqp_kf_ti.
+	Rename CCDE_FOR_xsxexpqp_tf to CODE_FOR_xsxexpqp_tf_di.
+	Rename CODE_FOR_xsxexpqp_kf to CODE_FOR_xsxexpqp_kf_di.
+	(CODE_FOR_xsxexpqp_kf_v2di, CODE_FOR_xsxsigqp_kf_v1ti,
+	CODE_FOR_xsiexpqp_kf_v2di): Add case statements.
+	* config/rs6000/rs6000-builtins.def
+	(__builtin_vsx_scalar_extract_exp_to_vec,
+	__builtin_vsx_scalar_extract_sig_to_vec,
+	__builtin_vsx_scalar_insert_exp_vqp): Add new builtin definitions.
+	Rename xsxexpqp_kf, xsxsigqp_kf, xsiexpqp_kf to xsexpqp_kf_di,
+	xsxsigqp_kf_ti, xsiexpqp_kf_di respectively.
+	* config/rs6000/rs6000-c.cc (altivec_resolve_overloaded_builtin):
+	Update case RS6000_OVLD_VEC_VSIE to handle MODE_VECTOR_INT for new
+	overloaded instance. Update comments.
+	* config/rs6000/rs6000-overload.def
+	(__builtin_vec_scalar_insert_exp): Add new overload definition with
+	vector arguments.
+	(scalar_extract_exp_to_vec, scalar_extract_sig_to_vec): New
+	overloaded definitions.
+	* config/rs6000/vsx.md (V2DI_DI): New mode iterator.
+	(DI_to_TI): New mode attribute.
+	Rename xsxexpqp_<mode> to sxexpqp_<IEEE128:mode>_<V2DI_DI:mode>.
+	Rename xsxsigqp_<mode> to xsxsigqp_<IEEE128:mode>_<VEC_TI:mode>.
+	Rename xsiexpqp_<mode> to xsiexpqp_<IEEE128:mode>_<V2DI_DI:mode>.
+	* doc/extend.texi (scalar_extract_exp_to_vec,
+	scalar_extract_sig_to_vec): Add documentation for new builtins.
+	(scalar_insert_exp): Add new overloaded builtin definition.
+
+2023-06-20  Li Xu  <xuli1@eswincomputing.com>
+
+	* config/riscv/riscv.cc (riscv_regmode_natural_size): set the natural
+	size of vector mask mode to one rvv register.
+
+2023-06-20  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	* config/riscv/riscv-v.cc (expand_const_vector): Optimize codegen.
+
+2023-06-20  Lehua Ding  <lehua.ding@rivai.ai>
+
+	* config/riscv/riscv.cc (riscv_arg_has_vector): Add default
+	switch handler.
+
+2023-06-20  Richard Biener  <rguenther@suse.de>
+
+	* tree-ssa-dse.cc (dse_classify_store): When we found
+	no defs and the basic-block with the original definition
+	ends in __builtin_unreachable[_trap] the store is dead.
+
+2023-06-20  Richard Biener  <rguenther@suse.de>
+
+	* tree-ssa-phiprop.cc (phiprop_insert_phi): For simple loads
+	keep the virtual SSA form up-to-date.
+
+2023-06-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64-simd.md (*aarch64_addp_same_reg<mode>):
+	New define_insn_and_split.
+
+2023-06-20  Tamar Christina  <tamar.christina@arm.com>
+
+	* config/aarch64/aarch64.md (*mov<mode>_aarch64): Drop test comment.
+
+2023-06-20  Jan Beulich  <jbeulich@suse.com>
+
+	* config/i386/sse.md (vec_dupv2di): Correct %vmovddup input
+	constraint. Add new AVX512F alternative.
+
+2023-06-20  Richard Biener  <rguenther@suse.de>
+
+	PR debug/110295
+	* dwarf2out.cc (process_scope_var): Continue processing
+	the decl after setting a parent in case the existing DIE
+	was in limbo.
+
+2023-06-20  Lehua Ding  <lehua.ding@rivai.ai>
+
+	* config/riscv/riscv.cc (riscv_scalable_vector_type_p): Delete.
+	(riscv_arg_has_vector): Simplify.
+	(riscv_pass_in_vector_p): Adjust warning message.
+
 2023-06-19  Jin Ma  <jinma@linux.alibaba.com>
 
 	* config/riscv/riscv.cc (riscv_compute_frame_info): Allocate frame for FCSR.
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 414ba4c..047f836 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230620
+20230621
diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog
index c3035d1..5110f3d 100644
--- a/gcc/ada/ChangeLog
+++ b/gcc/ada/ChangeLog
@@ -1,3 +1,223 @@
+2023-06-20  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* gcc-interface/decl.cc (gnat_to_gnu_entity) <E_Variable>: Pass
+	the NULL_TREE explicitly and test imported_p in lieu of
+	Is_Imported. <E_Function>: Remove public_flag local variable and
+	make extern_flag local variable a constant.
+
+2023-06-20  Yannick Moy  <moy@adacore.com>
+
+	* sem_res.adb (Resolve_Call): Fix change that replaced test for
+	quantified expressions by the test for potentially unevaluated
+	contexts. Both should be performed.
+
+2023-06-20  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* exp_ch7.adb (Convert_View): Detect more cases of mismatches for
+	private types and use Implementation_Base_Type as main criterion.
+	* gen_il-fields.ads (Opt_Field_Enum): Add
+	Has_Secondary_Private_View
+	* gen_il-gen-gen_nodes.adb (N_Expanded_Name): Likewise.
+	(N_Direct_Name): Likewise.
+	(N_Op): Likewise.
+	* sem_ch12.ads (Check_Private_View): Document the usage of second
+	flag Has_Secondary_Private_View.
+	* sem_ch12.adb (Get_Associated_Entity): New function to retrieve
+	the ultimate associated entity, if any.
+	(Check_Private_View): Implement Has_Secondary_Private_View
+	support.
+	(Copy_Generic_Node): Remove specific treatment for Component_Type
+	of an array type and Designated_Type of an access type. Add
+	specific treatment for comparison and equality operators, as well
+	as iterator and loop parameter specifications.
+	(Instantiate_Type): Implement Has_Secondary_Private_View support.
+	(Requires_Delayed_Save): Call Get_Associated_Entity.
+	(Set_Global_Type): Implement Has_Secondary_Private_View support.
+	* sem_ch6.adb (Conforming_Types): Remove bypass for private views
+	in instances.
+	* sem_type.adb (Covers): Return true if Is_Subtype_Of does so.
+	Remove bypass for private views in instances.
+	(Specific_Type): Likewise.
+	* sem_util.adb (Wrong_Type): Likewise.
+	* sinfo.ads (Has_Secondary_Private_View): Document new flag.
+
+2023-06-20  Ronan Desplanques  <desplanques@adacore.com>
+
+	* libgnarl/s-mudido.ads: Remove outdated comment.
+
+2023-06-20  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* doc/gnat_ugn/gnat_and_program_execution.rst (Overflows in GNAT)
+	<Default Settings>: Remove obsolete paragraph about -gnato.
+	<Implementation Notes>: Replace CHECKED with STRICT.
+	* gnat_ugn.texi: Regenerate.
+
+2023-06-20  Yannick Moy  <moy@adacore.com>
+
+	* sem_util.adb (Check_Result_And_Post_State): Do not warn in cases
+	where the warning could be spurious.
+
+2023-06-20  Yannick Moy  <moy@adacore.com>
+
+	* err_vars.ads (Error_Msg_Code): New variable for error codes.
+	* errout.adb (Error_Msg_Internal): Display continuation message
+	when an error code was present.
+	(Set_Msg_Text): Handle character sequence [] for error codes.
+	* errout.ads: Document new insertion sequence [].
+	(Error_Msg_Code): New renaming.
+	* erroutc.adb (Prescan_Message): Detect presence of error code.
+	(Set_Msg_Insertion_Code): Handle new insertion sequence [].
+	* erroutc.ads (Has_Error_Code): New variable for prescan.
+	(Set_Msg_Insertion_Code): Handle new insertion sequence [].
+	* contracts.adb (Check_Type_Or_Object_External_Properties):
+	Replace reference to SPARK RM section by an error code.
+	* sem_elab.adb (SPARK_Processor): Same.
+	* sem_prag.adb (Check_Missing_Part_Of): Same.
+	* sem_res.adb (Resolve_Actuals, Resolve_Entity_Name): Same.
+
+2023-06-20  Piotr Trojanek  <trojanek@adacore.com>
+
+	* sem_res.adb (Resolve_Entity_Name): Handle Range like First and Last.
+
+2023-06-20  Jose Ruiz  <ruiz@adacore.com>
+
+	* doc/gnat_ugn/the_gnat_compilation_model.rst
+	(Partition-Wide Settings): add this subsection to document
+	configuration settings made by the Ada run time.
+	* gnat_ugn.texi: Regenerate.
+
+2023-06-20  Piotr Trojanek  <trojanek@adacore.com>
+
+	* sem_res.adb (Resolve_Entity_Name): Ignore implicit loop scopes
+	introduced by quantified expressions.
+
+2023-06-20  Bob Duff  <duff@adacore.com>
+
+	* sem_ch3.adb (Analyze_Object_Declaration): Remove predicate-check
+	generation if there is an address clause. These are unnecessary,
+	and cause gigi to crash.
+	* exp_util.ads (Following_Address_Clause): Remove obsolete "???"
+	comments. The suggested changes were done long ago.
+
+2023-06-20  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* einfo.ads (Has_Private_Ancestor): Fix inaccuracy in description.
+	* sem_ch12.adb (Check_Actual_Type): Do not switch the view of the
+	type if it has a private ancestor.
+
+2023-06-20  Daniel King  <dmking@adacore.com>
+
+	* libgnat/i-cheri.ads: Add CHERI intrinsics and helper functions.
+	* libgnat/i-cheri.adb: Likewise
+
+2023-06-20  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* exp_ch7.adb (Convert_View): Remove Ind parameter and adjust.
+	* sem_ch12.adb (Check_Generic_Actuals): Check the type of both in
+	and in out actual objects, as well as the type of formal parameters
+	of actual subprograms.  Extend the condition under which the views
+	are swapped to nested generic constructs.
+	(Save_References_In_Identifier): Call Set_Global_Type on a global
+	identifier rewritten as an explicit dereference, either directly
+	or after having first been rewritten as a function call.
+	(Save_References_In_Operator): Set N2 unconditionally and reuse it.
+	* sem_ch3.adb (Build_Derived_Record_Type): Add missing comment.
+	* sem_res.adb (Resolve_Implicit_Dereference): Remove special bypass
+	for private views in instances.
+
+2023-06-20  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* exp_aggr.adb (Convert_To_Assignments): Tweak comment.
+	(Expand_Array_Aggregate): Do not delay the expansion if the parent
+	node is a container aggregate.
+
+2023-06-20  Ghjuvan Lacambre  <lacambre@adacore.com>
+
+	* errout.adb (Output_Messages): Fix loop termination condition.
+
+2023-06-20  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* doc/gnat_ugn/building_executable_programs_with_gnat.rst (Compiler
+	Switches): Document -gnateH.
+	* opt.ads (Reverse_Bit_Order_Threshold): New variable.
+	* sem_ch13.adb (Adjust_Record_For_Reverse_Bit_Order): Use its value
+	if it is nonnegative instead of System_Max_Integer_Size.
+	* switch-c.adb (Scan_Front_End_Switches): Deal with -gnateH.
+	* usage.adb (Usage): Print -gnateH.
+	* gnat_ugn.texi: Regenerate.
+
+2023-06-20  Yannick Moy  <moy@adacore.com>
+
+	* libgnat/s-aridou.adb (Scaled_Divide): Add assertions.
+	* libgnat/s-valuti.adb: Add Loop_Variant.
+	* libgnat/s-valuti.ads: Add Exceptional_Cases on No_Return
+	procedure.
+
+2023-06-20  Marc Poulhiès  <poulhies@adacore.com>
+
+	* sem_ch3.adb (Build_Derived_Record_Type): Use full view as
+	Parent_Base if needed.
+
+2023-06-20  Ghjuvan Lacambre  <lacambre@adacore.com>
+
+	* lib-load.adb (Load_Unit): Pass Error_Node to calls to Error_Msg.
+
+2023-06-20  Claire Dross  <dross@adacore.com>
+
+	* libgnat/a-strfix.ads: Replace Might_Not_Return annotations by
+	Exceptional_Cases and Always_Terminates aspects.
+	* libgnat/a-tideio.ads: Idem.
+	* libgnat/a-tienio.ads: Idem.
+	* libgnat/a-tifiio.ads: Idem.
+	* libgnat/a-tiflio.ads: Idem.
+	* libgnat/a-tiinio.ads: Idem.
+	* libgnat/a-timoio.ads: Idem.
+	* libgnat/a-textio.ads: Idem. Also mark functions Name, Col, Line,
+	and Page as out of SPARK as they might raise Layout_Error.
+	* libgnarl/a-reatim.ads: Replace Always_Return annotations by
+	Always_Terminates aspects.
+	* libgnat/a-chahan.ads: Idem.
+	* libgnat/a-nbnbig.ads: Idem.
+	* libgnat/a-nbnbin.ads: Idem.
+	* libgnat/a-nbnbre.ads: Idem.
+	* libgnat/a-ngelfu.ads: Idem.
+	* libgnat/a-nlelfu.ads: Idem.
+	* libgnat/a-nllefu.ads: Idem.
+	* libgnat/a-nselfu.ads: Idem.
+	* libgnat/a-nuelfu.ads: Idem.
+	* libgnat/a-strbou.ads: Idem.
+	* libgnat/a-strmap.ads: Idem.
+	* libgnat/a-strsea.ads: Idem.
+	* libgnat/a-strsup.ads: Idem.
+	* libgnat/a-strunb.ads: Idem.
+	* libgnat/a-strunb__shared.ads: Idem.
+	* libgnat/g-souinf.ads: Idem.
+	* libgnat/i-c.ads: Idem.
+	* libgnat/interfac.ads: Idem.
+	* libgnat/interfac__2020.ads: Idem.
+	* libgnat/s-aridou.adb: Idem.
+	* libgnat/s-arit32.adb: Idem.
+	* libgnat/s-atacco.ads: Idem.
+	* libgnat/s-spcuop.ads: Idem.
+	* libgnat/s-stoele.ads: Idem.
+	* libgnat/s-vaispe.ads: Idem.
+	* libgnat/s-vauspe.ads: Idem.
+	* libgnat/i-cstrin.ads: Add a precondition instead of a
+	Might_Not_Return annotation.
+
+2023-06-20  Javier Miranda  <miranda@adacore.com>
+
+	* sem_ch4.adb
+	(Try_Selected_Component_In_Instance): New subprogram; factorizes
+	existing code.
+	(Find_Component_In_Instance) Moved inside the new subprogram.
+	(Analyze_Selected_Component): Invoke the new subprogram before
+	trying the Object.Operation notation.
+
+2023-06-20  Ronan Desplanques  <desplanques@adacore.com>
+
+	* libgnat/a-calfor.adb (Time_Of): Fix handling of special case.
+
 2023-06-15  Marek Polacek  <polacek@redhat.com>
 
 	* gcc-interface/Make-lang.in (ALL_ADAFLAGS): Remove NO_PIE_CFLAGS.  Add
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index f5e06bd..147fb1d 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,13 @@
+2023-06-20  Tobias Burnus  <tobias@codesourcery.com>
+
+	* dump-parse-tree.cc (show_omp_namelist): Fix dump of the allocator
+	modifier of OMP_LIST_ALLOCATE.
+
+2023-06-20  Tobias Burnus  <tobias@codesourcery.com>
+
+	* match.cc (gfc_match_char): Match with '%S' a symbol
+	with host_assoc = 1.
+
 2023-06-19  Tobias Burnus  <tobias@codesourcery.com>
 
 	* intrinsic.texi (OpenMP Modules OMP_LIB and OMP_LIB_KINDS): Also
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 904242d..3e3f0ad 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,242 @@
+2023-06-20  Lewis Hyatt  <lhyatt@gmail.com>
+
+	PR c++/66290
+	* c-c++-common/cpp/macro-ranges.c: New test.
+	* c-c++-common/cpp/line-2.c: Adapt to check for column information
+	on macro-related libcpp warnings.
+	* c-c++-common/cpp/line-3.c: Likewise.
+	* c-c++-common/cpp/macro-arg-count-1.c: Likewise.
+	* c-c++-common/cpp/pr58844-1.c: Likewise.
+	* c-c++-common/cpp/pr58844-2.c: Likewise.
+	* c-c++-common/cpp/warning-zero-location.c: Likewise.
+	* c-c++-common/pragma-diag-14.c: Likewise.
+	* c-c++-common/pragma-diag-15.c: Likewise.
+	* g++.dg/modules/macro-2_d.C: Likewise.
+	* g++.dg/modules/macro-4_d.C: Likewise.
+	* g++.dg/modules/macro-4_e.C: Likewise.
+	* g++.dg/spellcheck-macro-ordering.C: Likewise.
+	* gcc.dg/builtin-redefine.c: Likewise.
+	* gcc.dg/cpp/Wunused.c: Likewise.
+	* gcc.dg/cpp/redef2.c: Likewise.
+	* gcc.dg/cpp/redef3.c: Likewise.
+	* gcc.dg/cpp/redef4.c: Likewise.
+	* gcc.dg/cpp/ucnid-11-utf8.c: Likewise.
+	* gcc.dg/cpp/ucnid-11.c: Likewise.
+	* gcc.dg/cpp/undef2.c: Likewise.
+	* gcc.dg/cpp/warn-redefined-2.c: Likewise.
+	* gcc.dg/cpp/warn-redefined.c: Likewise.
+	* gcc.dg/cpp/warn-unused-macros-2.c: Likewise.
+	* gcc.dg/cpp/warn-unused-macros.c: Likewise.
+
+2023-06-20  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* gcc.target/aarch64/sve/pcs/args_1.c: Match moves from the stack
+	pointer to indirect argument registers and allow either to be used
+	as the base register in subsequent stores.
+	* gcc.target/aarch64/sve/pcs/args_8.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_2.c: Allow the store of the
+	indirect argument to happen via the argument register or the
+	stack pointer.
+	* gcc.target/aarch64/sve/pcs/args_3.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_4.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_be_bf16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_be_f16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_be_f32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_be_f64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_be_s16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_be_s32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_be_s64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_be_s8.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_be_u16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_be_u32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_be_u64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_be_u8.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_le_bf16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_le_f16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_le_f32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_le_f64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_le_s16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_le_s32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_le_s64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_le_s8.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_le_u16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_le_u32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_le_u64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_le_u8.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_be_bf16.c: Disable
+	-fcprop-registers and combine.
+	* gcc.target/aarch64/sve/pcs/args_6_be_f16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_be_f32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_be_f64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_be_s16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_be_s32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_be_s64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_be_s8.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_be_u16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_be_u32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_be_u64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_be_u8.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_le_bf16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_le_f16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_le_f32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_le_f64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_le_s16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_le_s32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_le_s64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_le_s8.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_le_u16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_le_u32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_le_u64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_le_u8.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_1.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_2_f16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_2_f32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_2_f64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_2_s16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_2_s32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_2_s64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_2_s8.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_2_u16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_2_u32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_2_u64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_2_u8.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_3_nosc.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_3_sc.c: Likewise.
+
+2023-06-20  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/79173
+	* g++.target/i386/pr79173-1.C: New test.
+
+2023-06-20  Martin Jambor  <mjambor@suse.cz>
+
+	PR ipa/110276
+	* gcc.dg/ipa/pr110276.c: New test.
+
+2023-06-20  Carl Love  <cel@us.ibm.com>
+
+	* gcc.target/powerpc/bfp/scalar-extract-exp-8.c: New test case.
+	* gcc.target/powerpc/bfp/scalar-extract-sig-8.c: New test case.
+	* gcc.target/powerpc/bfp/scalar-insert-exp-16.c: New test case.
+
+2023-06-20  Robin Dapp  <rdapp@ventanamicro.com>
+
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c: Add
+	-mabi=lp64d.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c: Dito.
+
+2023-06-20  Li Xu  <xuli1@eswincomputing.com>
+
+	* gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c: New test.
+
+2023-06-20  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	* gcc.target/riscv/rvv/autovec/partial/slp-1.c: Adapt testcase.
+	* gcc.target/riscv/rvv/autovec/partial/slp-16.c: New test.
+	* gcc.target/riscv/rvv/autovec/partial/slp_run-16.c: New test.
+
+2023-06-20  Robin Dapp  <rdapp@ventanamicro.com>
+
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c: Add
+	-Wno-psabi.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c:
+	Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c: Dito.
+
+2023-06-20  Robin Dapp  <rdapp@ventanamicro.com>
+
+	* gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Add
+	-ffast-math.
+	* gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Remove
+	-ffast-math
+	* gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: Check for
+	vfmul.
+	* gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: Dito.
+
+2023-06-20  Richard Biener  <rguenther@suse.de>
+
+	* gcc.dg/tree-ssa/ssa-dse-47.c: New testcase.
+	* c-c++-common/asan/pr106558.c: Avoid undefined behavior
+	due to missing return.
+
+2023-06-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* gcc.target/aarch64/simd/addp-same-low_1.c: New test.
+
+2023-06-20  Jan Beulich  <jbeulich@suse.com>
+
+	* gcc.target/i386/avx512f-dupv2di.c: New test.
+
+2023-06-20  Richard Biener  <rguenther@suse.de>
+
+	PR debug/110295
+	* g++.dg/debug/pr110295.C: New testcase.
+
+2023-06-20  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c: Fix fail.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-zvfh-run.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-zvfh-run.c: Ditto.
+
+2023-06-20  Lehua Ding  <lehua.ding@rivai.ai>
+
+	* gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: Add -Wno-psabi option.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Ditto.
+	* gcc.target/riscv/rvv/base/pr110119-1.c: Ditto.
+	* gcc.target/riscv/rvv/base/pr110119-2.c: Ditto.
+	* gcc.target/riscv/vector-abi-1.c: Ditto.
+	* gcc.target/riscv/vector-abi-2.c: Ditto.
+	* gcc.target/riscv/vector-abi-3.c: Ditto.
+	* gcc.target/riscv/vector-abi-4.c: Ditto.
+	* gcc.target/riscv/vector-abi-5.c: Ditto.
+	* gcc.target/riscv/vector-abi-6.c: Ditto.
+	* gcc.target/riscv/vector-abi-7.c: New test.
+	* gcc.target/riscv/vector-abi-8.c: New test.
+	* gcc.target/riscv/vector-abi-9.c: New test.
+
 2023-06-19  Jin Ma  <jinma@linux.alibaba.com>
 
 	* gcc.target/riscv/interrupt-fcsr-1.c: New test.
diff --git a/libcpp/ChangeLog b/libcpp/ChangeLog
index 98fabcf..48acad7 100644
--- a/libcpp/ChangeLog
+++ b/libcpp/ChangeLog
@@ -1,3 +1,16 @@
+2023-06-20  Lewis Hyatt  <lhyatt@gmail.com>
+
+	PR c++/66290
+	* macro.cc (_cpp_create_definition): Add location argument.
+	* internal.h (_cpp_create_definition): Adjust prototype.
+	* directives.cc (do_define): Pass new location argument to
+	_cpp_create_definition.
+	(do_undef): Stop passing inferior location to cpp_warning_with_line;
+	the default from cpp_warning is better.
+	(cpp_pop_definition): Pass new location argument to
+	_cpp_create_definition.
+	* pch.cc (cpp_read_state): Likewise.
+
 2023-06-19  Ben Boeckel  <ben.boeckel@kitware.com>
 
 	* charset.cc: Reject encodings of codepoints above 0x10FFFF.
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 57e0a0a..afeacbc 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,9 @@
+2023-06-20  Jonathan Wakely  <jwakely@redhat.com>
+
+	* include/std/array (to_array(T(&)[N])): Remove redundant
+	condition.
+	(to_array(T(&&)[N])): Remove redundant std::move.
+
 2023-06-16  Alexandre Oliva  <oliva@adacore.com>
 
 	* testsuite/20_util/from_chars/4.cc: Skip long double on