rtl.def: Add extra fourth optional field to define_cond_exec.

2013-06-04  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* rtl.def: Add extra fourth optional field to define_cond_exec.
	* gensupport.c (process_one_cond_exec): Process attributes from
	define_cond_exec.
	* doc/md.texi: Document fourth field in define_cond_exec.

From-SVN: r199640

4 files changed, 34 insertions, 3 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cae512a..f845fbd 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2013-06-04  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* rtl.def: Add extra fourth optional field to define_cond_exec.
+	* gensupport.c (process_one_cond_exec): Process attributes from
+	define_cond_exec.
+	* doc/md.texi: Document fourth field in define_cond_exec.
+
 2013-06-04  Eric Botcazou  <ebotcazou@adacore.com>
 
 	* expmed.c (extract_bit_field_1): In the larger-than-a-word case, factor
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 8c72c85..3b20991 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -8866,7 +8866,8 @@ can be quite tedious to describe these forms directly in the
 (define_cond_exec
   [@var{predicate-pattern}]
   "@var{condition}"
-  "@var{output-template}")
+  "@var{output-template}"
+  "@var{optional-insn-attribues}")
 @end smallexample
 
 @var{predicate-pattern} is the condition that must be true for the
@@ -8887,6 +8888,13 @@ In order to handle the general case, there is a global variable
 @code{current_insn_predicate} that will contain the entire predicate
 if the current insn is predicated, and will otherwise be @code{NULL}.
 
+@var{optional-insn-attributes} is an optional vector of attributes that gets
+appended to the insn attributes of the produced cond_exec rtx. It can
+be used to add some distinguishing attribute to cond_exec rtxs produced
+that way. An example usage would be to use this attribute in conjunction
+with attributes on the main pattern to disable particular alternatives under
+certain conditions.
+
 When @code{define_cond_exec} is used, an implicit reference to
 the @code{predicable} instruction attribute is made.
 @xref{Insn Attributes}.  This attribute must be a boolean (i.e.@: have
diff --git a/gcc/gensupport.c b/gcc/gensupport.c
index 1092bd8..19b9240 100644
--- a/gcc/gensupport.c
+++ b/gcc/gensupport.c
@@ -1717,6 +1717,21 @@ process_one_cond_exec (struct queue_elem *ce_elem)
 	  XVECEXP (insn, 1, 0) = pattern;
 	}
 
+       if (XVEC (ce_elem->data, 3) != NULL)
+	{
+	  rtvec attributes = rtvec_alloc (XVECLEN (insn, 4)
+	                                  + XVECLEN (ce_elem->data, 3));
+	  int i = 0;
+	  int j = 0;
+	  for (i = 0; i < XVECLEN (insn, 4); i++)
+	    RTVEC_ELT (attributes, i) = XVECEXP (insn, 4, i);
+
+	  for (j = 0; j < XVECLEN (ce_elem->data, 3); j++, i++)
+	    RTVEC_ELT (attributes, i) = XVECEXP (ce_elem->data, 3, j);
+
+	  XVEC (insn, 4) = attributes;
+	}
+
       XSTR (insn, 2) = alter_test_for_insn (ce_elem, insn_elem);
       XTMPL (insn, 3) = alter_output_for_insn (ce_elem, insn_elem,
 					      alternatives, max_operand);
diff --git a/gcc/rtl.def b/gcc/rtl.def
index f8aea32..b4ce1b9 100644
--- a/gcc/rtl.def
+++ b/gcc/rtl.def
@@ -962,8 +962,9 @@ DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
       relational operator.  Operands should have only one alternative.
    1: A C expression giving an additional condition for recognizing
       the generated pattern.
-   2: A template or C code to produce assembler output.  */
-DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA)
+   2: A template or C code to produce assembler output.
+   3: A vector of attributes to append to the resulting cond_exec insn.  */
+DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "EssV", RTX_EXTRA)
 
 /* Definition of an operand predicate.  The difference between
    DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will