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| author | Richard Sandiford <rsandifo@redhat.com> | 2004-05-28 10:04:48 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2004-05-28 10:04:48 +0000 |
| commit | a97a3e73b5f3d0bde5350da0ffad08aa1572d3c1 (patch) | |
| tree | f684bf8823cf90f97a781deb3eb06620d61ed8c8 | |
| parent | 6c2511d34e54923dd7c2195dff882ffcffaa9631 (diff) | |
| download | gcc-a97a3e73b5f3d0bde5350da0ffad08aa1572d3c1.zip gcc-a97a3e73b5f3d0bde5350da0ffad08aa1572d3c1.tar.gz gcc-a97a3e73b5f3d0bde5350da0ffad08aa1572d3c1.tar.bz2 | |
mips.md (extendsidi2): Tie the source and destination of the register alternative.
* config/mips/mips.md (extendsidi2): Tie the source and destination
of the register alternative. Split it into nothing.
From-SVN: r82359
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 25 |
2 files changed, 24 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 618d6d4..31f9531 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2004-05-28 Richard Sandiford <rsandifo@redhat.com> + * config/mips/mips.md (extendsidi2): Tie the source and destination + of the register alternative. Split it into nothing. + +2004-05-28 Richard Sandiford <rsandifo@redhat.com> + * rtl.h (skip_consecutive_labels): Declare. * emit-rtl.c (skip_consecutive_labels): New function. * reorg.c (relax_delay_slots, dbr_schedule): Use it. diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 022562d..3235ff5 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -3405,16 +3405,29 @@ dsrl\t%3,%3,1\n\ ;; Extension insns. ;; Those for integer source operand are ordered widest source type first. -(define_insn "extendsidi2" +;; When TARGET_64BIT, all SImode integer registers should already be in +;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can +;; therefore get rid of register->register instructions if we constrain +;; the source to be in the same register as the destination. +;; +;; The register alternative has type "arith" so that the pre-reload +;; scheduler will treat it as a move. This reflects what happens if +;; the register alternative needs a reload. +(define_insn_and_split "extendsidi2" [(set (match_operand:DI 0 "register_operand" "=d,d") - (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] + (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))] "TARGET_64BIT" "@ - sll\t%0,%1,0 + # lw\t%0,%1" - [(set_attr "type" "shift,load") - (set_attr "mode" "DI") - (set_attr "extended_mips16" "yes,*")]) + "&& reload_completed && register_operand (operands[1], VOIDmode)" + [(const_int 0)] +{ + emit_note (NOTE_INSN_DELETED); + DONE; +} + [(set_attr "type" "arith,load") + (set_attr "mode" "DI")]) ;; These patterns originally accepted general_operands, however, slightly ;; better code is generated by only accepting register_operands, and then |