aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorJoe Ramsay <Joe.Ramsay@arm.com>2020-08-19 12:34:06 +0000
committerJoe Ramsay <joe.ramsay@arm.com>2020-08-20 15:27:09 +0000
commit91d206adfe39ce063f6a5731b92a03c05e82e94a (patch)
treec3a8f26e20ff9b23e0b00fddc29a4dd7dc152dfb
parentf9b9832837b65046a8f01c18597cf615ff61db40 (diff)
downloadgcc-91d206adfe39ce063f6a5731b92a03c05e82e94a.zip
gcc-91d206adfe39ce063f6a5731b92a03c05e82e94a.tar.gz
gcc-91d206adfe39ce063f6a5731b92a03c05e82e94a.tar.bz2
arm: Require MVE memory operand for destination of vst1q intrinsic
Previously, the machine description patterns for vst1q accepted a generic memory operand for the destination, which could lead to an unrecognised builtin when expanding vst1q* intrinsics. This change fixes the pattern to only accept MVE memory operands. gcc/ChangeLog: PR target/96683 * config/arm/mve.md (mve_vst1q_f<mode>): Require MVE memory operand for destination. (mve_vst1q_<supf><mode>): Likewise. gcc/testsuite/ChangeLog: PR target/96683 * gcc.target/arm/mve/intrinsics/vst1q_f16.c: New test. * gcc.target/arm/mve/intrinsics/vst1q_s16.c: New test. * gcc.target/arm/mve/intrinsics/vst1q_s8.c: New test. * gcc.target/arm/mve/intrinsics/vst1q_u16.c: New test. * gcc.target/arm/mve/intrinsics/vst1q_u8.c: New test.
-rw-r--r--gcc/config/arm/mve.md4
-rw-r--r--gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c10
-rw-r--r--gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c10
-rw-r--r--gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c10
-rw-r--r--gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c10
-rw-r--r--gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c10
6 files changed, 37 insertions, 17 deletions
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 9758862..465b39a 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -9330,7 +9330,7 @@
[(set_attr "length" "4")])
(define_expand "mve_vst1q_f<mode>"
- [(match_operand:<MVE_CNVT> 0 "memory_operand")
+ [(match_operand:<MVE_CNVT> 0 "mve_memory_operand")
(unspec:<MVE_CNVT> [(match_operand:MVE_0 1 "s_register_operand")] VST1Q_F)
]
"TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
@@ -9340,7 +9340,7 @@
})
(define_expand "mve_vst1q_<supf><mode>"
- [(match_operand:MVE_2 0 "memory_operand")
+ [(match_operand:MVE_2 0 "mve_memory_operand")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand")] VST1Q)
]
"TARGET_HAVE_MVE"
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c
index 363b4ca..312b746 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c
@@ -10,12 +10,16 @@ foo (float16_t * addr, float16x8_t value)
vst1q_f16 (addr, value);
}
-/* { dg-final { scan-assembler "vstrh.16" } } */
-
void
foo1 (float16_t * addr, float16x8_t value)
{
vst1q (addr, value);
}
-/* { dg-final { scan-assembler "vstrh.16" } } */
+/* { dg-final { scan-assembler-times "vstrh.16" 2 } } */
+
+void
+foo2 (float16_t a, float16x8_t x)
+{
+ vst1q (&a, x);
+}
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c
index 37c4713..cd14e2c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c
@@ -10,12 +10,16 @@ foo (int16_t * addr, int16x8_t value)
vst1q_s16 (addr, value);
}
-/* { dg-final { scan-assembler "vstrh.16" } } */
-
void
foo1 (int16_t * addr, int16x8_t value)
{
vst1q (addr, value);
}
-/* { dg-final { scan-assembler "vstrh.16" } } */
+/* { dg-final { scan-assembler-times "vstrh.16" 2 } } */
+
+void
+foo2 (int16_t a, int16x8_t x)
+{
+ vst1q (&a, x);
+}
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c
index fe5edea..0004c80 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c
@@ -10,12 +10,16 @@ foo (int8_t * addr, int8x16_t value)
vst1q_s8 (addr, value);
}
-/* { dg-final { scan-assembler "vstrb.8" } } */
-
void
foo1 (int8_t * addr, int8x16_t value)
{
vst1q (addr, value);
}
-/* { dg-final { scan-assembler "vstrb.8" } } */
+/* { dg-final { scan-assembler-times "vstrb.8" 2 } } */
+
+void
+foo2 (int8_t a, int8x16_t x)
+{
+ vst1q (&a, x);
+}
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c
index a4c8c1a..248e7ce 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c
@@ -10,12 +10,16 @@ foo (uint16_t * addr, uint16x8_t value)
vst1q_u16 (addr, value);
}
-/* { dg-final { scan-assembler "vstrh.16" } } */
-
void
foo1 (uint16_t * addr, uint16x8_t value)
{
vst1q (addr, value);
}
-/* { dg-final { scan-assembler "vstrh.16" } } */
+/* { dg-final { scan-assembler-times "vstrh.16" 2 } } */
+
+void
+foo2 (uint16_t a, uint16x8_t x)
+{
+ vst1q (&a, x);
+}
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c
index bf20b6d..f8b48a6 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c
@@ -10,12 +10,16 @@ foo (uint8_t * addr, uint8x16_t value)
vst1q_u8 (addr, value);
}
-/* { dg-final { scan-assembler "vstrb.8" } } */
-
void
foo1 (uint8_t * addr, uint8x16_t value)
{
vst1q (addr, value);
}
-/* { dg-final { scan-assembler "vstrb.8" } } */
+/* { dg-final { scan-assembler-times "vstrb.8" 2 } } */
+
+void
+foo2 (uint8_t a, uint8x16_t x)
+{
+ vst1q (&a, x);
+}