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| author | Maciej W. Rozycki <macro@embecosm.com> | 2022-06-13 22:29:45 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@embecosm.com> | 2022-06-13 22:29:45 +0100 |
| commit | 72b185189f914a412ae39776cd284dfaeaf2213b (patch) | |
| tree | 8013dceaa5fb31a0530c2c0146ddda168306d48c | |
| parent | 751f306688508b08842d0ab967dee8e6c3b91351 (diff) | |
| download | gcc-72b185189f914a412ae39776cd284dfaeaf2213b.zip gcc-72b185189f914a412ae39776cd284dfaeaf2213b.tar.gz gcc-72b185189f914a412ae39776cd284dfaeaf2213b.tar.bz2 | |
RISC-V: Reset the length to the default of 4 for FP comparisons
The default length for floating-point compare operations is overridden
to 8, however the FEQ.fmt, FLT.fmt, FLE.fmt machine instructions and
FGE.fmt, FGT.fmt assembly idioms the relevant RTL insns produce are all
4 bytes long each. And all the floating-point compare RTL insns that
produce multiple machine instructions explicitly set their lengths.
Remove the override then, letting the default of 4 apply for the single
instruction case.
gcc/
* config/riscv/riscv.md (length): Remove the explicit setting
for "fcmp".
| -rw-r--r-- | gcc/config/riscv/riscv.md | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 7745290..308b64d 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -231,8 +231,6 @@ (eq_attr "got" "load") (const_int 8) - (eq_attr "type" "fcmp") (const_int 8) - ;; SHIFT_SHIFTs are decomposed into two separate instructions. (eq_attr "move_type" "shift_shift") (const_int 8) |